From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45895 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PPfNj-000468-IV for qemu-devel@nongnu.org; Mon, 06 Dec 2010 13:01:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PPfNi-0007Qx-0W for qemu-devel@nongnu.org; Mon, 06 Dec 2010 13:01:47 -0500 Received: from mail-px0-f173.google.com ([209.85.212.173]:61267) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PPfNh-0007QQ-JZ for qemu-devel@nongnu.org; Mon, 06 Dec 2010 13:01:45 -0500 Received: by pxi16 with SMTP id 16so2301590pxi.4 for ; Mon, 06 Dec 2010 10:01:44 -0800 (PST) MIME-Version: 1.0 In-Reply-To: <0c3c2a6386d496eab09ec18e16657c960ad3a9d0.1291397462.git.chouteau@adacore.com> References: <5c4895c6f9c6ebd80262c494563726dd59a7ff93.1291397462.git.chouteau@adacore.com> <3ecbaf8fc01bebd2b2f2fb2c709642b2a1db7ff0.1291397462.git.chouteau@adacore.com> <7c24465a442966eba3ae4e2bb03da4463e0f8644.1291397462.git.chouteau@adacore.com> <0c3c2a6386d496eab09ec18e16657c960ad3a9d0.1291397462.git.chouteau@adacore.com> From: Blue Swirl Date: Mon, 6 Dec 2010 18:01:24 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH 6/6] [RFC] SPARCV8 asr17 register support. Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Fabien Chouteau Cc: qemu-devel@nongnu.org On Mon, Dec 6, 2010 at 9:26 AM, Fabien Chouteau wrot= e: > > Signed-off-by: Fabien Chouteau > --- > =C2=A0hw/leon3.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 =C2=A06 ++++++ > =C2=A0target-sparc/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A01 + > =C2=A0target-sparc/machine.c =C2=A0 | =C2=A0 =C2=A02 ++ > =C2=A0target-sparc/translate.c | =C2=A0 10 ++++++++++ > =C2=A04 files changed, 19 insertions(+), 0 deletions(-) > > diff --git a/hw/leon3.c b/hw/leon3.c > index ba61081..9605ce8 100644 > --- a/hw/leon3.c > +++ b/hw/leon3.c > @@ -187,6 +187,12 @@ static void main_cpu_reset(void *opaque) > =C2=A0 =C2=A0 =C2=A0 =C2=A0values */ > =C2=A0 =C2=A0 leon3_state.inst_cache_conf =3D 0x10220000; > =C2=A0 =C2=A0 leon3_state.data_cache_conf =3D 0x18220000; > + > + =C2=A0 =C2=A0/* Asr17 for Leon3 mono-processor */ > + =C2=A0 =C2=A0env->asr17 &=3D 0 << 28; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0/* CPU id */ > + =C2=A0 =C2=A0env->asr17 &=3D 1 << 8; =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= /* SPARC V8 multiply and divide available */ > + =C2=A0 =C2=A0env->asr17 &=3D env->nwindows -1; /* Number of implemented= registers > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 windows */ This is constant... > =C2=A0} > > =C2=A0static void leon3_generic_hw_init(ram_addr_t =C2=A0ram_size, > diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h > index 6020ffd..36d49fc 100644 > --- a/target-sparc/cpu.h > +++ b/target-sparc/cpu.h > @@ -341,6 +341,7 @@ typedef struct CPUSPARCState { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 from PSR) */ > =C2=A0#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32) > =C2=A0 =C2=A0 uint32_t wim; =C2=A0 =C2=A0 =C2=A0/* window invalid mask */ > + =C2=A0 =C2=A0uint32_t asr17; =C2=A0 =C2=A0/* asr17 */ ... so no new env fields are needed... > =C2=A0#endif > =C2=A0 =C2=A0 target_ulong tbr; =C2=A0/* trap base register */ > =C2=A0#if !defined(TARGET_SPARC64) > diff --git a/target-sparc/machine.c b/target-sparc/machine.c > index 752e431..c530bd3 100644 > --- a/target-sparc/machine.c > +++ b/target-sparc/machine.c > @@ -42,6 +42,7 @@ void cpu_save(QEMUFile *f, void *opaque) > =C2=A0 =C2=A0 qemu_put_be32s(f, &env->pil_in); > =C2=A0#ifndef TARGET_SPARC64 > =C2=A0 =C2=A0 qemu_put_be32s(f, &env->wim); > + =C2=A0 =C2=A0qemu_put_be32s(f, &env->asr17); ... there's also nothing to save/load... > =C2=A0 =C2=A0 /* MMU */ > =C2=A0 =C2=A0 for (i =3D 0; i < 32; i++) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_put_be32s(f, &env->mmuregs[i]); > @@ -138,6 +139,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_i= d) > =C2=A0 =C2=A0 qemu_get_be32s(f, &env->pil_in); > =C2=A0#ifndef TARGET_SPARC64 > =C2=A0 =C2=A0 qemu_get_be32s(f, &env->wim); > + =C2=A0 =C2=A0qemu_get_be32s(f, &env->asr17); > =C2=A0 =C2=A0 /* MMU */ > =C2=A0 =C2=A0 for (i =3D 0; i < 32; i++) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 qemu_get_be32s(f, &env->mmuregs[i]); > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 23f9519..65de614 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -58,6 +58,7 @@ static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu= _ver; > =C2=A0static TCGv_i32 cpu_softint; > =C2=A0#else > =C2=A0static TCGv cpu_wim; > +static TCGv cpu_asr17; > =C2=A0#endif > =C2=A0/* local register indexes (only used inside old micro ops) */ > =C2=A0static TCGv cpu_tmp0; > @@ -2049,6 +2050,8 @@ static void disas_sparc_insn(DisasContext * dc) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 rs1 =3D GET_FIELD= (insn, 13, 17); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 switch(rs1) { > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 case 0: /* rdy */ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ge= n_movl_TN_reg(rd, cpu_y); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0br= eak; > =C2=A0#ifndef TARGET_SPARC64 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 case 0x01 ... 0x0= e: /* undefined in the SPARCv8 > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0manual, r= dy on the microSPARC > @@ -2058,6 +2061,11 @@ static void disas_sparc_insn(DisasContext * dc) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 case 0x10 ... 0x1= f: /* implementation-dependent in the > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SPARCv8 m= anual, rdy on the > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0microSPAR= C II */ > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if= (rs1 =3D=3D 0x11) { /* Read %asr17 */ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0gen_movl_TN_reg(rd, cpu_asr17); Instead: r_const =3D tcg_const_tl(asr constants | dc->def->nwindows - 1); gen_movl_TN_reg(rd, r_const); tcg_temp_free(r_const);