From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=54419 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OGskL-0001xX-AO for qemu-devel@nongnu.org; Tue, 25 May 2010 07:56:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OGskJ-0005lX-KN for qemu-devel@nongnu.org; Tue, 25 May 2010 07:56:33 -0400 Received: from mail-ww0-f45.google.com ([74.125.82.45]:43913) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OGskJ-0005lO-94 for qemu-devel@nongnu.org; Tue, 25 May 2010 07:56:31 -0400 Received: by wwd20 with SMTP id 20so157315wwd.4 for ; Tue, 25 May 2010 04:56:29 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20100525113103.13135.93703.stgit@skyserv> References: <20100525113103.13135.93703.stgit@skyserv> From: Artyom Tarasenko Date: Tue, 25 May 2010 13:56:08 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH] sparc64: clean up pci bridge map Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Igor V. Kovalenko" Cc: qemu-devel@nongnu.org 2010/5/25 Igor V. Kovalenko : > From: Igor V. Kovalenko > > - remove unused host state and store pci bus pointer only > - do not map host state access into unused 1fe.10000000 range > - reorder pci region registration > - assign pci i/o region to isa_mem_base > - rename default machine (it's Ultrasparc IIi now) Just rename the machine or use another CPU too? While you are at it maybe split these two? > > Signed-off-by: Igor V. Kovalenko > --- > =A0hw/apb_pci.c | =A0 49 ++++++++++++++++++++++++++----------------------= - > =A0hw/sun4u.c =A0 | =A0 =A06 +++--- > =A02 files changed, 29 insertions(+), 26 deletions(-) > > diff --git a/hw/apb_pci.c b/hw/apb_pci.c > index 65d8ba6..b53e3c3 100644 > --- a/hw/apb_pci.c > +++ b/hw/apb_pci.c > @@ -65,7 +65,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) > > =A0typedef struct APBState { > =A0 =A0 SysBusDevice busdev; > - =A0 =A0PCIHostState host_state; > + =A0 =A0PCIBus =A0 =A0 =A0*bus; > =A0 =A0 ReadWriteHandler pci_config_handler; > =A0 =A0 uint32_t iommu[4]; > =A0 =A0 uint32_t pci_control[16]; > @@ -191,7 +191,7 @@ static void apb_pci_config_write(ReadWriteHandler *h,= pcibus_t addr, > > =A0 =A0 val =3D qemu_bswap_len(val, size); > =A0 =A0 APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr= , val); > - =A0 =A0pci_data_write(s->host_state.bus, addr, val, size); > + =A0 =A0pci_data_write(s->bus, addr, val, size); > =A0} > > =A0static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr= , > @@ -200,7 +200,7 @@ static uint32_t apb_pci_config_read(ReadWriteHandler = *h, pcibus_t addr, > =A0 =A0 uint32_t ret; > =A0 =A0 APBState *s =3D container_of(h, APBState, pci_config_handler); > > - =A0 =A0ret =3D pci_data_read(s->host_state.bus, addr, size); > + =A0 =A0ret =3D pci_data_read(s->bus, addr, size); > =A0 =A0 ret =3D qemu_bswap_len(ret, size); > =A0 =A0 APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr,= ret); > =A0 =A0 return ret; > @@ -331,37 +331,37 @@ PCIBus *pci_apb_init(target_phys_addr_t special_bas= e, > =A0 =A0 s =3D sysbus_from_qdev(dev); > =A0 =A0 /* apb_config */ > =A0 =A0 sysbus_mmio_map(s, 0, special_base); > + =A0 =A0/* PCI configuration space */ > + =A0 =A0sysbus_mmio_map(s, 1, special_base + 0x1000000ULL); > =A0 =A0 /* pci_ioport */ > - =A0 =A0sysbus_mmio_map(s, 1, special_base + 0x2000000ULL); > - =A0 =A0/* pci_config */ > - =A0 =A0sysbus_mmio_map(s, 2, special_base + 0x1000000ULL); > - =A0 =A0/* mem_data */ > - =A0 =A0sysbus_mmio_map(s, 3, mem_base); > + =A0 =A0sysbus_mmio_map(s, 2, special_base + 0x2000000ULL); > =A0 =A0 d =3D FROM_SYSBUS(APBState, s); > - =A0 =A0d->host_state.bus =3D pci_register_bus(&d->busdev.qdev, "pci", > + > + =A0 =A0d->bus =3D pci_register_bus(&d->busdev.qdev, "pci", > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0pci_apb_set_irq, pci_pbm_map_irq, d, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A00, 32); > - =A0 =A0pci_bus_set_mem_base(d->host_state.bus, mem_base); > + =A0 =A0pci_bus_set_mem_base(d->bus, mem_base); > > =A0 =A0 for (i =3D 0; i < 32; i++) { > =A0 =A0 =A0 =A0 sysbus_connect_irq(s, i, pic[i]); > =A0 =A0 } > > - =A0 =A0pci_create_simple(d->host_state.bus, 0, "pbm"); > + =A0 =A0pci_create_simple(d->bus, 0, "pbm"); > + > =A0 =A0 /* APB secondary busses */ > - =A0 =A0*bus2 =3D pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0), > + =A0 =A0*bus2 =3D pci_bridge_init(d->bus, PCI_DEVFN(1, 0), > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PCI_VENDOR_ID_SUN= , PCI_DEVICE_ID_SUN_SIMBA, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_apb_map_irq, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "Advanced PCI Bus= secondary bridge 1"); > =A0 =A0 apb_pci_bridge_init(*bus2); > > - =A0 =A0*bus3 =3D pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1), > + =A0 =A0*bus3 =3D pci_bridge_init(d->bus, PCI_DEVFN(1, 1), > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PCI_VENDOR_ID_SUN= , PCI_DEVICE_ID_SUN_SIMBA, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 pci_apb_map_irq, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "Advanced PCI Bus= secondary bridge 2"); > =A0 =A0 apb_pci_bridge_init(*bus3); > > - =A0 =A0return d->host_state.bus; > + =A0 =A0return d->bus; > =A0} > > =A0static void pci_pbm_reset(DeviceState *d) > @@ -382,7 +382,7 @@ static void pci_pbm_reset(DeviceState *d) > =A0static int pci_pbm_init_device(SysBusDevice *dev) > =A0{ > =A0 =A0 APBState *s; > - =A0 =A0int pci_mem_data, apb_config, pci_ioport, pci_config; > + =A0 =A0int pci_config, apb_config, pci_ioport; > =A0 =A0 unsigned int i; > > =A0 =A0 s =3D FROM_SYSBUS(APBState, dev); > @@ -396,20 +396,23 @@ static int pci_pbm_init_device(SysBusDevice *dev) > =A0 =A0 /* apb_config */ > =A0 =A0 apb_config =3D cpu_register_io_memory(apb_config_read, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 apb_config_write, s); > + =A0 =A0/* at region 0 */ > =A0 =A0 sysbus_init_mmio(dev, 0x10000ULL, apb_config); > - =A0 =A0/* pci_ioport */ > - =A0 =A0pci_ioport =3D cpu_register_io_memory(pci_apb_ioread, > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0 =A0pci_apb_iowrite, s); > - =A0 =A0sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); > - =A0 =A0/* pci_config */ > + > + =A0 =A0/* PCI configuration space */ > =A0 =A0 s->pci_config_handler.read =3D apb_pci_config_read; > =A0 =A0 s->pci_config_handler.write =3D apb_pci_config_write; > =A0 =A0 pci_config =3D cpu_register_io_memory_simple(&s->pci_config_handl= er); > =A0 =A0 assert(pci_config >=3D 0); > + =A0 =A0/* at region 1 */ > =A0 =A0 sysbus_init_mmio(dev, 0x1000000ULL, pci_config); > - =A0 =A0/* mem_data */ > - =A0 =A0pci_mem_data =3D pci_host_data_register_mmio(&s->host_state, 1); > - =A0 =A0sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data); > + > + =A0 =A0/* pci_ioport */ > + =A0 =A0pci_ioport =3D cpu_register_io_memory(pci_apb_ioread, > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0= =A0 =A0pci_apb_iowrite, s); > + =A0 =A0/* at region 2 */ > + =A0 =A0sysbus_init_mmio(dev, 0x10000ULL, pci_ioport); > + > =A0 =A0 return 0; > =A0} > > diff --git a/hw/sun4u.c b/hw/sun4u.c > index e9a1e23..40b5f1f 100644 > --- a/hw/sun4u.c > +++ b/hw/sun4u.c > @@ -70,7 +70,7 @@ > =A0#define PROM_VADDR =A0 =A0 =A0 =A0 =A0 0x000ffd00000ULL > =A0#define APB_SPECIAL_BASE =A0 =A0 0x1fe00000000ULL > =A0#define APB_MEM_BASE =A0 =A0 =A0 =A0 0x1ff00000000ULL > -#define VGA_BASE =A0 =A0 =A0 =A0 =A0 =A0 (APB_MEM_BASE + 0x400000ULL) > +#define APB_PCI_IO_BASE =A0 =A0 =A0(APB_SPECIAL_BASE + 0x02000000ULL) > =A0#define PROM_FILENAME =A0 =A0 =A0 =A0"openbios-sparc64" > =A0#define NVRAM_SIZE =A0 =A0 =A0 =A0 =A0 0x2000 > =A0#define MAX_IDE_BUS =A0 =A0 =A0 =A0 =A02 > @@ -766,7 +766,7 @@ static void sun4uv_init(ram_addr_t RAM_size, > =A0 =A0 irq =3D qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); > =A0 =A0 pci_bus =3D pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pc= i_bus2, > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0&pci_bus3); > - =A0 =A0isa_mem_base =3D VGA_BASE; > + =A0 =A0isa_mem_base =3D APB_PCI_IO_BASE; > =A0 =A0 pci_vga_init(pci_bus, 0, 0); > > =A0 =A0 // XXX Should be pci_bus3 > @@ -859,7 +859,7 @@ enum { > =A0static const struct hwdef hwdefs[] =3D { > =A0 =A0 /* Sun4u generic PC-like machine */ > =A0 =A0 { > - =A0 =A0 =A0 =A0.default_cpu_model =3D "TI UltraSparc II", > + =A0 =A0 =A0 =A0.default_cpu_model =3D "TI UltraSparc IIi", > =A0 =A0 =A0 =A0 .machine_id =3D sun4u_id, > =A0 =A0 =A0 =A0 .prom_addr =3D 0x1fff0000000ULL, > =A0 =A0 =A0 =A0 .console_serial_base =3D 0, > > > --=20 Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/