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From: Blue Swirl <blauwirbel@gmail.com>
Date: Fri, 28 May 2010 20:30:19 +0000
Message-ID: <AANLkTimR9xaNqoNvtH2ZgRRHL-mVMh1PNP2umHgvbKRP@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH] sparc64: fix 128-bit atomic load from
	nucleus context
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To: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
Cc: qemu-devel@nongnu.org

On Fri, May 28, 2010 at 9:48 AM, Igor V. Kovalenko
<igor.v.kovalenko@gmail.com> wrote:
> From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
>
> Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
> ---
> =C2=A0sparc-dis.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=
=A0 =C2=A02 ++
> =C2=A0target-sparc/op_helper.c | =C2=A0 10 +++++-----
> =C2=A02 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/sparc-dis.c b/sparc-dis.c
> index c1b682d..dbd3b4f 100644
> --- a/sparc-dis.c
> +++ b/sparc-dis.c
> @@ -2155,6 +2155,8 @@ static const arg asi_table_v9[] =3D
> =C2=A0 /* These are UltraSPARC extensions. =C2=A0*/
> =C2=A0 { 0x14, "#ASI_PHYS_USE_EC"},
> =C2=A0 { 0x15, "#ASI_PHYS_BYPASS_EC_WITH_EBIT"},
> + =C2=A0{ 0x24, "#ASI_NUCLEUS_QUAD_LDD" },
> + =C2=A0{ 0x2c, "#ASI_NUCLEUS_QUAD_LDD_LITTLE" },
> =C2=A0 { 0x45, "#ASI_LSU_CONTROL_REG"},
> =C2=A0 { 0x47, "#ASI_DCACHE_TAG"},
> =C2=A0 { 0x49, "#ASI_INTR_RECEIVE"},

The patch does not apply because the above line is not in the tree.

This change should be also mentioned in the commit body.

> diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
> index e946ec7..63fef8c 100644
> --- a/target-sparc/op_helper.c
> +++ b/target-sparc/op_helper.c
> @@ -3088,19 +3088,19 @@ void helper_ldda_asi(target_ulong addr, int asi, =
int rd)
> =C2=A0 =C2=A0 case 0x2c: // Nucleus quad LDD 128 bit atomic LE
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 helper_check_align(addr, 0xf);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (rd =3D=3D 0) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[1] =3D ldq_kernel(a=
ddr + 8);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[1] =3D ldq_nucleus(=
addr + 8);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (asi =3D=3D 0x2c)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bswap64s(&env->gr=
egs[1]);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (rd < 8) {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[rd] =3D ldq_kernel(=
addr);
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[rd + 1] =3D ldq_ker=
nel(addr + 8);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[rd] =3D ldq_nucleus=
(addr);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->gregs[rd + 1] =3D ldq_nuc=
leus(addr + 8);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (asi =3D=3D 0x2c) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bswap64s(&env->gr=
egs[rd]);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bswap64s(&env->gr=
egs[rd + 1]);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regwptr[rd] =3D ldq_kerne=
l(addr);
> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regwptr[rd + 1] =3D ldq_k=
ernel(addr + 8);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regwptr[rd] =3D ldq_nucle=
us(addr);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regwptr[rd + 1] =3D ldq_n=
ucleus(addr + 8);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (asi =3D=3D 0x2c) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bswap64s(&env->re=
gwptr[rd]);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bswap64s(&env->re=
gwptr[rd + 1]);
>
>
>