From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=35240 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OYOIL-0000nm-Sl for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:04:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OYOIJ-0001Ke-ND for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:04:00 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:61095) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OYOIJ-0001KQ-En for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:03:59 -0400 Received: by bwz5 with SMTP id 5so2788945bwz.4 for ; Mon, 12 Jul 2010 12:03:57 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Artyom Tarasenko Date: Mon, 12 Jul 2010 21:03:37 +0200 Message-ID: Subject: Re: [Qemu-devel] [PATCH 04/15] ebus: convert to pci_bar_map Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel 2010/7/12 Blue Swirl : > Use pci_bar_map() instead of a mapping function. > > Signed-off-by: Blue Swirl > --- > =A0hw/isa.h =A0 =A0 =A0| =A0 =A01 + > =A0hw/isa_mmio.c | =A0 17 +++++++++++++++-- > =A0hw/sun4u.c =A0 =A0| =A0 29 ++++++++++------------------- > =A03 files changed, 26 insertions(+), 21 deletions(-) > > diff --git a/hw/isa.h b/hw/isa.h > index aaf0272..6fba4ac 100644 > --- a/hw/isa.h > +++ b/hw/isa.h > @@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name); > =A0extern target_phys_addr_t isa_mem_base; > > =A0void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, i= nt be); > +int pci_isa_mmio_init(int be); > > =A0/* dma.c */ > =A0int DMA_get_channel_mode (int nchan); > diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c > index 66bdd2c..3b2de4a 100644 > --- a/hw/isa_mmio.c > +++ b/hw/isa_mmio.c > @@ -125,7 +125,7 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = =3D { > > =A0static int isa_mmio_iomemtype =3D 0; > > -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int= be) > +static int isa_mmio_memtype(int be) > =A0{ > =A0 =A0 if (!isa_mmio_iomemtype) { > =A0 =A0 =A0 =A0 if (be) { > @@ -138,5 +138,18 @@ void isa_mmio_init(target_phys_addr_t base, > target_phys_addr_t size, int be) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 = =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 NULL); > =A0 =A0 =A0 =A0 } > =A0 =A0 } > - =A0 =A0cpu_register_physical_memory(base, size, isa_mmio_iomemtype); > + =A0 =A0return isa_mmio_iomemtype; > +} > + > +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, int= be) > +{ > + =A0 =A0int isa; > + > + =A0 =A0isa =3D isa_mmio_memtype(be); > + =A0 =A0cpu_register_physical_memory(base, size, isa); > +} > + > +int pci_isa_mmio_init(int be) > +{ > + =A0 =A0return isa_mmio_memtype(be); > =A0} > diff --git a/hw/sun4u.c b/hw/sun4u.c > index 31c0c4c..8565243 100644 > --- a/hw/sun4u.c > +++ b/hw/sun4u.c > @@ -517,21 +517,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t li= mit) > =A0 =A0 } > =A0} > > -static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0pcibus_t add= r, pcibus_t size, int type) > -{ > - =A0 =A0EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n", > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 region_num, addr); > - =A0 =A0switch (region_num) { > - =A0 =A0case 0: > - =A0 =A0 =A0 =A0isa_mmio_init(addr, 0x1000000, 1); > - =A0 =A0 =A0 =A0break; > - =A0 =A0case 1: > - =A0 =A0 =A0 =A0isa_mmio_init(addr, 0x800000, 1); > - =A0 =A0 =A0 =A0break; > - =A0 =A0} > -} > - > =A0static void dummy_isa_irq_handler(void *opaque, int n, int level) > =A0{ > =A0} > @@ -550,6 +535,8 @@ pci_ebus_init(PCIBus *bus, int devfn) > =A0static int > =A0pci_ebus_init1(PCIDevice *s) > =A0{ > + =A0 =A0int io_index; > + > =A0 =A0 isa_bus_new(&s->qdev); > > =A0 =A0 pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); > @@ -563,10 +550,14 @@ pci_ebus_init1(PCIDevice *s) > =A0 =A0 pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); > =A0 =A0 s->config[0x0D] =3D 0x0a; // latency_timer > > - =A0 =A0pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY, > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ebus_mmio_mapfunc); > - =A0 =A0pci_register_bar(s, 1, 0x800000, =A0PCI_BASE_ADDRESS_SPACE_MEMOR= Y, > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ebus_mmio_mapfunc); > + =A0 =A0pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,= NULL); > + =A0 =A0io_index =3D pci_isa_mmio_init(1); > + =A0 =A0pci_bar_map(s, 0, 0, 0, 0x1000000, io_index); > + > + =A0 =A0pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_MEMORY, = NULL); > + =A0 =A0io_index =3D pci_isa_mmio_init(1); > + =A0 =A0pci_bar_map(s, 1, 0, 0, 0x800000, io_index); Are these well-known constants? > + > =A0 =A0 return 0; > =A0} > > -- > 1.7.1 > > --=20 Regards, Artyom Tarasenko solaris/sparc under qemu blog: http://tyom.blogspot.com/