From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=51797 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q0rJZ-0006q2-45 for qemu-devel@nongnu.org; Sat, 19 Mar 2011 04:15:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q0rJX-0002Fy-K1 for qemu-devel@nongnu.org; Sat, 19 Mar 2011 04:15:12 -0400 Received: from mail-vx0-f173.google.com ([209.85.220.173]:53075) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q0rJX-0002Fp-G1 for qemu-devel@nongnu.org; Sat, 19 Mar 2011 04:15:11 -0400 Received: by vxb41 with SMTP id 41so4508827vxb.4 for ; Sat, 19 Mar 2011 01:15:11 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <9f6d960c3755e0ca0680da81adb774e256773121.1300266238.git.yamahata@valinux.co.jp> References: <9f6d960c3755e0ca0680da81adb774e256773121.1300266238.git.yamahata@valinux.co.jp> From: Blue Swirl Date: Sat, 19 Mar 2011 10:14:51 +0200 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] Re: [PATCH 08/26] apb_pci: simplify apb_pci.c by using pci_p2pbr List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" On Wed, Mar 16, 2011 at 11:29 AM, Isaku Yamahata w= rote: > apply pci_p2pbr for apb_pci.c. > > Cc: Michael S. Tsirkin > Cc: Blue Swirl > Signed-off-by: Isaku Yamahata > --- > =C2=A0hw/apb_pci.c | =C2=A0 63 ++++++++++++++++++++++++------------------= --------------- > =C2=A01 files changed, 27 insertions(+), 36 deletions(-) > > diff --git a/hw/apb_pci.c b/hw/apb_pci.c > index c56ea9a..c9f2a6b 100644 > --- a/hw/apb_pci.c > +++ b/hw/apb_pci.c > @@ -31,6 +31,7 @@ > =C2=A0#include "pci_host.h" > =C2=A0#include "pci_bridge.h" > =C2=A0#include "pci_internals.h" > +#include "pci_p2pbr.h" > =C2=A0#include "rwhandler.h" > =C2=A0#include "apb_pci.h" > =C2=A0#include "sysemu.h" > @@ -297,16 +298,6 @@ static void pci_apb_set_irq(void *opaque, int irq_nu= m, int level) > > =C2=A0static int apb_pci_bridge_initfn(PCIDevice *dev) > =C2=A0{ > - =C2=A0 =C2=A0int rc; > - > - =C2=A0 =C2=A0rc =3D pci_bridge_initfn(dev); > - =C2=A0 =C2=A0if (rc < 0) { > - =C2=A0 =C2=A0 =C2=A0 =C2=A0return rc; > - =C2=A0 =C2=A0} > - > - =C2=A0 =C2=A0pci_config_set_vendor_id(dev->config, PCI_VENDOR_ID_SUN); > - =C2=A0 =C2=A0pci_config_set_device_id(dev->config, PCI_DEVICE_ID_SUN_SI= MBA); > - > =C2=A0 =C2=A0 /* > =C2=A0 =C2=A0 =C2=A0* command register: > =C2=A0 =C2=A0 =C2=A0* According to PCI bridge spec, after reset > @@ -321,10 +312,31 @@ static int apb_pci_bridge_initfn(PCIDevice *dev) > =C2=A0 =C2=A0 pci_set_word(dev->config + PCI_STATUS, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_STATUS_= FAST_BACK | PCI_STATUS_66MHZ | > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_STATUS_= DEVSEL_MEDIUM); > - =C2=A0 =C2=A0pci_set_byte(dev->config + PCI_REVISION_ID, 0x11); > =C2=A0 =C2=A0 return 0; > =C2=A0} > > +static PCIBridge *apb_pci_bridge_init(PCIBus *bus, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint8_t devfn= , const char *bus_name) > +{ > + =C2=A0 =C2=A0const PCIP2PBridgeInit init =3D { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.bus =3D bus, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.devfn =3D devfn, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.multifunction =3D true, > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.bus_name =3D bus_name, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.map_irq =3D pci_apb_map_irq, > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.initfn =3D apb_pci_bridge_initfn, > + =C2=A0 =C2=A0}; > + =C2=A0 =C2=A0const PCIP2PBridgeProp prop =3D { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.vendor_id =3D PCI_VENDOR_ID_SUN, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.device_id =3D PCI_DEVICE_ID_SUN_SIMBA, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0.revision_id =3D 0x11, > + =C2=A0 =C2=A0}; 'static' again.