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Date: Fri, 11 Mar 2011 11:09:55 -0800
Message-ID: <AANLkTimowTpydbdeTL++X7_MRfq17Z-Psa7EJwvvjX=m@mail.gmail.com>
Subject: Re: [Qemu-devel] Re: RFC: emulation of system flash
From: Jordan Justen <jljusten@gmail.com>
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To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Cc: Gleb Natapov <gleb@redhat.com>, Stefan Hajnoczi <stefanha@gmail.com>, qemu-devel <qemu-devel@nongnu.org>, Michal Suchanek <hramrach@centrum.cz>, Kevin O'Connor <kevin@koconnor.net>, Jan Kiszka <jan.kiszka@web.de>, Avi Kivity <avi@redhat.com>

On Thu, Mar 10, 2011 at 16:27, Carl-Daniel Hailfinger
<c-d.hailfinger.devel.2006@gmx.net> wrote:
> Auf 11.03.2011 01:19, Jan Kiszka schrieb:
>> At least it's an in-band interface, which is the better choice as we
>> currently only have a PIIX3 southbridge for x86, predating even FWHs.
>>
>
> Right, that pretty much kills the option of using SPI unless someone
> wants to emulate a flash translation controller (e.g. the ITE IT8716F
> Super I/O). Can be done, would work, but the IT8716F has some quirks
> (max 1 MB SPI flash chips) which make it a less desirable option for
> emulation.

I don't much like this, but we might consider adding the SPI host
controller MMIO just below the flash data.  For the firmware, we
usually will know the size of firmware device that we've built for.
It seems SPI flash is pretty common today, and it sounds like
Carl-Daniel may have some SPI emulation code.

Am I understanding correctly that CFI is programmed via MMIO in the
flash memory space?  How difficult would it be to emulate CFI?  Does
CFI have the same power-of-2 size flexibility as SPI?

-Jordan