From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=36986 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OYOWh-0007LZ-Nb for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:18:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OYOWf-0003Ra-Uw for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:18:51 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:41424) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OYOWf-0003RB-Jj for qemu-devel@nongnu.org; Mon, 12 Jul 2010 15:18:49 -0400 Received: by pwi2 with SMTP id 2so1985765pwi.4 for ; Mon, 12 Jul 2010 12:18:48 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: From: Blue Swirl Date: Mon, 12 Jul 2010 19:18:28 +0000 Message-ID: Subject: Re: [Qemu-devel] [PATCH 04/15] ebus: convert to pci_bar_map Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: qemu-devel On Mon, Jul 12, 2010 at 7:03 PM, Artyom Tarasenko wrote: > 2010/7/12 Blue Swirl : >> Use pci_bar_map() instead of a mapping function. >> >> Signed-off-by: Blue Swirl >> --- >> =C2=A0hw/isa.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A01 + >> =C2=A0hw/isa_mmio.c | =C2=A0 17 +++++++++++++++-- >> =C2=A0hw/sun4u.c =C2=A0 =C2=A0| =C2=A0 29 ++++++++++------------------- >> =C2=A03 files changed, 26 insertions(+), 21 deletions(-) >> >> diff --git a/hw/isa.h b/hw/isa.h >> index aaf0272..6fba4ac 100644 >> --- a/hw/isa.h >> +++ b/hw/isa.h >> @@ -33,6 +33,7 @@ ISADevice *isa_create_simple(const char *name); >> =C2=A0extern target_phys_addr_t isa_mem_base; >> >> =C2=A0void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t siz= e, int be); >> +int pci_isa_mmio_init(int be); >> >> =C2=A0/* dma.c */ >> =C2=A0int DMA_get_channel_mode (int nchan); >> diff --git a/hw/isa_mmio.c b/hw/isa_mmio.c >> index 66bdd2c..3b2de4a 100644 >> --- a/hw/isa_mmio.c >> +++ b/hw/isa_mmio.c >> @@ -125,7 +125,7 @@ static CPUReadMemoryFunc * const isa_mmio_read_le[] = =3D { >> >> =C2=A0static int isa_mmio_iomemtype =3D 0; >> >> -void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, in= t be) >> +static int isa_mmio_memtype(int be) >> =C2=A0{ >> =C2=A0 =C2=A0 if (!isa_mmio_iomemtype) { >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (be) { >> @@ -138,5 +138,18 @@ void isa_mmio_init(target_phys_addr_t base, >> target_phys_addr_t size, int be) >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 NULL); >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 } >> =C2=A0 =C2=A0 } >> - =C2=A0 =C2=A0cpu_register_physical_memory(base, size, isa_mmio_iomemty= pe); >> + =C2=A0 =C2=A0return isa_mmio_iomemtype; >> +} >> + >> +void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size, in= t be) >> +{ >> + =C2=A0 =C2=A0int isa; >> + >> + =C2=A0 =C2=A0isa =3D isa_mmio_memtype(be); >> + =C2=A0 =C2=A0cpu_register_physical_memory(base, size, isa); >> +} >> + >> +int pci_isa_mmio_init(int be) >> +{ >> + =C2=A0 =C2=A0return isa_mmio_memtype(be); >> =C2=A0} >> diff --git a/hw/sun4u.c b/hw/sun4u.c >> index 31c0c4c..8565243 100644 >> --- a/hw/sun4u.c >> +++ b/hw/sun4u.c >> @@ -517,21 +517,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t l= imit) >> =C2=A0 =C2=A0 } >> =C2=A0} >> >> -static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pcibus_t addr, pcibus_t size, int type) >> -{ >> - =C2=A0 =C2=A0EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBU= S "\n", >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 region_num, ad= dr); >> - =C2=A0 =C2=A0switch (region_num) { >> - =C2=A0 =C2=A0case 0: >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0isa_mmio_init(addr, 0x1000000, 1); >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0break; >> - =C2=A0 =C2=A0case 1: >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0isa_mmio_init(addr, 0x800000, 1); >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0break; >> - =C2=A0 =C2=A0} >> -} >> - >> =C2=A0static void dummy_isa_irq_handler(void *opaque, int n, int level) >> =C2=A0{ >> =C2=A0} >> @@ -550,6 +535,8 @@ pci_ebus_init(PCIBus *bus, int devfn) >> =C2=A0static int >> =C2=A0pci_ebus_init1(PCIDevice *s) >> =C2=A0{ >> + =C2=A0 =C2=A0int io_index; >> + >> =C2=A0 =C2=A0 isa_bus_new(&s->qdev); >> >> =C2=A0 =C2=A0 pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); >> @@ -563,10 +550,14 @@ pci_ebus_init1(PCIDevice *s) >> =C2=A0 =C2=A0 pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); >> =C2=A0 =C2=A0 s->config[0x0D] =3D 0x0a; // latency_timer >> >> - =C2=A0 =C2=A0pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_= MEMORY, >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 ebus_mmio_mapfunc); >> - =C2=A0 =C2=A0pci_register_bar(s, 1, 0x800000, =C2=A0PCI_BASE_ADDRESS_S= PACE_MEMORY, >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 ebus_mmio_mapfunc); >> + =C2=A0 =C2=A0pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_= MEMORY, NULL); >> + =C2=A0 =C2=A0io_index =3D pci_isa_mmio_init(1); >> + =C2=A0 =C2=A0pci_bar_map(s, 0, 0, 0, 0x1000000, io_index); >> + >> + =C2=A0 =C2=A0pci_register_bar(s, 1, 0x800000, PCI_BASE_ADDRESS_SPACE_M= EMORY, NULL); >> + =C2=A0 =C2=A0io_index =3D pci_isa_mmio_init(1); >> + =C2=A0 =C2=A0pci_bar_map(s, 1, 0, 0, 0x800000, io_index); > > Are these well-known constants? IIRC I picked them from device tree range sizes: ranges: 00000010.00000000.82010810.00000000.f0000000.01000000.00000014.00000000.820= 10814.00000000.f1000000.00800000 It's a bit annoying to repeat the constants, but this is a simple case where the subregion size is equal to the whole BAR size.