From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwnby-0002kH-FS for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:15:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Wwnbt-0005Zp-9M for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:15:18 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:55321) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Wwnbs-0005Za-WD for qemu-devel@nongnu.org; Tue, 17 Jun 2014 03:15:13 -0400 From: "Aggeler Fabian" Date: Tue, 17 Jun 2014 07:15:10 +0000 Message-ID: References: <1402444514-19658-1-git-send-email-aggelerf@ethz.ch> <1402444514-19658-31-git-send-email-aggelerf@ethz.ch> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-ID: <8C4A9AA3ABF24940A63A05EEC3C66A86@intern.ethz.ch> Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v3 30/32] target-arm: make PAR banked List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Greg Bellows Cc: Peter Maydell , Peter Crosthwaite , QEMU Developers , Sergey Fedorov , "Edgar E. Iglesias" , Christoffer Dall On 14 Jun 2014, at 00:49, Greg Bellows > wrote: On 10 June 2014 18:55, Fabian Aggeler > wrote: When EL3 is running in Aarch32 (or ARMv7 with Security Extensions) PAR has a secure and a non-secure instance. Signed-off-by: Fabian Aggeler > --- target-arm/cpu.h | 10 +++++++++- target-arm/helper.c | 25 ++++++++++++++----------- 2 files changed, 23 insertions(+), 12 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 7f5124c..048ede9 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -299,7 +299,15 @@ typedef struct CPUARMState { }; }; uint64_t far_el3; - uint64_t par_el1; /* Translation result. */ + struct { /* Translation result. */ + union { + uint64_t par_ns; + uint64_t par_s; + }; + union { + uint64_t par_el1; + }; + }; This is broken. This should be a union of structs rather than a struct of = unions. Should instead be. union { struct { uint64_t par_ns; uint64_t par_s; }; struct { uint64_t par_el1; }; }; Right, that should have been the other way round, like you said. uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c9_pmcr; /* performance monitor control register */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 47bf7a7..c3195bd 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1281,7 +1281,7 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) * fault. */ } - env->cp15.par_el1 =3D par64; + A32_BANKED_CURRENT_REG_SET(env, par, par64); } else { /* ret is a DFSR/IFSR value for the short descriptor * translation table format (with WnR always clear). @@ -1291,14 +1291,16 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) /* We do not set any attribute bits in the PAR */ if (page_size =3D=3D (1 << 24) && arm_feature(env, ARM_FEATURE_V7)) { - env->cp15.par_el1 =3D (phys_addr & 0xff000000) | 1 << 1; + A32_BANKED_CURRENT_REG_SET(env, par, + (phys_addr & 0xff000000) | 1 << 1); } else { - env->cp15.par_el1 =3D phys_addr & 0xfffff000; + A32_BANKED_CURRENT_REG_SET(env, par, phys_addr & 0xfffff00= 0); } } else { - env->cp15.par_el1 =3D ((ret & (1 << 10)) >> 5) | - ((ret & (1 << 12)) >> 6) | - ((ret & 0xf) << 1) | 1; + A32_BANKED_CURRENT_REG_SET(env, par, + ((ret & (1 << 10)) >> 5) | + ((ret & (1 << 12)) >> 6) | + ((ret & 0xf) << 1) | 1); } } } @@ -1306,9 +1308,9 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) static const ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, - .access =3D PL1_RW, .resetvalue =3D 0, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.par_el1), - .writefn =3D par_write }, + .access =3D PL1_RW, .resetvalue =3D 0, .writefn =3D par_write, + .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), + offsetoflow32(CPUARMState, cp15.par_ns) } }, #ifndef CONFIG_USER_ONLY { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, .access =3D PL1_W, .accessfn =3D ats_access, @@ -1755,8 +1757,9 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, { .name =3D "PAR", .cp =3D 15, .crm =3D 7, .opc1 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_64BIT, - .fieldoffset =3D offsetof(CPUARMState, cp15.par_el1), .resetvalue = =3D 0 }, + .access =3D PL1_RW, .type =3D ARM_CP_64BIT, .resetvalue =3D 0, + .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.par_s), + offsetof(CPUARMState, cp15.par_ns)} }, { .name =3D "TTBR0", .cp =3D 15, .crm =3D 2, .opc1 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_64BIT | ARM_CP_NO_MIGRATE, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), -- 1.8.3.2