* [Qemu-devel] [PATCH] tcg-hppa: Support deposit opcode.
@ 2011-06-20 22:10 Richard Henderson
2011-07-01 21:10 ` Blue Swirl
0 siblings, 1 reply; 2+ messages in thread
From: Richard Henderson @ 2011-06-20 22:10 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/hppa/tcg-target.c | 24 ++++++++++++++++++++----
tcg/hppa/tcg-target.h | 1 +
2 files changed, 21 insertions(+), 4 deletions(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 95f3316..16423aa 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -467,6 +467,14 @@ static inline void tcg_out_dep(TCGContext *s, int ret, int arg,
| INSN_SHDEP_CP(31 - ofs) | INSN_DEP_LEN(len));
}
+static inline void tcg_out_depi(TCGContext *s, int ret, int arg,
+ unsigned ofs, unsigned len)
+{
+ assert(ofs < 32 && len <= 32 - ofs);
+ tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(arg)
+ | INSN_SHDEP_CP(31 - ofs) | INSN_DEP_LEN(len));
+}
+
static inline void tcg_out_shd(TCGContext *s, int ret, int hi, int lo,
unsigned count)
{
@@ -499,8 +507,7 @@ static void tcg_out_ori(TCGContext *s, int ret, int arg, tcg_target_ulong m)
assert(bs1 == 32 || (1ul << bs1) > m);
tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
- tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(-1)
- | INSN_SHDEP_CP(31 - bs0) | INSN_DEP_LEN(bs1 - bs0));
+ tcg_out_depi(s, ret, -1, bs0, bs1 - bs0);
}
static void tcg_out_andi(TCGContext *s, int ret, int arg, tcg_target_ulong m)
@@ -529,8 +536,7 @@ static void tcg_out_andi(TCGContext *s, int ret, int arg, tcg_target_ulong m)
tcg_out_extr(s, ret, arg, 0, ls0, 0);
} else {
tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
- tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(0)
- | INSN_SHDEP_CP(31 - ls0) | INSN_DEP_LEN(ls1 - ls0));
+ tcg_out_depi(s, ret, 0, ls0, ls1 - ls0);
}
}
@@ -1459,6 +1465,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[4], args[5], const_args[2], const_args[4]);
break;
+ case INDEX_op_deposit_i32:
+ if (const_args[2]) {
+ tcg_out_depi(s, args[0], args[2], args[3], args[4]);
+ } else {
+ tcg_out_dep(s, args[0], args[2], args[3], args[4]);
+ }
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0);
break;
@@ -1552,6 +1566,8 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } },
{ INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } },
+ { INDEX_op_deposit_i32, { "r", "0", "rJ" } },
+
#if TARGET_LONG_BITS == 32
{ INDEX_op_qemu_ld8u, { "r", "L" } },
{ INDEX_op_qemu_ld8s, { "r", "L" } },
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index a5cc440..f7919ce 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -94,6 +94,7 @@ enum {
#define TCG_TARGET_HAS_not_i32
#define TCG_TARGET_HAS_andc_i32
// #define TCG_TARGET_HAS_orc_i32
+#define TCG_TARGET_HAS_deposit_i32
/* optional instructions automatically implemented */
#undef TCG_TARGET_HAS_neg_i32 /* sub rd, 0, rs */
--
1.5.6.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg-hppa: Support deposit opcode.
2011-06-20 22:10 [Qemu-devel] [PATCH] tcg-hppa: Support deposit opcode Richard Henderson
@ 2011-07-01 21:10 ` Blue Swirl
0 siblings, 0 replies; 2+ messages in thread
From: Blue Swirl @ 2011-07-01 21:10 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
Thanks, applied.
On Tue, Jun 21, 2011 at 1:10 AM, Richard Henderson <rth@twiddle.net> wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/hppa/tcg-target.c | 24 ++++++++++++++++++++----
> tcg/hppa/tcg-target.h | 1 +
> 2 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
> index 95f3316..16423aa 100644
> --- a/tcg/hppa/tcg-target.c
> +++ b/tcg/hppa/tcg-target.c
> @@ -467,6 +467,14 @@ static inline void tcg_out_dep(TCGContext *s, int ret, int arg,
> | INSN_SHDEP_CP(31 - ofs) | INSN_DEP_LEN(len));
> }
>
> +static inline void tcg_out_depi(TCGContext *s, int ret, int arg,
> + unsigned ofs, unsigned len)
> +{
> + assert(ofs < 32 && len <= 32 - ofs);
> + tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(arg)
> + | INSN_SHDEP_CP(31 - ofs) | INSN_DEP_LEN(len));
> +}
> +
> static inline void tcg_out_shd(TCGContext *s, int ret, int hi, int lo,
> unsigned count)
> {
> @@ -499,8 +507,7 @@ static void tcg_out_ori(TCGContext *s, int ret, int arg, tcg_target_ulong m)
> assert(bs1 == 32 || (1ul << bs1) > m);
>
> tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
> - tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(-1)
> - | INSN_SHDEP_CP(31 - bs0) | INSN_DEP_LEN(bs1 - bs0));
> + tcg_out_depi(s, ret, -1, bs0, bs1 - bs0);
> }
>
> static void tcg_out_andi(TCGContext *s, int ret, int arg, tcg_target_ulong m)
> @@ -529,8 +536,7 @@ static void tcg_out_andi(TCGContext *s, int ret, int arg, tcg_target_ulong m)
> tcg_out_extr(s, ret, arg, 0, ls0, 0);
> } else {
> tcg_out_mov(s, TCG_TYPE_I32, ret, arg);
> - tcg_out32(s, INSN_DEPI | INSN_R2(ret) | INSN_IM5(0)
> - | INSN_SHDEP_CP(31 - ls0) | INSN_DEP_LEN(ls1 - ls0));
> + tcg_out_depi(s, ret, 0, ls0, ls1 - ls0);
> }
> }
>
> @@ -1459,6 +1465,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> args[4], args[5], const_args[2], const_args[4]);
> break;
>
> + case INDEX_op_deposit_i32:
> + if (const_args[2]) {
> + tcg_out_depi(s, args[0], args[2], args[3], args[4]);
> + } else {
> + tcg_out_dep(s, args[0], args[2], args[3], args[4]);
> + }
> + break;
> +
> case INDEX_op_qemu_ld8u:
> tcg_out_qemu_ld(s, args, 0);
> break;
> @@ -1552,6 +1566,8 @@ static const TCGTargetOpDef hppa_op_defs[] = {
> { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } },
> { INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } },
>
> + { INDEX_op_deposit_i32, { "r", "0", "rJ" } },
> +
> #if TARGET_LONG_BITS == 32
> { INDEX_op_qemu_ld8u, { "r", "L" } },
> { INDEX_op_qemu_ld8s, { "r", "L" } },
> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
> index a5cc440..f7919ce 100644
> --- a/tcg/hppa/tcg-target.h
> +++ b/tcg/hppa/tcg-target.h
> @@ -94,6 +94,7 @@ enum {
> #define TCG_TARGET_HAS_not_i32
> #define TCG_TARGET_HAS_andc_i32
> // #define TCG_TARGET_HAS_orc_i32
> +#define TCG_TARGET_HAS_deposit_i32
>
> /* optional instructions automatically implemented */
> #undef TCG_TARGET_HAS_neg_i32 /* sub rd, 0, rs */
> --
> 1.5.6.5
^ permalink raw reply [flat|nested] 2+ messages in thread
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2011-06-20 22:10 [Qemu-devel] [PATCH] tcg-hppa: Support deposit opcode Richard Henderson
2011-07-01 21:10 ` Blue Swirl
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