From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49706) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHi3d-00009S-FE for qemu-devel@nongnu.org; Wed, 04 May 2011 15:48:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHi3c-0002dT-4V for qemu-devel@nongnu.org; Wed, 04 May 2011 15:48:25 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:57011) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHi3b-0002dO-Vl for qemu-devel@nongnu.org; Wed, 04 May 2011 15:48:24 -0400 Received: by qyk36 with SMTP id 36so3369625qyk.4 for ; Wed, 04 May 2011 12:48:23 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1304470768-16924-24-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> <1304470768-16924-24-git-send-email-jcmvbkbc@gmail.com> From: Blue Swirl Date: Wed, 4 May 2011 22:48:03 +0300 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC 24/28] target-xtensa: implement SIMCALL List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-devel@nongnu.org On Wed, May 4, 2011 at 3:59 AM, Max Filippov wrote: > Tensilica iss provides support for applications running in freestanding > environment through SIMCALL command. It is used by Tensilica libc to > access argc/argv, for file I/O, etc. > > Signed-off-by: Max Filippov > --- > =C2=A0target-xtensa/helpers.h =C2=A0 | =C2=A0 =C2=A01 + > =C2=A0target-xtensa/op_helper.c | =C2=A0 =C2=A07 ++ > =C2=A0target-xtensa/simcall.c =C2=A0 | =C2=A0157 ++++++++++++++++++++++++= +++++++++++++++++++++ > =C2=A0target-xtensa/translate.c | =C2=A0 =C2=A02 +- > =C2=A04 files changed, 166 insertions(+), 1 deletions(-) > =C2=A0create mode 100644 target-xtensa/simcall.c > > diff --git a/target-xtensa/helpers.h b/target-xtensa/helpers.h > index 7e212a3..55eb0d8 100644 > --- a/target-xtensa/helpers.h > +++ b/target-xtensa/helpers.h > @@ -11,6 +11,7 @@ DEF_HELPER_2(window_check, void, i32, i32) > =C2=A0DEF_HELPER_0(restore_owb, void) > =C2=A0DEF_HELPER_1(movsp, void, i32) > =C2=A0DEF_HELPER_1(wsr_lend, void, i32) > +DEF_HELPER_0(simcall, void) > =C2=A0DEF_HELPER_0(dump_state, void) > > =C2=A0#include "def-helper.h" > diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c > index f0690ee..68b1526 100644 > --- a/target-xtensa/op_helper.c > +++ b/target-xtensa/op_helper.c > @@ -264,6 +264,13 @@ void HELPER(wsr_lend)(uint32_t v) > =C2=A0 =C2=A0 } > =C2=A0} > > +#include "simcall.c" > + > +void HELPER(simcall)(void) > +{ > + =C2=A0 =C2=A0simcall(env->regs); Maybe this should be enabled only with -semihosting parameter, like ARM and m68k. Consider for example what could happen if this would be issued from userland when used with an OS. > +} > + > =C2=A0void HELPER(dump_state)(void) > =C2=A0{ > =C2=A0 =C2=A0 cpu_dump_state(env, stderr, fprintf, 0); > diff --git a/target-xtensa/simcall.c b/target-xtensa/simcall.c > new file mode 100644 > index 0000000..3446275 > --- /dev/null > +++ b/target-xtensa/simcall.c > @@ -0,0 +1,157 @@ > +/* > + * Copyright (c) 2011, Max Filippov, Motorola Solutions, Inc. > + * All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions ar= e met: > + * =C2=A0 =C2=A0 * Redistributions of source code must retain the above = copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer. > + * =C2=A0 =C2=A0 * Redistributions in binary form must reproduce the abo= ve copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer in the > + * =C2=A0 =C2=A0 =C2=A0 documentation and/or other materials provided wi= th the distribution. > + * =C2=A0 =C2=A0 * Neither the name of the Motorola Solutions nor the > + * =C2=A0 =C2=A0 =C2=A0 names of its contributors may be used to endorse= or promote products > + * =C2=A0 =C2=A0 =C2=A0 derived from this software without specific prio= r written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "= AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,= THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PU= RPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SE= RVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUS= ED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR= TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE= OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +enum { > + =C2=A0 =C2=A0SYS_exit =3D 1, > + =C2=A0 =C2=A0SYS_read =3D 3, > + =C2=A0 =C2=A0SYS_write =3D 4, > + =C2=A0 =C2=A0SYS_open =3D 5, > + =C2=A0 =C2=A0SYS_close =3D 6, > + > + =C2=A0 =C2=A0SYS_argc =3D 1000, > + =C2=A0 =C2=A0SYS_argv_sz =3D 1001, > + =C2=A0 =C2=A0SYS_argv =3D 1002, > + =C2=A0 =C2=A0SYS_memset =3D 1004, I think these names may easily conflict with system defines, please use for example TARGET_SYS_exit etc. > +}; > + > +static void simcall(uint32_t regs[16]) > +{ > + =C2=A0 =C2=A0switch (regs[2]) { > + =C2=A0 =C2=A0case SYS_exit: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0printf("exit(%d)\n", regs[3]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0exit(regs[3]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_read: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0{ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_phys_addr_t len =3D reg= s[5]; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *buf =3D cpu_physical_mem= ory_map(regs[4], &len, 1); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (buf) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D read= (regs[3], buf, len); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D errn= o; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_physical_mem= ory_unmap(buf, len, 1, len); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D -1; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_write: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0{ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_phys_addr_t len =3D reg= s[5]; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *buf =3D cpu_physical_mem= ory_map(regs[4], &len, 0); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (buf) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D writ= e(regs[3], buf, len); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D errn= o; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_physical_mem= ory_unmap(buf, len, 0, len); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D -1; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_open: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0{ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_phys_addr_t len =3D 102= 4; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *buf =3D cpu_physical_mem= ory_map(regs[3], &len, 0); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (buf && strnlen((char *)buf= , len) < len) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D open= ((char *)buf, regs[4], regs[5]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D errn= o; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D -1; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_close: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0if (regs[3] < 3) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D close(regs[3]); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D errno; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_argc: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D 1; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_argv_sz: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[2] =3D 128; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0regs[3] =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_argv: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0{ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct Argv { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0uint32_t argptr[= 2]; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0char text[120]; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} argv =3D { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0{0, 0}, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"test" > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}; > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0argv.argptr[0] =3D regs[3] + o= ffsetof(struct Argv, text); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_memory_rw_debug( > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0en= v, regs[3], (uint8_t *)&argv, sizeof(argv), 1); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0} > + =C2=A0 =C2=A0 =C2=A0 =C2=A0break; > + > + =C2=A0 =C2=A0case SYS_memset: > + =C2=A0 =C2=A0 =C2=A0 =C2=A0{ > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0target_phys_addr_t len =3D reg= s[5]; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void *buf =3D cpu_physical_mem= ory_map(regs[3], &len, 1); > + > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0assert(len =3D=3D regs[5]); The guest can probably trigger this assertion, which would not be safe.