Re: [Qemu-devel] Bug #757654: UHCI fails to signal stall response patch

[Jan Vesely <jano.vesely@gmail.com>]

On Sat, Apr 16, 2011 at 8:33 AM, Brad Hards <bradh@frogmouth.net> wrote:
> On Sat, 16 Apr 2011 06:57:00 am Jan Vesely wrote:
>> +        s->status |= UHCI_STS_USBERR;
> This is per UHCI 1.1D Section 4.1.5. Looks good.
>
>> +        *int_mask |= 0x02;
>> +        if (td->ctrl & TD_CTRL_IOC)
>> +            *int_mask |= 0x01;
>> +        uhci_update_irq(s);
> I see "A hardware interrupt is signalled to the system", but can you provide a
> little explanation of why this particular interrupt mask?

I used th code I found around in that same file (hw/usb-uhci.c),
lines 705-724 contain both masks. "if (td->ctrl & TD_CTRL_IOC)
*int_mask |= 0x01;", is in more places so I just copied that lines.
*int_mask |= 0x2, is used when SPD condition is detected.
that is strange, SPD should use the same interrupt as IOC, but return
value indicates that it is treated as error condition (unsuccessful
td) so I figured *int_mask |= 0x2 signals error interrupt (it does not
match bits in interrupt enable register- that was my first guess)
uhci_update_irq(s); to me it looks like a duplicate functionality to
int_mask parameter, I did not investigate further and included it just
to be sure (it's used on line 775, when error countdown reaches zero).

>
>> +        s->status |= UHCI_STS_USBERR;
> This is per UHCI 1.1d Section 4.1.4. Looks good.
>
>> +        *int_mask |= 0x02;
>> +        if (td->ctrl & TD_CTRL_IOC)
>> +           *int_mask |= 0x01;
>> +        uhci_update_irq(s);
> I see "A hardware interrupt is signalled to the system", but can you provide a
> little explanation of why this particular interrupt mask?
>
>