From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:35457) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWw5f-00083w-9r for qemu-devel@nongnu.org; Wed, 15 Jun 2011 15:49:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QWw5d-0007VZ-Km for qemu-devel@nongnu.org; Wed, 15 Jun 2011 15:49:27 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:60582) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QWw5d-0007VS-9z for qemu-devel@nongnu.org; Wed, 15 Jun 2011 15:49:25 -0400 Received: by qwj8 with SMTP id 8so442415qwj.4 for ; Wed, 15 Jun 2011 12:49:24 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <1306860503-13248-1-git-send-email-peter.maydell@linaro.org> From: Blue Swirl Date: Wed, 15 Jun 2011 22:49:02 +0300 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] smc91c111: qdevify reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org, patches@linaro.org On Tue, Jun 14, 2011 at 8:11 PM, Peter Maydell w= rote: > Ping? Thanks, applied. > On 31 May 2011 17:48, Peter Maydell wrote: >> From: Juha Riihim=C3=A4ki >> >> Register the smc91c111 reset function as a qdev reset function. >> >> Signed-off-by: Juha Riihim=C3=A4ki >> Reviewed-by: Peter Maydell >> --- >> =C2=A0hw/smc91c111.c | =C2=A0 =C2=A09 ++++----- >> =C2=A01 files changed, 4 insertions(+), 5 deletions(-) >> >> diff --git a/hw/smc91c111.c b/hw/smc91c111.c >> index dafea5c..701baaf 100644 >> --- a/hw/smc91c111.c >> +++ b/hw/smc91c111.c >> @@ -252,8 +252,9 @@ static void smc91c111_queue_tx(smc91c111_state *s, i= nt packet) >> =C2=A0 =C2=A0 smc91c111_do_tx(s); >> =C2=A0} >> >> -static void smc91c111_reset(smc91c111_state *s) >> +static void smc91c111_reset(DeviceState *dev) >> =C2=A0{ >> + =C2=A0 =C2=A0smc91c111_state *s =3D FROM_SYSBUS(smc91c111_state, sysbu= s_from_qdev(dev)); >> =C2=A0 =C2=A0 s->bank =3D 0; >> =C2=A0 =C2=A0 s->tx_fifo_len =3D 0; >> =C2=A0 =C2=A0 s->tx_fifo_done_len =3D 0; >> @@ -302,7 +303,7 @@ static void smc91c111_writeb(void *opaque, target_ph= ys_addr_t offset, >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 case 5: >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 SET_HIGH(rcr, value); >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (s->rcr & RCR_SOFT_RST) >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0smc91c111_reset= (s); >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0smc91c111_reset= (&s->busdev.qdev); >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return; >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 case 10: case 11: /* RPCR */ >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Ignored */ >> @@ -753,9 +754,6 @@ static int smc91c111_init1(SysBusDevice *dev) >> =C2=A0 =C2=A0 sysbus_init_mmio(dev, 16, s->mmio_index); >> =C2=A0 =C2=A0 sysbus_init_irq(dev, &s->irq); >> =C2=A0 =C2=A0 qemu_macaddr_default_if_unset(&s->conf.macaddr); >> - >> - =C2=A0 =C2=A0smc91c111_reset(s); >> - >> =C2=A0 =C2=A0 s->nic =3D qemu_new_nic(&net_smc91c111_info, &s->conf, >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 dev->qdev.info->name, dev->qdev.id, s); >> =C2=A0 =C2=A0 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); >> @@ -768,6 +766,7 @@ static SysBusDeviceInfo smc91c111_info =3D { >> =C2=A0 =C2=A0 .qdev.name =C2=A0=3D "smc91c111", >> =C2=A0 =C2=A0 .qdev.size =C2=A0=3D sizeof(smc91c111_state), >> =C2=A0 =C2=A0 .qdev.vmsd =3D &vmstate_smc91c111, >> + =C2=A0 =C2=A0.qdev.reset =3D smc91c111_reset, >> =C2=A0 =C2=A0 .qdev.props =3D (Property[]) { >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEFINE_NIC_PROPERTIES(smc91c111_state, conf)= , >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_END_OF_LIST(), >> -- >> 1.7.1 >> >> >> > > > > -- > 1234567890123456789012345678901234567890123456789012345678901234567890123= 4567890 > =C2=A0 =C2=A0 =C2=A0 =C2=A0=C2=A0 1 =C2=A0 =C2=A0 =C2=A0 =C2=A0 2 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 3 =C2=A0 =C2=A0 =C2=A0 =C2=A0 4 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 5 =C2=A0 =C2=A0 =C2=A0 =C2=A0 6 =C2=A0 =C2=A0 =C2=A0 =C2=A0 7 =C2=A0= =C2=A0 =C2=A0 =C2=A0 8 > >