From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45320) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHhRe-0007yK-9x for qemu-devel@nongnu.org; Wed, 04 May 2011 15:09:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHhRd-0003vT-7l for qemu-devel@nongnu.org; Wed, 04 May 2011 15:09:10 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:41317) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHhRc-0003vK-VO for qemu-devel@nongnu.org; Wed, 04 May 2011 15:09:09 -0400 Received: by qwj8 with SMTP id 8so1104237qwj.4 for ; Wed, 04 May 2011 12:09:08 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1304348602-28907-7-git-send-email-agraf@suse.de> References: <1304348602-28907-1-git-send-email-agraf@suse.de> <1304348602-28907-7-git-send-email-agraf@suse.de> From: Blue Swirl Date: Wed, 4 May 2011 22:08:48 +0300 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 6/6] PPC: Qdev'ify e500 pci List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Scott Wood , "Edgar E. Iglesias" , Liu Yu , QEMU-devel Developers On Mon, May 2, 2011 at 6:03 PM, Alexander Graf wrote: > The e500 PCI controller isn't qdev'ified yet. This leads to severe issues > when running with -drive. > > To be able to use a virtio disk with an e500 VM, let's convert the PCI > controller over to qdev. > > Signed-off-by: Alexander Graf > > --- > > v2 -> v3: > > =C2=A0- rebase to current code base > =C2=A0- fix endian issue > =C2=A0- use sysbus helpers > --- > =C2=A0hw/ppce500_pci.c | =C2=A0112 +++++++++++++++++++++++++++++++++++---= ---------------- > =C2=A01 files changed, 73 insertions(+), 39 deletions(-) > > diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c > index 83a20e4..88bc759 100644 > --- a/hw/ppce500_pci.c > +++ b/hw/ppce500_pci.c > @@ -73,11 +73,11 @@ struct pci_inbound { > =C2=A0}; > > =C2=A0struct PPCE500PCIState { > + =C2=A0 =C2=A0PCIHostState pci_state; > =C2=A0 =C2=A0 struct pci_outbound pob[PPCE500_PCI_NR_POBS]; > =C2=A0 =C2=A0 struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; > =C2=A0 =C2=A0 uint32_t gasket_time; > - =C2=A0 =C2=A0PCIHostState pci_state; > - =C2=A0 =C2=A0PCIDevice *pci_dev; > + =C2=A0 =C2=A0uint64_t base_addr; This does not seem to be used. Also devices shouldn't care about their base addresses.