From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=40641 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q6pCb-0001uL-7s for qemu-devel@nongnu.org; Mon, 04 Apr 2011 15:12:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q6pCa-00062K-78 for qemu-devel@nongnu.org; Mon, 04 Apr 2011 15:12:41 -0400 Received: from mail-fx0-f45.google.com ([209.85.161.45]:58748) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q6pCa-00061s-01 for qemu-devel@nongnu.org; Mon, 04 Apr 2011 15:12:40 -0400 Received: by fxm2 with SMTP id 2so4977921fxm.4 for ; Mon, 04 Apr 2011 12:12:38 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <20100522104440.18257.92813.stgit@skyserv> <20100522105234.18257.53650.stgit@skyserv> Date: Mon, 4 Apr 2011 23:12:38 +0400 Message-ID: Subject: Re: [Qemu-devel] [PATCH 4/5] sparc64: fix mmu context at trap levels above zero From: Igor Kovalenko Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel@nongnu.org, Artyom Tarasenko On Mon, Apr 4, 2011 at 10:37 PM, Blue Swirl wrote: > On Mon, Apr 4, 2011 at 8:25 PM, Artyom Tarasenko wr= ote: >> On Sat, May 22, 2010 at 12:52 PM, Igor V. Kovalenko >> wrote: >>> --- a/target-sparc/helper.c >>> +++ b/target-sparc/helper.c >>> @@ -572,6 +572,23 @@ static int get_physical_address(CPUState *env, tar= get_phys_addr_t *physical, >>> =A0 =A0 /* ??? We treat everything as a small page, then explicitly flu= sh >>> =A0 =A0 =A0 =A0everything when an entry is evicted. =A0*/ >>> =A0 =A0 *page_size =3D TARGET_PAGE_SIZE; >>> + >>> +#if defined (DEBUG_MMU) >>> + =A0 =A0/* safety net to catch wrong softmmu index use from dynamic co= de */ >> >> What does "wrong softmmu index" mean? Is it an error or an indication >> that something is not implemented? >> I'm hitting this net with the following message: > > The warning is not correct for CPUs without hypervisor mode. On T1/T2, > the default access mode when TL > 1 is hypervisor or nucleus mode. > Even then, the hypervisor could perform some accesses with kernel or > user ASIs. Right. The warning is still good for CODE access. Check itself was intended to catch reusing translated block of user or kernel mode after entering trap so it must be corrected. --=20 Kind regards, Igor V. Kovalenko