From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:58370) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHi6v-0001RU-Hd for qemu-devel@nongnu.org; Wed, 04 May 2011 15:51:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QHi6t-00034U-W4 for qemu-devel@nongnu.org; Wed, 04 May 2011 15:51:49 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:49075) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QHi6t-00034Q-S8 for qemu-devel@nongnu.org; Wed, 04 May 2011 15:51:47 -0400 Received: by qyk36 with SMTP id 36so3372450qyk.4 for ; Wed, 04 May 2011 12:51:47 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> References: <1304470768-16924-1-git-send-email-jcmvbkbc@gmail.com> From: Blue Swirl Date: Wed, 4 May 2011 22:51:27 +0300 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [RFC 01/28] target-xtensa: add target stubs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Max Filippov Cc: qemu-devel@nongnu.org On Wed, May 4, 2011 at 3:59 AM, Max Filippov wrote: > Signed-off-by: Max Filippov > --- > =C2=A0Makefile.target =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A02= + > =C2=A0arch_init.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 =C2=A02 + > =C2=A0arch_init.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2= =A0 =C2=A01 + > =C2=A0cpu-exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 10 +++++ > =C2=A0elf.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | =C2=A0 =C2=A02 + > =C2=A0hw/xtensa_pic.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 11 ++++= ++ > =C2=A0target-xtensa/cpu.h =C2=A0 =C2=A0 =C2=A0 | =C2=A0 84 ++++++++++++++= +++++++++++++++++++++++++++++++ > =C2=A0target-xtensa/exec.h =C2=A0 =C2=A0 =C2=A0| =C2=A0 55 ++++++++++++++= +++++++++++++++ > =C2=A0target-xtensa/helper.c =C2=A0 =C2=A0| =C2=A0 74 +++++++++++++++++++= ++++++++++++++++++++ > =C2=A0target-xtensa/machine.c =C2=A0 | =C2=A0 38 ++++++++++++++++++++ > =C2=A0target-xtensa/op_helper.c | =C2=A0 51 +++++++++++++++++++++++++++ > =C2=A0target-xtensa/translate.c | =C2=A0 67 +++++++++++++++++++++++++++++= ++++++ > =C2=A012 files changed, 397 insertions(+), 0 deletions(-) > =C2=A0create mode 100644 hw/xtensa_pic.c > =C2=A0create mode 100644 target-xtensa/cpu.h > =C2=A0create mode 100644 target-xtensa/exec.h > =C2=A0create mode 100644 target-xtensa/helper.c > =C2=A0create mode 100644 target-xtensa/machine.c > =C2=A0create mode 100644 target-xtensa/op_helper.c > =C2=A0create mode 100644 target-xtensa/translate.c > > diff --git a/Makefile.target b/Makefile.target > index 21f864a..7e7afd2 100644 > --- a/Makefile.target > +++ b/Makefile.target > @@ -366,6 +366,8 @@ obj-s390x-y =3D s390-virtio-bus.o s390-virtio.o > > =C2=A0obj-alpha-y =3D alpha_palcode.o > > +obj-xtensa-y +=3D xtensa_pic.o > + > =C2=A0main.o: QEMU_CFLAGS+=3D$(GPROF_CFLAGS) > > =C2=A0monitor.o: hmp-commands.h qmp-commands.h > diff --git a/arch_init.c b/arch_init.c > index 0c09f91..c1f0005 100644 > --- a/arch_init.c > +++ b/arch_init.c > @@ -78,6 +78,8 @@ const char arch_config_name[] =3D CONFIG_QEMU_CONFDIR "= /target-" TARGET_ARCH ".con > =C2=A0#define QEMU_ARCH QEMU_ARCH_SH4 > =C2=A0#elif defined(TARGET_SPARC) > =C2=A0#define QEMU_ARCH QEMU_ARCH_SPARC > +#elif defined(TARGET_XTENSA) > +#define QEMU_ARCH QEMU_ARCH_XTENSA > =C2=A0#endif > > =C2=A0const uint32_t arch_type =3D QEMU_ARCH; > diff --git a/arch_init.h b/arch_init.h > index 86ebc14..61ad347 100644 > --- a/arch_init.h > +++ b/arch_init.h > @@ -17,6 +17,7 @@ enum { > =C2=A0 =C2=A0 QEMU_ARCH_S390X =3D 512, > =C2=A0 =C2=A0 QEMU_ARCH_SH4 =3D 1024, > =C2=A0 =C2=A0 QEMU_ARCH_SPARC =3D 2048, > + =C2=A0 =C2=A0QEMU_ARCH_XTENSA =3D 4096, > =C2=A0}; > > =C2=A0extern const uint32_t arch_type; > diff --git a/cpu-exec.c b/cpu-exec.c > index 395cd8c..a692daf 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -275,6 +275,7 @@ int cpu_exec(CPUState *env1) > =C2=A0#elif defined(TARGET_SH4) > =C2=A0#elif defined(TARGET_CRIS) > =C2=A0#elif defined(TARGET_S390X) > +#elif defined(TARGET_XTENSA) > =C2=A0 =C2=A0 /* XXXXX */ > =C2=A0#else > =C2=A0#error unsupported target CPU > @@ -348,6 +349,8 @@ int cpu_exec(CPUState *env1) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 do_= interrupt(0); > =C2=A0#elif defined(TARGET_S390X) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 do_= interrupt(env); > +#elif defined(TARGET_XTENSA) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do= _interrupt(env); > =C2=A0#endif > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env= ->exception_index =3D -1; > =C2=A0#endif > @@ -568,6 +571,12 @@ int cpu_exec(CPUState *env1) > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 do_interrupt(env); > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 next_tb =3D 0; > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > +#elif defined(TARGET_XTENSA) > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if= (interrupt_request & CPU_INTERRUPT_HARD) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0env->exception_index =3D EXC_IRQ; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0do_interrupt(env); > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0next_tb =3D 0; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > =C2=A0#endif > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* D= on't use the cached interupt_request value, > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 do_interrupt may have updated the EXITTB flag. */ > @@ -696,6 +705,7 @@ int cpu_exec(CPUState *env1) > =C2=A0#elif defined(TARGET_ALPHA) > =C2=A0#elif defined(TARGET_CRIS) > =C2=A0#elif defined(TARGET_S390X) > +#elif defined(TARGET_XTENSA) > =C2=A0 =C2=A0 /* XXXXX */ > =C2=A0#else > =C2=A0#error unsupported target CPU > diff --git a/elf.h b/elf.h > index ffcac7e..2e05d34 100644 > --- a/elf.h > +++ b/elf.h > @@ -125,6 +125,8 @@ typedef int64_t =C2=A0Elf64_Sxword; > =C2=A0#define EM_MICROBLAZE =C2=A0 =C2=A0 =C2=A0189 > =C2=A0#define EM_MICROBLAZE_OLD =C2=A00xBAAB > > +#define EM_XTENSA =C2=A0 94 =C2=A0 =C2=A0 =C2=A0/* Tensilica Xtensa */ > + > =C2=A0/* This is the info that is needed to parse the dynamic section of = the file */ > =C2=A0#define DT_NULL =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A00 > =C2=A0#define DT_NEEDED =C2=A0 =C2=A0 =C2=A01 > diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c > new file mode 100644 > index 0000000..5ff1697 > --- /dev/null > +++ b/hw/xtensa_pic.c > @@ -0,0 +1,11 @@ > +#include "hw.h" > +#include "pc.h" > + > +/* Stub functions for hardware that doesn't exist. =C2=A0*/ > +void pic_info(Monitor *mon) > +{ > +} > + > +void irq_info(Monitor *mon) > +{ > +} > diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h > new file mode 100644 > index 0000000..ef6881a > --- /dev/null > +++ b/target-xtensa/cpu.h > @@ -0,0 +1,84 @@ > +/* > + * Copyright (c) 2011, Max Filippov, Motorola Solutions, Inc. > + * All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions ar= e met: > + * =C2=A0 =C2=A0 * Redistributions of source code must retain the above = copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer. > + * =C2=A0 =C2=A0 * Redistributions in binary form must reproduce the abo= ve copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer in the > + * =C2=A0 =C2=A0 =C2=A0 documentation and/or other materials provided wi= th the distribution. > + * =C2=A0 =C2=A0 * Neither the name of the Motorola Solutions nor the > + * =C2=A0 =C2=A0 =C2=A0 names of its contributors may be used to endorse= or promote products > + * =C2=A0 =C2=A0 =C2=A0 derived from this software without specific prio= r written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "= AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,= THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PU= RPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SE= RVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUS= ED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR= TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE= OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#ifndef CPU_XTENSA_H > +#define CPU_XTENSA_H > + > +#define TARGET_LONG_BITS 32 > +#define ELF_MACHINE EM_XTENSA > + > +#define CPUState struct CPUXtensaState > + > +#include "config.h" > +#include "qemu-common.h" > +#include "cpu-defs.h" > + > +#define TARGET_HAS_ICE 1 > + > +#define NB_MMU_MODES 2 > + > +#define TARGET_PHYS_ADDR_SPACE_BITS 32 > +#define TARGET_VIRT_ADDR_SPACE_BITS 32 > +#define TARGET_PAGE_BITS 12 > + > +typedef struct CPUXtensaState { > + =C2=A0 =C2=A0uint32_t regs[16]; > + =C2=A0 =C2=A0uint32_t pc; > + =C2=A0 =C2=A0uint32_t sregs[256]; > + > + =C2=A0 =C2=A0CPU_COMMON > +} CPUXtensaState; > + > +#define cpu_init cpu_xtensa_init > +#define cpu_exec cpu_xtensa_exec > +#define cpu_gen_code cpu_xtensa_gen_code > +#define cpu_signal_handler cpu_xtensa_signal_handler > +#define cpu_list xtensa_cpu_list > + > +CPUXtensaState *cpu_xtensa_init(const char *cpu_model); > +void xtensa_translate_init(void); > +int cpu_xtensa_exec(CPUXtensaState *s); > +void do_interrupt(CPUXtensaState *s); > +int cpu_xtensa_signal_handler(int host_signum, void *pinfo, void *puc); > +void xtensa_cpu_list(FILE *f, fprintf_function cpu_fprintf); > + > +static inline int cpu_mmu_index(CPUState *env) > +{ > + =C2=A0 =C2=A0return 0; > +} > + > +static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, > + =C2=A0 =C2=A0 =C2=A0 =C2=A0target_ulong *cs_base, int *flags) > +{ > + =C2=A0 =C2=A0*pc =3D env->pc; > + =C2=A0 =C2=A0*cs_base =3D 0; > + =C2=A0 =C2=A0*flags =3D 0; > +} > + > +#include "cpu-all.h" > + > +#endif > diff --git a/target-xtensa/exec.h b/target-xtensa/exec.h > new file mode 100644 > index 0000000..5a0cb6f > --- /dev/null > +++ b/target-xtensa/exec.h > @@ -0,0 +1,55 @@ > +/* > + * Copyright (c) 2011, Max Filippov, Motorola Solutions, Inc. > + * All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions ar= e met: > + * =C2=A0 =C2=A0 * Redistributions of source code must retain the above = copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer. > + * =C2=A0 =C2=A0 * Redistributions in binary form must reproduce the abo= ve copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer in the > + * =C2=A0 =C2=A0 =C2=A0 documentation and/or other materials provided wi= th the distribution. > + * =C2=A0 =C2=A0 * Neither the name of the Motorola Solutions nor the > + * =C2=A0 =C2=A0 =C2=A0 names of its contributors may be used to endorse= or promote products > + * =C2=A0 =C2=A0 =C2=A0 derived from this software without specific prio= r written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "= AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,= THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PU= RPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SE= RVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUS= ED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR= TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE= OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include "config.h" > +#include "dyngen-exec.h" > + > +register struct CPUXtensaState *env asm(AREG0); > + > +#include "cpu.h" > +#include "exec-all.h" > + > +static inline int cpu_has_work(CPUState *env) > +{ > + =C2=A0 =C2=A0return 1; > +} > + > +static inline int cpu_halted(CPUState *env) > +{ > + =C2=A0 =C2=A0return 0; > +} > + > +#if !defined(CONFIG_USER_ONLY) > +#include "softmmu_exec.h" > +#endif > + > +void raise_exception(int); > + > +static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) > +{ > + =C2=A0 =C2=A0env->pc =3D tb->pc; > +} > diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c > new file mode 100644 > index 0000000..6b6e17b > --- /dev/null > +++ b/target-xtensa/helper.c > @@ -0,0 +1,74 @@ > +/* > + * Copyright (c) 2011, Max Filippov, Motorola Solutions, Inc. > + * All rights reserved. > + * > + * Redistribution and use in source and binary forms, with or without > + * modification, are permitted provided that the following conditions ar= e met: > + * =C2=A0 =C2=A0 * Redistributions of source code must retain the above = copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer. > + * =C2=A0 =C2=A0 * Redistributions in binary form must reproduce the abo= ve copyright > + * =C2=A0 =C2=A0 =C2=A0 notice, this list of conditions and the followin= g disclaimer in the > + * =C2=A0 =C2=A0 =C2=A0 documentation and/or other materials provided wi= th the distribution. > + * =C2=A0 =C2=A0 * Neither the name of the Motorola Solutions nor the > + * =C2=A0 =C2=A0 =C2=A0 names of its contributors may be used to endorse= or promote products > + * =C2=A0 =C2=A0 =C2=A0 derived from this software without specific prio= r written permission. > + * > + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "= AS IS" > + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,= THE > + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PU= RPOSE > + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY > + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DA= MAGES > + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SE= RVICES; > + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUS= ED AND > + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR= TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE= OF THIS > + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + */ > + > +#include "cpu.h" > +#include "exec-all.h" > +#include "gdbstub.h" > +#include "qemu-common.h" > +#include "host-utils.h" > +#if !defined(CONFIG_USER_ONLY) > +#include "hw/loader.h" > +#endif > + > +void cpu_reset(CPUXtensaState *env) > +{ > + =C2=A0 =C2=A0env->pc =3D 0; > +} > + > +CPUXtensaState *cpu_xtensa_init(const char *cpu_model) > +{ > + =C2=A0 =C2=A0static int tcg_inited; > + =C2=A0 =C2=A0CPUXtensaState *env; > + > + =C2=A0 =C2=A0env =3D qemu_mallocz(sizeof(*env)); > + =C2=A0 =C2=A0cpu_exec_init(env); > + > + =C2=A0 =C2=A0if (!tcg_inited) { > + =C2=A0 =C2=A0 =C2=A0 =C2=A0tcg_inited =3D 1; > + =C2=A0 =C2=A0 =C2=A0 =C2=A0xtensa_translate_init(); > + =C2=A0 =C2=A0} > + > + =C2=A0 =C2=A0cpu_reset(env); CPU init should not call reset anymore, this is done elsewhere nowadays.