From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:43546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qcl4U-0004aX-MF for qemu-devel@nongnu.org; Fri, 01 Jul 2011 17:16:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qcl4S-00021j-Gu for qemu-devel@nongnu.org; Fri, 01 Jul 2011 17:16:18 -0400 Received: from mail-qy0-f180.google.com ([209.85.216.180]:50865) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qcl4S-00021b-3I for qemu-devel@nongnu.org; Fri, 01 Jul 2011 17:16:16 -0400 Received: by qyk30 with SMTP id 30so2162525qyk.4 for ; Fri, 01 Jul 2011 14:16:15 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <78deacb7abc46e23598060dadfb217e7fd5d0166.1309548174.git.atar4qemu@gmail.com> References: <78deacb7abc46e23598060dadfb217e7fd5d0166.1309548174.git.atar4qemu@gmail.com> Date: Fri, 1 Jul 2011 23:16:15 +0200 Message-ID: From: Laurent Desnogues Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH][sparc64] fix cpu_cc_src and cpu_cc_src2 corruption in udivx and sdivx List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Artyom Tarasenko Cc: blauwirbel@gmail.com, qemu-devel@nongnu.org On Fri, Jul 1, 2011 at 9:28 PM, Artyom Tarasenko wrot= e: > udivx and sdvix don't modify condition flags, so they shall not > overwrite cpu_cc_* Looks good to me. Laurent > Signed-off-by: Artyom Tarasenko > --- > =A0target-sparc/translate.c | =A0 32 ++++++++++++++++++++++---------- > =A01 files changed, 22 insertions(+), 10 deletions(-) > > diff --git a/target-sparc/translate.c b/target-sparc/translate.c > index 992cd77..f32a674 100644 > --- a/target-sparc/translate.c > +++ b/target-sparc/translate.c > @@ -727,19 +727,24 @@ static inline void gen_trap_ifdivzero_tl(TCGv divis= or) > =A0static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2) > =A0{ > =A0 =A0 int l1, l2; > + =A0 =A0TCGv r_temp1, r_temp2; > > =A0 =A0 l1 =3D gen_new_label(); > =A0 =A0 l2 =3D gen_new_label(); > - =A0 =A0tcg_gen_mov_tl(cpu_cc_src, src1); > - =A0 =A0tcg_gen_mov_tl(cpu_cc_src2, src2); > - =A0 =A0gen_trap_ifdivzero_tl(cpu_cc_src2); > - =A0 =A0tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src, INT64_MIN, l1); > - =A0 =A0tcg_gen_brcondi_tl(TCG_COND_NE, cpu_cc_src2, -1, l1); > + =A0 =A0r_temp1 =3D tcg_temp_local_new(); > + =A0 =A0r_temp2 =3D tcg_temp_local_new(); > + =A0 =A0tcg_gen_mov_tl(r_temp1, src1); > + =A0 =A0tcg_gen_mov_tl(r_temp2, src2); > + =A0 =A0gen_trap_ifdivzero_tl(r_temp2); > + =A0 =A0tcg_gen_brcondi_tl(TCG_COND_NE, r_temp1, INT64_MIN, l1); > + =A0 =A0tcg_gen_brcondi_tl(TCG_COND_NE, r_temp2, -1, l1); > =A0 =A0 tcg_gen_movi_i64(dst, INT64_MIN); > =A0 =A0 tcg_gen_br(l2); > =A0 =A0 gen_set_label(l1); > - =A0 =A0tcg_gen_div_i64(dst, cpu_cc_src, cpu_cc_src2); > + =A0 =A0tcg_gen_div_i64(dst, r_temp1, r_temp2); > =A0 =A0 gen_set_label(l2); > + =A0 =A0tcg_temp_free(r_temp1); > + =A0 =A0tcg_temp_free(r_temp2); > =A0} > =A0#endif > > @@ -3173,10 +3178,17 @@ static void disas_sparc_insn(DisasContext * dc) > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > =A0#ifdef TARGET_SPARC64 > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case 0xd: /* V9 udivx */ > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_mov_tl(cpu_cc_sr= c, cpu_src1); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_mov_tl(cpu_cc_sr= c2, cpu_src2); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0gen_trap_ifdivzero_tl(cp= u_cc_src2); > - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_divu_i64(cpu_dst= , cpu_cc_src, cpu_cc_src2); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0{ > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0TCGv r_temp1, r_= temp2; > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0r_temp1 =3D tcg_= temp_local_new(); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0r_temp2 =3D tcg_= temp_local_new(); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_mov_tl(r= _temp1, cpu_src1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_mov_tl(r= _temp2, cpu_src2); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0gen_trap_ifdivze= ro_tl(r_temp2); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_gen_divu_i64= (cpu_dst, r_temp1, r_temp2); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_temp_free(r_= temp1); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0tcg_temp_free(r_= temp2); > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0} > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 break; > =A0#endif > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 case 0xe: /* udiv */ > -- > 1.7.3.4 > >