Re: [Qemu-devel] QEMU testing methodology & results

[Blue Swirl <blauwirbel@gmail.com>]

On Fri, Apr 29, 2011 at 11:33 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> On 04/29/2011 02:17 AM, Peter Maydell wrote:
>>
>> The theoretical aim there as far
>> as I'm concerned is architectural correctness -- in other words we
>> should be a valid implementation of the architecture,
>
> That's not even the case for x86.  It should be a goal, however, that with
> mainstream kernels user programs shouldn't be able to see the difference.
>  There are some known issues besides bugs, for example the "instruction
> pointer of the last FP instruction" register (!) is not implemented.

For Sparc32 userland, I think the emulator is pretty close to correct
(or at least it could be very precise) since the instruction set is so
simple and there are very few corner cases. Maybe also for Sparc64,
where the set is not so simple anymore.

Still, things like order of exceptions may be tricky to implement
correctly. FPUs in QEMU execute synchronously to integer units.

Another case is that TCG needs to keep TBs and the instructions which
were used to generate the TBs in synch to support PC search (usually
this is needed anyway for example to support SMC on x86), but on Sparc
it should be possible to execute old code from cache while the
instructions have been modified in memory and no barrier instructions
have been issued.