From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54480) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFvMD-00083K-Ng for qemu-devel@nongnu.org; Fri, 29 Apr 2011 17:36:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QFvMC-0007Qp-Q4 for qemu-devel@nongnu.org; Fri, 29 Apr 2011 17:36:13 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:41553) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFvMC-0007Qc-LT for qemu-devel@nongnu.org; Fri, 29 Apr 2011 17:36:12 -0400 Received: by qwj8 with SMTP id 8so2266875qwj.4 for ; Fri, 29 Apr 2011 14:36:12 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: <4DB9C3AA.20907@codemonkey.ws> From: Blue Swirl Date: Sat, 30 Apr 2011 00:35:52 +0300 Message-ID: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] QEMU testing methodology & results List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: qemu-devel@nongnu.org On Fri, Apr 29, 2011 at 11:33 AM, Paolo Bonzini wrote= : > On 04/29/2011 02:17 AM, Peter Maydell wrote: >> >> The theoretical aim there as far >> as I'm concerned is architectural correctness -- in other words we >> should be a valid implementation of the architecture, > > That's not even the case for x86. =C2=A0It should be a goal, however, tha= t with > mainstream kernels user programs shouldn't be able to see the difference. > =C2=A0There are some known issues besides bugs, for example the "instruct= ion > pointer of the last FP instruction" register (!) is not implemented. For Sparc32 userland, I think the emulator is pretty close to correct (or at least it could be very precise) since the instruction set is so simple and there are very few corner cases. Maybe also for Sparc64, where the set is not so simple anymore. Still, things like order of exceptions may be tricky to implement correctly. FPUs in QEMU execute synchronously to integer units. Another case is that TCG needs to keep TBs and the instructions which were used to generate the TBs in synch to support PC search (usually this is needed anyway for example to support SMC on x86), but on Sparc it should be possible to execute old code from cache while the instructions have been modified in memory and no barrier instructions have been issued.