From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54244) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOCAi-00069I-Hm for qemu-devel@nongnu.org; Sun, 22 May 2011 13:10:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QOCAh-00080y-Kd for qemu-devel@nongnu.org; Sun, 22 May 2011 13:10:32 -0400 Received: from mail-iw0-f173.google.com ([209.85.214.173]:46817) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QOCAh-00080m-GN for qemu-devel@nongnu.org; Sun, 22 May 2011 13:10:31 -0400 Received: by iwl42 with SMTP id 42so4950554iwl.4 for ; Sun, 22 May 2011 10:10:29 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: References: Date: Sun, 22 May 2011 18:10:29 +0100 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 9/9] cpu-exec.c: avoid AREG0 use List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: qemu-devel On 22 May 2011 17:55, Blue Swirl wrote: > For ARM, the handcrafted instructions below need to be changed to save al= so r7: > =C2=A0 =C2=A0/* stmdb sp!, { r4 - r6, r8 - r11, lr } */ > =C2=A0 =C2=A0tcg_out32(s, (COND_AL << 28) | 0x092d4f70); > > =C2=A0 =C2=A0/* ldmia sp!, { r4 - r6, r8 - r11, pc } */ > =C2=A0 =C2=A0tcg_out32(s, (COND_AL << 28) | 0x08bd8f70); That would be ...ff0 rather than ...f70 in both cases (bottom 16 bits are a bit map of registers being saved/loaded): /* stmdb sp!, { r4 - r11, lr } */ tcg_out32(s, (COND_AL << 28) | 0x092d4ff0); /* ldmia sp!, { r4 - r11, pc } */ tcg_out32(s, (COND_AL << 28) | 0x08bd8ff0); -- PMM