From: Blue Swirl <blauwirbel@gmail.com>
To: Jan Kiszka <jan.kiszka@web.de>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH] target-i386: Initialize CPUState::halted in cpu_reset
Date: Tue, 26 Apr 2011 22:59:18 +0300 [thread overview]
Message-ID: <BANLkTimA5a3SNDdzXDgw68_JGq82vm1uEw@mail.gmail.com> (raw)
In-Reply-To: <4DB7151A.4000401@web.de>
On Tue, Apr 26, 2011 at 9:55 PM, Jan Kiszka <jan.kiszka@web.de> wrote:
> On 2011-04-26 20:00, Blue Swirl wrote:
>> On Tue, Apr 26, 2011 at 11:50 AM, Jan Kiszka <jan.kiszka@siemens.com> wrote:
>>> Instead of having an extra reset function at machine level and special
>>> code for processing INIT, move the initialization of halted into the
>>> cpu reset handler.
>>
>> Nack. A CPU is designated as a BSP at board level. CPUs do not need to
>> know about this at all.
>
> That's why we have cpu_is_bsp() in pc.c.
>
> Obviously, every CPU (which includes the APIC) must know if it is
> supposed to be BP or AP. It would be unable to enter the right state
> after reset otherwise (e.g. Intel SDM 9.1). cpu_is_bsp() is basically
> reporting the result of the MP init protocol in condensed from.
Intel 64 and IA-32 Architectures Software Developer’s Manual vol 3A,
7.5.1 says that the protocol result is stored in APIC MSR. I think we
should be using that instead. For example, the board could call
cpu_designate_bsp() to set the BSP flag in MSR. Then cpu_is_bsp()
would only check the MSR, which naturally belongs to the CPU/APIC
domain.
next prev parent reply other threads:[~2011-04-26 19:59 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-04-26 8:50 [Qemu-devel] [PATCH] target-i386: Initialize CPUState::halted in cpu_reset Jan Kiszka
2011-04-26 18:00 ` Blue Swirl
2011-04-26 18:55 ` Jan Kiszka
2011-04-26 19:59 ` Blue Swirl [this message]
2011-04-27 7:11 ` Jan Kiszka
2011-04-27 17:17 ` Blue Swirl
2011-04-27 17:32 ` Jan Kiszka
2011-04-27 18:29 ` Blue Swirl
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