From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([140.186.70.92]:44657)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <blauwirbel@gmail.com>) id 1QEoQ8-0001bD-2h
	for qemu-devel@nongnu.org; Tue, 26 Apr 2011 15:59:40 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <blauwirbel@gmail.com>) id 1QEoQ7-0007fX-1j
	for qemu-devel@nongnu.org; Tue, 26 Apr 2011 15:59:39 -0400
Received: from mail-vx0-f173.google.com ([209.85.220.173]:52903)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <blauwirbel@gmail.com>) id 1QEoQ6-0007fT-UO
	for qemu-devel@nongnu.org; Tue, 26 Apr 2011 15:59:39 -0400
Received: by vxb41 with SMTP id 41so865662vxb.4
	for <qemu-devel@nongnu.org>; Tue, 26 Apr 2011 12:59:38 -0700 (PDT)
MIME-Version: 1.0
In-Reply-To: <4DB7151A.4000401@web.de>
References: <4DB68768.3050700@siemens.com>
	<BANLkTikJFu2A9aEw2niF7fciTb+yqOVm7Q@mail.gmail.com>
	<4DB7151A.4000401@web.de>
From: Blue Swirl <blauwirbel@gmail.com>
Date: Tue, 26 Apr 2011 22:59:18 +0300
Message-ID: <BANLkTimA5a3SNDdzXDgw68_JGq82vm1uEw@mail.gmail.com>
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: quoted-printable
Subject: Re: [Qemu-devel] [PATCH] target-i386: Initialize CPUState::halted
	in cpu_reset
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Jan Kiszka <jan.kiszka@web.de>
Cc: qemu-devel <qemu-devel@nongnu.org>

On Tue, Apr 26, 2011 at 9:55 PM, Jan Kiszka <jan.kiszka@web.de> wrote:
> On 2011-04-26 20:00, Blue Swirl wrote:
>> On Tue, Apr 26, 2011 at 11:50 AM, Jan Kiszka <jan.kiszka@siemens.com> wr=
ote:
>>> Instead of having an extra reset function at machine level and special
>>> code for processing INIT, move the initialization of halted into the
>>> cpu reset handler.
>>
>> Nack. A CPU is designated as a BSP at board level. CPUs do not need to
>> know about this at all.
>
> That's why we have cpu_is_bsp() in pc.c.
>
> Obviously, every CPU (which includes the APIC) must know if it is
> supposed to be BP or AP. It would be unable to enter the right state
> after reset otherwise (e.g. Intel SDM 9.1). cpu_is_bsp() is basically
> reporting the result of the MP init protocol in condensed from.

Intel 64 and IA-32 Architectures Software Developer=E2=80=99s Manual vol 3A=
,
7.5.1 says that the protocol result is stored in APIC MSR. I think we
should be using that instead. For example, the board could call
cpu_designate_bsp() to set the BSP flag in MSR. Then cpu_is_bsp()
would only check the MSR, which naturally belongs to the CPU/APIC
domain.