From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40581) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLwK9-00062l-LA for qemu-devel@nongnu.org; Mon, 16 May 2011 07:51:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QLwK8-0003oV-R2 for qemu-devel@nongnu.org; Mon, 16 May 2011 07:50:57 -0400 MIME-Version: 1.0 Date: Mon, 16 May 2011 19:50:55 +0800 Message-ID: From: TeLeMan Content-Type: text/plain; charset=UTF-8 Subject: [Qemu-devel] [PATCH] piix_pci: fix piix3_set_irq_pic() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: qemu-trivial@nongnu.org, qemu-devel If pic_irq is greater than 7, the irq level is always 0 on 32bits. Signed-off-by: TeLeMan --- hw/piix_pci.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/piix_pci.c b/hw/piix_pci.c index 7f1c4cc..85a320e 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -312,7 +312,7 @@ static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) { qemu_set_irq(piix3->pic[pic_irq], !!(piix3->pic_levels & - (((1UL << PIIX_NUM_PIRQS) - 1) << + (((1ULL << PIIX_NUM_PIRQS) - 1) << (pic_irq * PIIX_NUM_PIRQS)))); } -- 1.7.3.1.msysgit.0 -- SUN OF A BEACH