From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:55383) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QAPit-0001FQ-CN for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:48:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QAPis-0002dE-9n for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:48:51 -0400 Received: from mail-vx0-f173.google.com ([209.85.220.173]:41122) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QAPis-0002d8-6Y for qemu-devel@nongnu.org; Thu, 14 Apr 2011 12:48:50 -0400 Received: by vxb41 with SMTP id 41so1710829vxb.4 for ; Thu, 14 Apr 2011 09:48:49 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <4DA7205E.1070208@twiddle.net> References: <1302645571-20500-1-git-send-email-aurelien@aurel32.net> <1302645571-20500-9-git-send-email-aurelien@aurel32.net> <4DA5C372.5090807@twiddle.net> <4DA70F43.90701@twiddle.net> <4DA7205E.1070208@twiddle.net> Date: Thu, 14 Apr 2011 17:48:48 +0100 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH 08/19] target-alpha: use new float64_unordered() function List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, Aurelien Jarno On 14 April 2011 17:27, Richard Henderson wrote: > On 04/14/2011 08:39 AM, Peter Maydell wrote: >>> =C2=A0Exponent underflow and disabled: >>> =C2=A0 =C2=A0Supply +0, no exception delivered to user. >>> >>> =C2=A0Exponent underflow and enabled: >>> =C2=A0 =C2=A0Supply +-MIN denorm, Underflow delivered to user. >>> >>> =C2=A0 =C2=A0Footnote 3, Overflow and Underflow have priority over Inex= act. >> >> Thanks. Does "no exception delivered to user" mean also >> "and do not set FPCR bit UNF" ? > > Yes. > >> The reason I thought it might set Inexact is that I was looking >> at page 4-79, which says: >> >> "If both the UNFD (underflow disable) bit and the UNDZ (underflow >> =C2=A0to zero) bit are set in the FPCR, the implementation sets the >> =C2=A0result of an underflow operation to a true zero result. The >> =C2=A0zeroing of a denormal result by UNDZ must also be treated as an >> =C2=A0inexact result." > > Hum. =C2=A0It looks like we can choose between these results then, > depending on the intersection of the FPCR disable bits, and > the per-instruction trapping mode bits (see section 4.7.7.2). > > I *think* what would be best for Alpha is if, within softfloat, > both conditions are signaled, and then we can filter the result > that is actually needed via helper_fp_exc_raise? =C2=A0It's hard to > say without actually doing the work... Unfortunately doing that is bad for other architectures because they tend to let the softfloat status flags act directly as the cumulative exception flags, so if softfloat sets flags they don't want you've suddenly imposed a burden of saving and restoring flags or something similarly ugly. It sounds like maybe what we need is to have a signed char float_ftz_flags or similar in float_status which should be set to the float_flags which should be passed to float_raise() when we flush an output denormal to zero. Then we can set that to float_flag_underflow for ARM, leave it at 0 for other architectures [preserve existing semantics] and set it to float_flag_underflow | float_flag_inexact for Alpha. Or the other approach would be to do something like how the 'denormal-input-went-to-zero' case is handled: have an extra float_flag for float_flag_output_denormal, and let targets either (a) special-case it or (b) merge it with whichever of underflow or inexact they like when constructing the guest-visible floating point status flags. I kind of like that better, actually. -- PMM