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From: Blue Swirl <blauwirbel@gmail.com>
Date: Sun, 10 Apr 2011 10:22:34 +0300
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Subject: [Qemu-devel] Re: [PATCHv2 3/3] unicore32: necessary modifications
 for other files to support unicore32
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To: Guan Xuetao <gxt@mprc.pku.edu.cn>
Cc: qemu-devel@nongnu.org

On Wed, Mar 30, 2011 at 11:29 AM, Guan Xuetao <gxt@mprc.pku.edu.cn> wrote:
>
> Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
> ---
> =C2=A0configure =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 11 +++-
> =C2=A0cpu-exec.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 12 ++++-
> =C2=A0default-configs/unicore32-linux-user.mak | =C2=A0 =C2=A01 +
> =C2=A0elf.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =
=C2=A02 +
> =C2=A0fpu/softfloat-specialize.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 | =C2=A0 10 ++--
> =C2=A0linux-user/elfload.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 74 +++++++++++++++++++++++++
> =C2=A0linux-user/main.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 89 +++++++++++++++++++++++++++++=
-
> =C2=A0linux-user/qemu.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| =C2=A0 =C2=A05 +-
> =C2=A0linux-user/syscall_defs.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
 =C2=A0 =C2=A0| =C2=A0 10 ++-
> =C2=A09 files changed, 201 insertions(+), 13 deletions(-)
> =C2=A0create mode 100644 default-configs/unicore32-linux-user.mak
>
> diff --git a/configure b/configure
> index 598e8e1..a6633cf 100755
> --- a/configure
> +++ b/configure
> @@ -280,7 +280,7 @@ else
> =C2=A0fi
>
> =C2=A0case "$cpu" in
> - =C2=A0alpha|cris|ia64|m68k|microblaze|ppc|ppc64|sparc64)
> + =C2=A0alpha|cris|ia64|m68k|microblaze|ppc|ppc64|sparc64|unicore32)

This patch does not apply anymore because of lm32 changes. Please rebase.

> =C2=A0 =C2=A0 cpu=3D"$cpu"
> =C2=A0 ;;
> =C2=A0 i386|i486|i586|i686|i86pc|BePC)
> @@ -793,6 +793,9 @@ case "$cpu" in
> =C2=A0 =C2=A0 hppa*)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0host_guest_base=3D"yes"
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0;;
> + =C2=A0 =C2=A0unicore32*)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 host_guest_base=3D"yes"
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ;;
> =C2=A0esac
>
> =C2=A0[ -z "$guest_base" ] && guest_base=3D"$host_guest_base"
> @@ -1018,6 +1021,7 @@ sh4eb-linux-user \
> =C2=A0sparc-linux-user \
> =C2=A0sparc64-linux-user \
> =C2=A0sparc32plus-linux-user \
> +unicore32-linux-user \
> =C2=A0"
> =C2=A0 =C2=A0 fi
> =C2=A0# the following are Darwin specific
> @@ -2495,7 +2499,7 @@ echo "docdir=3D$docdir" >> $config_host_mak
> =C2=A0echo "confdir=3D$confdir" >> $config_host_mak
>
> =C2=A0case "$cpu" in
> - =C2=A0i386|x86_64|alpha|cris|hppa|ia64|m68k|microblaze|mips|mips64|ppc|=
ppc64|s390|s390x|sparc|sparc64)
> + =C2=A0i386|x86_64|alpha|cris|hppa|ia64|m68k|microblaze|mips|mips64|ppc|=
ppc64|s390|s390x|sparc|sparc64|unicore32)
> =C2=A0 =C2=A0 ARCH=3D$cpu
> =C2=A0 ;;
> =C2=A0 armv4b|armv4l)
> @@ -3007,6 +3011,9 @@ case "$target_arch2" in
> =C2=A0 s390x)
> =C2=A0 =C2=A0 target_phys_bits=3D64
> =C2=A0 ;;
> + =C2=A0unicore32)
> + =C2=A0 =C2=A0target_phys_bits=3D32
> + =C2=A0;;
> =C2=A0 *)
> =C2=A0 =C2=A0 echo "Unsupported target CPU"
> =C2=A0 =C2=A0 exit 1
> diff --git a/cpu-exec.c b/cpu-exec.c
> index 8c9fb8b..130e0c3 100644
> --- a/cpu-exec.c
> +++ b/cpu-exec.c
> @@ -262,6 +262,7 @@ int cpu_exec(CPUState *env1)
> =C2=A0 =C2=A0 env->cc_x =3D (env->sr >> 4) & 1;
> =C2=A0#elif defined(TARGET_ALPHA)
> =C2=A0#elif defined(TARGET_ARM)
> +#elif defined(TARGET_UNICORE32)
> =C2=A0#elif defined(TARGET_PPC)
> =C2=A0#elif defined(TARGET_MICROBLAZE)
> =C2=A0#elif defined(TARGET_MIPS)
> @@ -326,6 +327,8 @@ int cpu_exec(CPUState *env1)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 do_=
interrupt(env);
> =C2=A0#elif defined(TARGET_ARM)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 do_=
interrupt(env);
> +#elif defined(TARGET_UNICORE32)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do=
_interrupt(env);
> =C2=A0#elif defined(TARGET_SH4)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0do_i=
nterrupt(env);
> =C2=A0#elif defined(TARGET_ALPHA)
> @@ -363,7 +366,7 @@ int cpu_exec(CPUState *env1)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> =C2=A0#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_=
MIPS) || \
> =C2=A0 =C2=A0 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TAR=
GET_CRIS) || \
> - =C2=A0 =C2=A0defined(TARGET_MICROBLAZE)
> + =C2=A0 =C2=A0defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if =
(interrupt_request & CPU_INTERRUPT_HALT) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 env->interrupt_request &=3D ~CPU_INTERRUPT_HALT;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 env->halted =3D 1;
> @@ -503,6 +506,12 @@ int cpu_exec(CPUState *env1)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 do_interrupt(env);
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 next_tb =3D 0;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> +#elif defined(TARGET_UNICORE32)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if=
 (interrupt_request & CPU_INTERRUPT_HARD
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0&& !(env->uncached_asr & ASR_I)) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0do_interrupt(env);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0next_tb =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> =C2=A0#elif defined(TARGET_SH4)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if =
(interrupt_request & CPU_INTERRUPT_HARD) {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 do_interrupt(env);
> @@ -653,6 +662,7 @@ int cpu_exec(CPUState *env1)
> =C2=A0 =C2=A0 env->eflags =3D env->eflags | helper_cc_compute_all(CC_OP) =
| (DF & DF_MASK);
> =C2=A0#elif defined(TARGET_ARM)
> =C2=A0 =C2=A0 /* XXX: Save/restore host fpu exception state?. =C2=A0*/
> +#elif defined(TARGET_UNICORE32)
> =C2=A0#elif defined(TARGET_SPARC)
> =C2=A0#elif defined(TARGET_PPC)
> =C2=A0#elif defined(TARGET_M68K)
> diff --git a/default-configs/unicore32-linux-user.mak b/default-configs/u=
nicore32-linux-user.mak
> new file mode 100644
> index 0000000..6aafd21
> --- /dev/null
> +++ b/default-configs/unicore32-linux-user.mak
> @@ -0,0 +1 @@
> +# Default configuration for unicore32-linux-user
> diff --git a/elf.h b/elf.h
> index 7067c90..876c1da 100644
> --- a/elf.h
> +++ b/elf.h
> @@ -105,6 +105,8 @@ typedef int64_t =C2=A0Elf64_Sxword;
> =C2=A0#define EM_H8_300H =C2=A0 =C2=A0 =C2=A047 =C2=A0 =C2=A0 =C2=A0/* Hi=
tachi H8/300H */
> =C2=A0#define EM_H8S =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A048 =C2=A0 =C2=A0 =
=C2=A0/* Hitachi H8S =C2=A0 =C2=A0 */
>
> +#define EM_UNICORE32 =C2=A0 =C2=A0110 =C2=A0 =C2=A0 /* UniCore32 */
> +
> =C2=A0/*
> =C2=A0* This is an interim value that we will use until the committee com=
es
> =C2=A0* up with a final number.
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index eb644b2..839049d 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -30,7 +30,7 @@ these four paragraphs for those parts of this code that=
 are retained.
>
> =C2=A0=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D*/
>
> -#if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +#if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICOR=
E32)
> =C2=A0#define SNAN_BIT_IS_ONE =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A01
> =C2=A0#else
> =C2=A0#define SNAN_BIT_IS_ONE =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A00
> @@ -108,7 +108,7 @@ float32 float32_maybe_silence_nan( float32 a_ )
> =C2=A0{
> =C2=A0 =C2=A0 if (float32_is_signaling_nan(a_)) {
> =C2=A0#if SNAN_BIT_IS_ONE
> -# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET=
_UNICORE32)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 return float32_default_nan;
> =C2=A0# =C2=A0else
> =C2=A0# =C2=A0 =C2=A0error Rules for silencing a signaling NaN are target=
-specific
> @@ -362,7 +362,7 @@ float64 float64_maybe_silence_nan( float64 a_ )
> =C2=A0{
> =C2=A0 =C2=A0 if (float64_is_signaling_nan(a_)) {
> =C2=A0#if SNAN_BIT_IS_ONE
> -# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET=
_UNICORE32)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 return float64_default_nan;
> =C2=A0# =C2=A0else
> =C2=A0# =C2=A0 =C2=A0error Rules for silencing a signaling NaN are target=
-specific
> @@ -519,7 +519,7 @@ floatx80 floatx80_maybe_silence_nan( floatx80 a )
> =C2=A0{
> =C2=A0 =C2=A0 if (floatx80_is_signaling_nan(a)) {
> =C2=A0#if SNAN_BIT_IS_ONE
> -# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET=
_UNICORE32)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 a.low =3D floatx80_default_nan_low;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 a.high =3D floatx80_default_nan_high;
> =C2=A0# =C2=A0else
> @@ -668,7 +668,7 @@ float128 float128_maybe_silence_nan( float128 a )
> =C2=A0{
> =C2=A0 =C2=A0 if (float128_is_signaling_nan(a)) {
> =C2=A0#if SNAN_BIT_IS_ONE
> -# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4)
> +# =C2=A0if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET=
_UNICORE32)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 a.low =3D float128_default_nan_low;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 a.high =3D float128_default_nan_high;
> =C2=A0# =C2=A0else
> diff --git a/linux-user/elfload.c b/linux-user/elfload.c
> index 08c44d8..0fdb2ed 100644
> --- a/linux-user/elfload.c
> +++ b/linux-user/elfload.c
> @@ -339,6 +339,80 @@ enum
>
> =C2=A0#endif
>
> +#ifdef TARGET_UNICORE32
> +
> +#define ELF_START_MMAP =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x80000000
> +
> +#define elf_check_arch(x) =C2=A0 =C2=A0 =C2=A0 ((x) =3D=3D EM_UNICORE32)
> +
> +#define ELF_CLASS =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ELFCL=
ASS32
> +#define ELF_DATA =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
ELFDATA2LSB
> +#define ELF_ARCH =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0=
EM_UNICORE32
> +
> +static inline void init_thread(struct target_pt_regs *regs,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0struct image_info *infop)
> +{
> + =C2=A0 =C2=A0abi_long stack =3D infop->start_stack;
> + =C2=A0 =C2=A0memset(regs, 0, sizeof(*regs));
> + =C2=A0 =C2=A0regs->UC32_REG_asr =3D 0x10;
> + =C2=A0 =C2=A0regs->UC32_REG_pc =3D infop->entry & 0xfffffffe;
> + =C2=A0 =C2=A0regs->UC32_REG_sp =3D infop->start_stack;
> + =C2=A0 =C2=A0/* FIXME - what to for failure of get_user()? */
> + =C2=A0 =C2=A0get_user_ual(regs->UC32_REG_02, stack + 8); /* envp */
> + =C2=A0 =C2=A0get_user_ual(regs->UC32_REG_01, stack + 4); /* envp */
> + =C2=A0 =C2=A0/* XXX: it seems that r0 is zeroed after ! */
> + =C2=A0 =C2=A0regs->UC32_REG_00 =3D 0;
> +}
> +
> +#define ELF_NREG =C2=A0 =C2=A034
> +typedef target_elf_greg_t =C2=A0target_elf_gregset_t[ELF_NREG];
> +
> +static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUStat=
e *env)
> +{
> + =C2=A0 =C2=A0(*regs)[0] =3D env->regs[0];
> + =C2=A0 =C2=A0(*regs)[1] =3D env->regs[1];
> + =C2=A0 =C2=A0(*regs)[2] =3D env->regs[2];
> + =C2=A0 =C2=A0(*regs)[3] =3D env->regs[3];
> + =C2=A0 =C2=A0(*regs)[4] =3D env->regs[4];
> + =C2=A0 =C2=A0(*regs)[5] =3D env->regs[5];
> + =C2=A0 =C2=A0(*regs)[6] =3D env->regs[6];
> + =C2=A0 =C2=A0(*regs)[7] =3D env->regs[7];
> + =C2=A0 =C2=A0(*regs)[8] =3D env->regs[8];
> + =C2=A0 =C2=A0(*regs)[9] =3D env->regs[9];
> + =C2=A0 =C2=A0(*regs)[10] =3D env->regs[10];
> + =C2=A0 =C2=A0(*regs)[11] =3D env->regs[11];
> + =C2=A0 =C2=A0(*regs)[12] =3D env->regs[12];
> + =C2=A0 =C2=A0(*regs)[13] =3D env->regs[13];
> + =C2=A0 =C2=A0(*regs)[14] =3D env->regs[14];
> + =C2=A0 =C2=A0(*regs)[15] =3D env->regs[15];
> + =C2=A0 =C2=A0(*regs)[16] =3D env->regs[16];
> + =C2=A0 =C2=A0(*regs)[17] =3D env->regs[17];
> + =C2=A0 =C2=A0(*regs)[18] =3D env->regs[18];
> + =C2=A0 =C2=A0(*regs)[19] =3D env->regs[19];
> + =C2=A0 =C2=A0(*regs)[20] =3D env->regs[20];
> + =C2=A0 =C2=A0(*regs)[21] =3D env->regs[21];
> + =C2=A0 =C2=A0(*regs)[22] =3D env->regs[22];
> + =C2=A0 =C2=A0(*regs)[23] =3D env->regs[23];
> + =C2=A0 =C2=A0(*regs)[24] =3D env->regs[24];
> + =C2=A0 =C2=A0(*regs)[25] =3D env->regs[25];
> + =C2=A0 =C2=A0(*regs)[26] =3D env->regs[26];
> + =C2=A0 =C2=A0(*regs)[27] =3D env->regs[27];
> + =C2=A0 =C2=A0(*regs)[28] =3D env->regs[28];
> + =C2=A0 =C2=A0(*regs)[29] =3D env->regs[29];
> + =C2=A0 =C2=A0(*regs)[30] =3D env->regs[30];
> + =C2=A0 =C2=A0(*regs)[31] =3D env->regs[31];
> +
> + =C2=A0 =C2=A0(*regs)[32] =3D cpu_asr_read((CPUState *)env);
> + =C2=A0 =C2=A0(*regs)[33] =3D env->regs[0]; /* XXX */
> +}
> +
> +#define USE_ELF_CORE_DUMP
> +#define ELF_EXEC_PAGESIZE =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 4096
> +
> +#define ELF_HWCAP =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 (UC32_HWCAP_CMOV | UC32_HWCAP_UCF64)
> +
> +#endif
> +
> =C2=A0#ifdef TARGET_SPARC
> =C2=A0#ifdef TARGET_SPARC64
>
> diff --git a/linux-user/main.c b/linux-user/main.c
> index 0d627d6..29ade8b 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -816,6 +816,83 @@ void cpu_loop(CPUARMState *env)
>
> =C2=A0#endif
>
> +#ifdef TARGET_UNICORE32
> +
> +void cpu_loop(CPUState *env)
> +{
> + =C2=A0 =C2=A0int trapnr;
> + =C2=A0 =C2=A0unsigned int n, insn;
> + =C2=A0 =C2=A0target_siginfo_t info;
> +
> + =C2=A0 =C2=A0for (;;) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_exec_start(env);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0trapnr =3D uc32_cpu_exec(env);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_exec_end(env);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0switch (trapnr) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0case UC32_EXCP_PRIV:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* system call *=
/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0get_user_u32(ins=
n, env->regs[31] - 4);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0n =3D insn & 0xf=
fffff;
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (n >=3D UC32_=
SYSCALL_BASE) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/*=
 linux syscall */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0n =
-=3D UC32_SYSCALL_BASE;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if=
 (n =3D=3D UC32_SYSCALL_NR_set_tls) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_set_tls(env, env->regs[0]);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[0] =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} =
else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0env->regs[0] =3D do_syscall(env,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0n,
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[0],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[1],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[2],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[3],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[4],
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[5]);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0go=
to error;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0case UC32_EXCP_TRAP:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0info.si_signo =3D SIGSEGV;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0info.si_errno =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* XXX: check env->error_code =
*/
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0info.si_code =3D TARGET_SEGV_M=
APERR;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0info._sifields._sigfault._addr=
 =3D env->cp0.c4_faultaddr;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0queue_signal(env, info.si_sign=
o, &info);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0case EXCP_INTERRUPT:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* just indicate that signals =
should be handled asap */
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0case EXCP_DEBUG:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int sig;
> +
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0sig =3D gdb_hand=
lesig(env, TARGET_SIGTRAP);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (sig) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in=
fo.si_signo =3D sig;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in=
fo.si_errno =3D 0;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0in=
fo.si_code =3D TARGET_TRAP_BRKPT;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qu=
eue_signal(env, info.si_signo, &info);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0break;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0default:
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0goto error;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0process_pending_signals(env);
> + =C2=A0 =C2=A0}
> +
> +error:
> + =C2=A0 =C2=A0fprintf(stderr, "qemu: unhandled CPU exception 0x%x - abor=
ting\n", trapnr);
> + =C2=A0 =C2=A0cpu_dump_state(env, stderr, fprintf, 0);
> + =C2=A0 =C2=A0abort();
> +}
> +#endif
> +
> =C2=A0#ifdef TARGET_SPARC
> =C2=A0#define SPARC64_STACK_BIAS 2047
>
> @@ -2916,6 +2993,8 @@ int main(int argc, char **argv, char **envp)
> =C2=A0#endif
> =C2=A0#elif defined(TARGET_ARM)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_model =3D "any";
> +#elif defined(TARGET_UNICORE32)
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_model =3D "any";
> =C2=A0#elif defined(TARGET_M68K)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 cpu_model =3D "any";
> =C2=A0#elif defined(TARGET_SPARC)
> @@ -3218,6 +3297,14 @@ int main(int argc, char **argv, char **envp)
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 env->regs[i] =3D regs->uregs[i]=
;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
> =C2=A0 =C2=A0 }
> +#elif defined(TARGET_UNICORE32)
> + =C2=A0 =C2=A0{
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0int i;
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0cpu_asr_write(env, regs->uregs[32], 0xffffff=
ff);
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0for (i =3D 0; i < 32; i++) {
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0env->regs[i] =3D regs->uregs[i=
];
> + =C2=A0 =C2=A0 =C2=A0 =C2=A0}
> + =C2=A0 =C2=A0}
> =C2=A0#elif defined(TARGET_SPARC)
> =C2=A0 =C2=A0 {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 int i;
> @@ -3358,7 +3445,7 @@ int main(int argc, char **argv, char **envp)
> =C2=A0#error unsupported target CPU
> =C2=A0#endif
>
> -#if defined(TARGET_ARM) || defined(TARGET_M68K)
> +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICOR=
E32)
> =C2=A0 =C2=A0 ts->stack_base =3D info->start_stack;
> =C2=A0 =C2=A0 ts->heap_base =3D info->brk;
> =C2=A0 =C2=A0 /* This will be filled in on the first SYS_HEAPINFO call. =
=C2=A0*/
> diff --git a/linux-user/qemu.h b/linux-user/qemu.h
> index 32de241..39218f4 100644
> --- a/linux-user/qemu.h
> +++ b/linux-user/qemu.h
> @@ -98,6 +98,9 @@ typedef struct TaskState {
> =C2=A0 =C2=A0 FPA11 fpa;
> =C2=A0 =C2=A0 int swi_errno;
> =C2=A0#endif
> +#ifdef TARGET_UNICORE32
> + =C2=A0 =C2=A0int swi_errno;
> +#endif
> =C2=A0#if defined(TARGET_I386) && !defined(TARGET_X86_64)
> =C2=A0 =C2=A0 abi_ulong target_v86;
> =C2=A0 =C2=A0 struct vm86_saved_state vm86_saved_regs;
> @@ -111,7 +114,7 @@ typedef struct TaskState {
> =C2=A0#ifdef TARGET_M68K
> =C2=A0 =C2=A0 int sim_syscalls;
> =C2=A0#endif
> -#if defined(TARGET_ARM) || defined(TARGET_M68K)
> +#if defined(TARGET_ARM) || defined(TARGET_M68K) || defined(TARGET_UNICOR=
E32)
> =C2=A0 =C2=A0 /* Extra fields for semihosted binaries. =C2=A0*/
> =C2=A0 =C2=A0 uint32_t stack_base;
> =C2=A0 =C2=A0 uint32_t heap_base;
> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> index d02a9bf..daa2107 100644
> --- a/linux-user/syscall_defs.h
> +++ b/linux-user/syscall_defs.h
> @@ -55,7 +55,7 @@
> =C2=A0#endif
>
> =C2=A0#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_S=
H4) \
> - =C2=A0 =C2=A0|| defined(TARGET_M68K) || defined(TARGET_CRIS)
> + =C2=A0 =C2=A0|| defined(TARGET_M68K) || defined(TARGET_CRIS) || defined=
(TARGET_UNICORE32)
>
> =C2=A0#define TARGET_IOC_SIZEBITS =C2=A0 =C2=A014
> =C2=A0#define TARGET_IOC_DIRBITS =C2=A0 =C2=A0 2
> @@ -315,7 +315,10 @@ struct target_sigaction;
> =C2=A0int do_sigaction(int sig, const struct target_sigaction *act,
> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0struct targ=
et_sigaction *oact);
>
> -#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC)=
 || defined(TARGET_PPC) || defined(TARGET_MIPS) || defined
> (TARGET_SH4) || defined(TARGET_M68K) || defined(TARGET_ALPHA) || defined(=
TARGET_CRIS) || defined(TARGET_MICROBLAZE)
> +#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SPARC)=
 \
> + =C2=A0 =C2=A0|| defined(TARGET_PPC) || defined(TARGET_MIPS) || defined(=
TARGET_SH4) \
> + =C2=A0 =C2=A0|| defined(TARGET_M68K) || defined(TARGET_ALPHA) || define=
d(TARGET_CRIS) \
> + =C2=A0 =C2=A0|| defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32)
>
> =C2=A0#if defined(TARGET_SPARC)
> =C2=A0#define TARGET_SA_NOCLDSTOP =C2=A0 =C2=A08u
> @@ -1001,7 +1004,8 @@ struct target_winsize {
> =C2=A0#define TARGET_MAP_NONBLOCK =C2=A0 =C2=A00x10000 =C2=A0 =C2=A0 =C2=
=A0 =C2=A0 /* do not block on IO */
> =C2=A0#endif
>
> -#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_AR=
M) || defined(TARGET_CRIS)
> +#if (defined(TARGET_I386) && defined(TARGET_ABI32)) || defined(TARGET_AR=
M) \
> + =C2=A0 =C2=A0|| defined(TARGET_CRIS) || defined(TARGET_UNICORE32)
> =C2=A0struct target_stat {
> =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned short st_dev;
> =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned short __pad1;
> --
> 1.6.2.2
>
>
>