From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34626) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QG0nP-0007YS-Rv for qemu-devel@nongnu.org; Fri, 29 Apr 2011 23:24:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QG0nO-0004Zi-Nq for qemu-devel@nongnu.org; Fri, 29 Apr 2011 23:24:39 -0400 Received: from mail-qy0-f173.google.com ([209.85.216.173]:51394) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QFuvR-0003k4-7j for qemu-devel@nongnu.org; Fri, 29 Apr 2011 17:08:33 -0400 Received: by qyk36 with SMTP id 36so534161qyk.4 for ; Fri, 29 Apr 2011 14:08:32 -0700 (PDT) MIME-Version: 1.0 Date: Sat, 30 Apr 2011 01:08:31 +0400 Message-ID: From: Max Filippov Content-Type: text/plain; charset=ISO-8859-1 Subject: [Qemu-devel] xtensa: new target architecture for qemu List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Hello. I'm developing support for new qemu target architecture: xtensa [1], primarily because AFAIK there's no free/open simulator for this architecture. Essential ISA parts (like core opcodes, special registers, windowed registers, exceptions and interrupts) are implemented, other (like TLB, MMU, caches, coprocessors, rare opcodes) are not, although I'm planning to implement them if/when needed. I'm wondering if this target could be eligible for inclusion into qemu mainline. If it is, could anyone please review the code [2]? There are several known issues which I'm planning to address: - mixed coding style; - no copyrights/license (it is BSD); - no direct TB linking; - dummy cpu_halted/cpu_has_work. If you see more, please report, especially if you know how to fix them (: [1] http://en.wikipedia.org/wiki/Tensilica [2] http://jcmvbkbc.spb.ru/git/?p=dumb/qemu-xtensa.git;a=shortlog;h=refs/heads/xtensa Thanks. -- Max