From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:50546) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTElI-0001qj-7n for qemu-devel@nongnu.org; Sun, 05 Jun 2011 10:57:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QTElG-0004HJ-L6 for qemu-devel@nongnu.org; Sun, 05 Jun 2011 10:57:08 -0400 Received: from mail-pw0-f45.google.com ([209.85.160.45]:57343) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QTElG-0004G2-28 for qemu-devel@nongnu.org; Sun, 05 Jun 2011 10:57:06 -0400 Received: by pwi6 with SMTP id 6so1839561pwi.4 for ; Sun, 05 Jun 2011 07:57:04 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <4DEB900F.5070206@embedded-brains.de> References: <4DEB5AFF.3010604@embedded-brains.de> <4DEB7F55.9030700@embedded-brains.de> <4DEB900F.5070206@embedded-brains.de> Date: Sun, 5 Jun 2011 15:57:02 +0100 Message-ID: From: Peter Maydell Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] Disable interrupts on Cortex M3 (lm3s6965evb) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sebastian Huber Cc: qemu-devel@nongnu.org, Paul Brook On 5 June 2011 15:17, Sebastian Huber wrote: > On 05/06/11 15:44, Peter Maydell wrote: >> In any case, M profile exception priority handling is sufficiently >> complicated that any change which only looks at PRIMASK (which is >> effectively what the change to look at CPSR_I here is doing) is >> almost certainly wrong. I think that whatever is raising the >> interrupt should be looking at the CPU priority and not raising it >> in the first place. > Yes. =C2=A0Please have a look at: > > http://lists.nongnu.org/archive/html/qemu-devel/2011-05/msg03132.html That patch does correct an error in the decode of the basepri registers (and so we might as well apply it), but it does not affect the fact that the underlying v7m.basepri field is not actually used for anything. >> (It looks suspiciously as if most of the v7M priority handling >> is simply missing from QEMU, ie you have bigger problems than >> can be fixed by a small patch like this...) > Yes, but the current behaviour is definitely not right. =C2=A0Since the > PRIMASK is mapped to the I bit in the CPSR I guessed that this was the > right place to fix it. I agree that the current behaviour is not right. However, to fix this problem you need to work on a larger scale than attempting to apply two line patches which fix your particular use case. -- PMM