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From: Blue Swirl <blauwirbel@gmail.com>
Date: Mon, 4 Apr 2011 21:37:28 +0300
Message-ID: <BANLkTinQbXLxQun_mGfFi9mmVsY1H=DpiQ@mail.gmail.com>
Subject: Re: [Qemu-devel] [PATCH 4/5] sparc64: fix mmu context at trap levels
	above zero
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To: Artyom Tarasenko <atar4qemu@gmail.com>
Cc: qemu-devel@nongnu.org

On Mon, Apr 4, 2011 at 8:25 PM, Artyom Tarasenko <atar4qemu@gmail.com> wrot=
e:
> On Sat, May 22, 2010 at 12:52 PM, Igor V. Kovalenko
> <igor.v.kovalenko@gmail.com> wrote:
>> --- a/target-sparc/helper.c
>> +++ b/target-sparc/helper.c
>> @@ -572,6 +572,23 @@ static int get_physical_address(CPUState *env, targ=
et_phys_addr_t *physical,
>> =C2=A0 =C2=A0 /* ??? We treat everything as a small page, then explicitl=
y flush
>> =C2=A0 =C2=A0 =C2=A0 =C2=A0everything when an entry is evicted. =C2=A0*/
>> =C2=A0 =C2=A0 *page_size =3D TARGET_PAGE_SIZE;
>> +
>> +#if defined (DEBUG_MMU)
>> + =C2=A0 =C2=A0/* safety net to catch wrong softmmu index use from dynam=
ic code */
>
> What does "wrong softmmu index" mean? Is it an error or an indication
> that something is not implemented?
> I'm hitting this net with the following message:

The warning is not correct for CPUs without hypervisor mode. On T1/T2,
the default access mode when TL > 1 is hypervisor or nucleus mode.
Even then, the hypervisor could perform some accesses with kernel or
user ASIs.