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Date: Sat, 18 Jun 2011 23:11:31 +0100
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From: Peter Maydell <peter.maydell@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH] Sparc32: dummy implementation of MXCC MMU
 breakpoint registers
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To: Blue Swirl <blauwirbel@gmail.com>
Cc: Bob Breuer <breuerr@mc.net>, qemu-devel <qemu-devel@nongnu.org>, Robert Reif <reif@earthlink.net>

On 18 June 2011 22:45, Blue Swirl <blauwirbel@gmail.com> wrote:
> Add dummy registers for SuperSPARC MXCC MMU counter breakpoints.
>
> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 320530e..b5d5291 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -403,6 +403,7 @@ typedef struct CPUSPARCState {
> =C2=A0 =C2=A0 uint32_t mmuregs[32];
> =C2=A0 =C2=A0 uint64_t mxccdata[4];
> =C2=A0 =C2=A0 uint64_t mxccregs[8];
> + =C2=A0 =C2=A0uint32_t mmubpctrv, mmubpctrc, mmubpctrs, mmubpaction;
> =C2=A0 =C2=A0 uint64_t mmubpregs[4];
> =C2=A0 =C2=A0 uint64_t prom_addr;
> =C2=A0#endif

Shouldn't there be a corresponding change to target-sparc/machine.c
adding these to cpu_save()/cpu_load() ?  [the existing mxccdata,
mxccregs, mmubpregs don't seem to be saved/restored either...]

-- PMM