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From: Blue Swirl <blauwirbel@gmail.com>
Date: Wed, 11 May 2011 20:35:47 +0300
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Subject: Re: [Qemu-devel] TCG: AREG0 removal planning
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To: Paul Brook <paul@codesourcery.com>
Cc: qemu-devel@nongnu.org, Richard Henderson <rth@twiddle.net>

On Wed, May 11, 2011 at 1:57 AM, Paul Brook <paul@codesourcery.com> wrote:
>> While we're at it, let us change things a bit further to allow guest
>> byte-swap load/store insns to be implemented more efficiently. =C2=A0For
>> instance, currently a sparc load_asr (little-endian), as emulated on
>> an x86 host, does the byte swap twice.
>
> FWIW this also ends up interacting with the device and bus models. This i=
s
> partially implemented by the endian parameter of cpu_register_io_memory e=
t.
> al. =C2=A0This may also be a runtime property, either part of the CPU sta=
te (e.g.
> ARM where instruction and data accesses may have different endianness), o=
r
> even a per-page TLB attribute (PPC?).

SuperSparc (Sparc32) MMU had a bit for reversing the endianness of a
page, on Sparc64 there are many levels where this can be done (global
CPU mode flag, MMU page flag and some memory accesses can use byte
swapping ASIs). I don't think they are used though.