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[77.188.68.61]) by smtp.gmail.com with ESMTPSA id uz25-20020a170907119900b008eb89a435c9sm6118315ejb.164.2023.03.01.13.08.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Mar 2023 13:08:40 -0800 (PST) Date: Wed, 01 Mar 2023 21:08:37 +0000 From: Bernhard Beschow To: BALATON Zoltan CC: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Gerd Hoffmann , Daniel Henrique Barboza , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Subject: Re: [PATCH v5 3/7] hw/isa/vt82c686: Implement PCI IRQ routing In-Reply-To: <794ef01a-730b-46c6-2e79-95c68bc42102@eik.bme.hu> References: <36574dd259a98b240bfe12cd9ffa30b778bf06eb.1677628524.git.balaton@eik.bme.hu> <375EC0ED-F7D8-4A40-B316-F7BA32709836@gmail.com> <794ef01a-730b-46c6-2e79-95c68bc42102@eik.bme.hu> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=shentey@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 1=2E M=C3=A4rz 2023 11:15:02 UTC schrieb BALATON Zoltan : >On Wed, 1 Mar 2023, Bernhard Beschow wrote: >> Am 1=2E M=C3=A4rz 2023 00:17:09 UTC schrieb BALATON Zoltan : >>> The real VIA south bridges implement a PCI IRQ router which is configu= red >>> by the BIOS or the OS=2E In order to respect these configurations, QEM= U >>> needs to implement it as well=2E The real chip may allow routing IRQs = from >>> internal functions independently of PCI interrupts but since guests >>> usually configute it to a single shared interrupt we don't model that >>> here for simplicity=2E >>>=20 >>> Note: The implementation was taken from piix4_set_irq() in hw/isa/piix= 4=2E >>>=20 >>> Suggested-by: Bernhard Beschow >>> Signed-off-by: BALATON Zoltan >>> --- >>> hw/isa/vt82c686=2Ec | 38 +++++++++++++++++++++++++++++++++++++- >>> 1 file changed, 37 insertions(+), 1 deletion(-) >>>=20 >>> diff --git a/hw/isa/vt82c686=2Ec b/hw/isa/vt82c686=2Ec >>> index 01e0148967=2E=2E018a119964 100644 >>> --- a/hw/isa/vt82c686=2Ec >>> +++ b/hw/isa/vt82c686=2Ec >>> @@ -604,6 +604,42 @@ static void via_isa_request_i8259_irq(void *opaqu= e, int irq, int level) >>> qemu_set_irq(s->cpu_intr, level); >>> } >>>=20 >>> +static int via_isa_get_pci_irq(const ViaISAState *s, int irq_num) >>> +{ >>> + switch (irq_num) { >>> + case 0: >>> + return s->dev=2Econfig[0x55] >> 4; >>> + case 1: >>> + return s->dev=2Econfig[0x56] & 0xf; >>> + case 2: >>> + return s->dev=2Econfig[0x56] >> 4; >>> + case 3: >>> + return s->dev=2Econfig[0x57] >> 4; >>> + } >>> + return 0; >>> +} >>> + >>> +static void via_isa_set_pci_irq(void *opaque, int irq_num, int level) >>> +{ >>> + ViaISAState *s =3D opaque; >>> + PCIBus *bus =3D pci_get_bus(&s->dev); >>> + int i, pic_level, pic_irq =3D via_isa_get_pci_irq(s, irq_num); >>> + >>> + if (unlikely(pic_irq =3D=3D 0 || pic_irq =3D=3D 2 || pic_irq > 14= )) { >>=20 >> Where does the "pic_irq > 14" come from? It's not mentioned in the data= sheet=2E > >Check at 0x3c register of USB and AC97 functions=2E For the others it may= be valid but unlikely to be used hence we just disallow it=2E (In my versi= on which also mapped IDE here I've checkrf for each source but there's no w= ay to do that in this version=2E) I'm not sure what you mean=2E The 0x3c regs aren't related to the PCI IRQ = routing regs=2E Moreover, as I wrote in my other mail, I wonder what the datasheet tries t= o tell us here at all=2E The information there partly contradicts itself=2E Can you please clarify? Thanks, Bernhard > >Regards, >BALATON Zoltan > >>> + return; >>> + } >>> + >>> + /* The pic level is the logical OR of all the PCI irqs mapped to = it=2E */ >>> + pic_level =3D 0; >>> + for (i =3D 0; i < PCI_NUM_PINS; i++) { >>> + if (pic_irq =3D=3D via_isa_get_pci_irq(s, i)) { >>> + pic_level |=3D pci_bus_get_irq_level(bus, i); >>> + } >>> + } >>> + /* Now we change the pic irq level according to the via irq mappi= ngs=2E */ >>> + qemu_set_irq(s->isa_irqs_in[pic_irq], pic_level); >>> +} >>> + >>> static void via_isa_realize(PCIDevice *d, Error **errp) >>> { >>> ViaISAState *s =3D VIA_ISA(d); >>> @@ -615,9 +651,9 @@ static void via_isa_realize(PCIDevice *d, Error **= errp) >>>=20 >>> qdev_init_gpio_out(dev, &s->cpu_intr, 1); >>> isa_irq =3D qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); >>> + qdev_init_gpio_in_named(dev, via_isa_set_pci_irq, "pirq", PCI_NUM= _PINS); >>> isa_bus =3D isa_bus_new(dev, pci_address_space(d), pci_address_spa= ce_io(d), >>> errp); >>> - >>> if (!isa_bus) { >>> return; >>> } >>=20 >>