qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Nabih Estefan <nabihestefan@google.com>
To: "Cédric Le Goater" <clg@kaod.org>
Cc: Jamin Lin <jamin_lin@aspeedtech.com>,
	Peter Maydell <peter.maydell@linaro.org>,
	 Steven Lee <steven_lee@aspeedtech.com>,
	Troy Lee <leetroy@gmail.com>,
	 Andrew Jeffery <andrew@codeconstruct.com.au>,
	Joel Stanley <joel@jms.id.au>,
	 "open list:All patches CC here" <qemu-devel@nongnu.org>,
	"open list:ASPEED BMCs" <qemu-arm@nongnu.org>,
	troy_lee@aspeedtech.com
Subject: Re: [PATCH v6 00/29] Support AST2700 A1
Date: Fri, 7 Mar 2025 09:47:26 -0800	[thread overview]
Message-ID: <CA+QoejWqZvhr6XWNxGGEJD8JEbeeRWf61dPDPY3ofzf_2z3cHg@mail.gmail.com> (raw)
In-Reply-To: <3485cd84-2aab-45e7-a72c-ca1d85e007ec@kaod.org>

It already got applied, so idk how worthwhile it is, but for
what it's worth: I was just able to test this whole patchset with our
custom A1 machine + custom A1 image!

I'll keep an eye out on future AST27x0 patches that we can help test
so I can test them earlier in the revision process.

Thank you for the development Jamin, and thank you for helping review this
Cèdric!

- Nabih

On Thu, Mar 6, 2025 at 11:35 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> On 3/7/25 04:59, Jamin Lin wrote:
> > v1:
> >   1. Refactor INTC model to support both INTC0 and INTC1.
> >   2. Support AST2700 A1.
> >   3. Create ast2700a0-evb machine.
> >
> > v2:
> >    To streamline the review process, split the following patch series into
> >    three parts.
> >    https://patchwork.kernel.org/project/qemu-devel/cover/20250121070424.2465942-1-jamin_lin@aspeedtech.com/
> >    This patch series focuses on cleaning up the INTC model to
> >    facilitate future support for the INTC_IO model.
> >
> > v3:
> >   1. Update and add functional test for AST2700
> >   2. Add AST2700 INTC design guidance and its block diagram.
> >   3. Retaining the INTC naming and introducing a new INTCIO model to support the AST2700 A1.
> >   4. Create ast2700a1-evb machine and rename ast2700a0-evb machine
> >   5. Fix silicon revision issue and support AST2700 A1.
> >
> > v4:
> >   1. rework functional test for AST2700
> >   2. the initial machine "ast2700-evb" is aliased to "ast2700a0-evb.
> >   3. intc: Reduce regs array size by adding a register sub-region
> >   4. intc: split patch for Support setting different register sizes
> >   5. update ast2700a1-evb machine parent to TYPE_ASPEED_MACHINE
> >
> > v5:
> >   1. Rename status_addr and addr to status_reg and reg for clarity
> >   2. Introduce dynamic allocation for regs array
> >   3. Sort the memmap table by mapping address
> >   4. ast27x0.c split patch for Support two levels of INTC controllers for AST2700 A1
> >   5. tests/functional/aspped split patch for Introduce start_ast2700_test API
> >   6. keep variable naming for reviewer suggestion.
> >   7. Add reviewer suggestion and split patch to make more readable.
> >
> > v6:
> >    1. rename reg_size to nr_regs
> >    2. Fix clean regs size
> >    3. replace g_malloc with g_new
> >
> > With the patch applied, QEMU now supports two machines for running AST2700 SoCs:
> > ast2700a0-evb: Designed for AST2700 A0
> > ast2700a1-evb: Designed for AST2700 A1
> >
> > Test information
> > 1. QEMU version: https://github.com/qemu/qemu/commit/50d38b8921837827ea397d4b20c8bc5efe186e53
> > 2. ASPEED SDK v09.05 pre-built image
> >     https://github.com/AspeedTech-BMC/openbmc/releases/tag/v09.05
> >     ast2700-default-obmc.tar.gz (AST2700 A1)
> >     https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-default-obmc.tar.gz
> >     ast2700-a0-default-obmc.tar.gz (AST2700 A0)
> >     https://github.com/AspeedTech-BMC/openbmc/releases/download/v09.05/ast2700-a0-default-obmc.tar.gz
> >
> > This patch series depends on the following patch series:
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250304064710.2128993-1-jamin_lin@aspeedtech.com/
> > https://patchwork.kernel.org/project/qemu-devel/cover/20250225075622.305515-1-jamin_lin@aspeedtech.com/
> >
> > Jamin Lin (29):
> >    hw/intc/aspeed: Support setting different memory size
> >    hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for
> >      clarity
> >    hw/intc/aspeed: Introduce dynamic allocation for regs array
> >    hw/intc/aspeed: Support setting different register size
> >    hw/intc/aspeed: Reduce regs array size by adding a register sub-region
> >    hw/intc/aspeed: Introduce helper functions for enable and status
> >      registers
> >    hw/intc/aspeed: Add object type name to trace events for better
> >      debugging
> >    hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
> >    hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number
> >    hw/intc/aspeed: Support different memory region ops
> >    hw/intc/aspeed: Rename num_ints to num_inpins for clarity
> >    hw/intc/aspeed: Add support for multiple output pins in INTC
> >    hw/intc/aspeed: Refactor INTC to support separate input and output pin
> >      indices
> >    hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq
> >      index and register address
> >    hw/intc/aspeed: Introduce IRQ handler function to reduce code
> >      duplication
> >    hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
> >    hw/intc/aspeed: Add Support for AST2700 INTCIO Controller
> >    hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon
> >      Revisions
> >    hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping
> >    hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two
> >      Instances
> >    hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for
> >      AST2700 A1
> >    hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1
> >    hw/arm/aspeed: Add Machine Support for AST2700 A1
> >    hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address
> >    tests/functional/aspeed: Introduce start_ast2700_test API
> >    tests/functional/aspeed: Update temperature hwmon path
> >    tests/functional/aspeed: Update test ASPEED SDK v09.05
> >    tests/functional/aspeed: Add test case for AST2700 A1
> >    docs/specs: Add aspeed-intc
> >
> >   docs/specs/aspeed-intc.rst              | 136 +++++
> >   docs/specs/index.rst                    |   1 +
> >   include/hw/arm/aspeed_soc.h             |   3 +-
> >   include/hw/intc/aspeed_intc.h           |  36 +-
> >   include/hw/misc/aspeed_scu.h            |   2 +
> >   hw/arm/aspeed.c                         |  33 +-
> >   hw/arm/aspeed_ast27x0.c                 | 329 ++++++++----
> >   hw/intc/aspeed_intc.c                   | 667 ++++++++++++++++++------
> >   hw/misc/aspeed_scu.c                    |   2 +
> >   hw/intc/trace-events                    |  25 +-
> >   tests/functional/test_aarch64_aspeed.py |  47 +-
> >   11 files changed, 978 insertions(+), 303 deletions(-)
> >   create mode 100644 docs/specs/aspeed-intc.rst
> >
>
> Applied to aspeed-next.
>
> Thanks,
>
> C.
>
>
>


      parent reply	other threads:[~2025-03-07 17:48 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-07  3:59 [PATCH v6 00/29] Support AST2700 A1 Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 01/29] hw/intc/aspeed: Support setting different memory size Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 02/29] hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 03/29] hw/intc/aspeed: Introduce dynamic allocation for regs array Jamin Lin via
2025-03-07  7:23   ` Cédric Le Goater
2025-03-07  3:59 ` [PATCH v6 04/29] hw/intc/aspeed: Support setting different register size Jamin Lin via
2025-03-07  7:23   ` Cédric Le Goater
2025-03-07  3:59 ` [PATCH v6 05/29] hw/intc/aspeed: Reduce regs array size by adding a register sub-region Jamin Lin via
2025-03-07  7:22   ` Cédric Le Goater
2025-03-07  3:59 ` [PATCH v6 06/29] hw/intc/aspeed: Introduce helper functions for enable and status registers Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 07/29] hw/intc/aspeed: Add object type name to trace events for better debugging Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 08/29] hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 09/29] hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 10/29] hw/intc/aspeed: Support different memory region ops Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 11/29] hw/intc/aspeed: Rename num_ints to num_inpins for clarity Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 12/29] hw/intc/aspeed: Add support for multiple output pins in INTC Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 13/29] hw/intc/aspeed: Refactor INTC to support separate input and output pin indices Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 14/29] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 15/29] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 16/29] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 17/29] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 18/29] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 19/29] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 20/29] hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 21/29] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 22/29] hw/arm/aspeed_ast27x0: Add SoC Support " Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 23/29] hw/arm/aspeed: Add Machine " Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 24/29] hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 25/29] tests/functional/aspeed: Introduce start_ast2700_test API Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 26/29] tests/functional/aspeed: Update temperature hwmon path Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 27/29] tests/functional/aspeed: Update test ASPEED SDK v09.05 Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 28/29] tests/functional/aspeed: Add test case for AST2700 A1 Jamin Lin via
2025-03-07  3:59 ` [PATCH v6 29/29] docs/specs: Add aspeed-intc Jamin Lin via
2025-03-07  7:33 ` [PATCH v6 00/29] Support AST2700 A1 Cédric Le Goater
2025-03-07  7:36   ` Jamin Lin
2025-03-07  7:44     ` Cédric Le Goater
2025-03-07  7:56       ` Steven Lee
2025-03-07  8:08         ` Cédric Le Goater
2025-03-07 17:47   ` Nabih Estefan [this message]

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CA+QoejWqZvhr6XWNxGGEJD8JEbeeRWf61dPDPY3ofzf_2z3cHg@mail.gmail.com \
    --to=nabihestefan@google.com \
    --cc=andrew@codeconstruct.com.au \
    --cc=clg@kaod.org \
    --cc=jamin_lin@aspeedtech.com \
    --cc=joel@jms.id.au \
    --cc=leetroy@gmail.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-arm@nongnu.org \
    --cc=qemu-devel@nongnu.org \
    --cc=steven_lee@aspeedtech.com \
    --cc=troy_lee@aspeedtech.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).