[Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

Anthony, I know you wanted to review some of the patches,
since you didn't respond either all's well or you
could not find the time.
I think we are better off merging them for 1.7 and then - worst case,
if major issues surface - disabling the functionality at the last minute
than delaying the merge even more.

The following changes since commit e26d3e734650640fabd7d95ace4f3a6f88725e0b:

  smbios: Factor out smbios_maybe_add_str() (2013-09-28 23:49:39 +0300)

are available in the git repository at:

  git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony

for you to fetch changes up to 6cab1e7000021fa6a487f67e1dba986f68fee30d:

  acpi-build: enable hotplug for PCI bridges (2013-10-14 17:48:58 +0300)

----------------------------------------------------------------
pci, pc, acpi fixes, enhancements

This includes some pretty big changes:
- pci master abort support by Marcel
- pci IRQ API rework by Marcel
- acpi generation and pci bridge hotplug support by myself

Everything has gone through several revisions, latest versions have been on
list for a while without any more comments, tested by several
people.

Please pull for 1.7.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

----------------------------------------------------------------
Igor Mammedov (1):
      cleanup object.h: include error.h directly

Marcel Apfelbaum (11):
      memory: Change MemoryRegion priorities from unsigned to signed
      docs/memory: Explictly state that MemoryRegion priority is signed
      hw/pci: partially handle pci master abort
      hw/core: Add interface to allocate and free a single IRQ
      hw/pci: add pci wrappers for allocating and asserting irqs
      hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init
      hw/vmxnet3: set interrupts using pci irq wrappers
      hw/vfio: set interrupts using pci irq wrappers
      hw: set interrupts using pci irq wrappers
      hw/pcie: AER and hot-plug events must use device's interrupt
      hw/pci: removed irq field from PCIDevice

Michael S. Tsirkin (31):
      qom: cleanup struct Error references
      qom: add pointer to int property helpers
      pci: fix up w64 size calculation helper
      fw_cfg: interface to trigger callback on read
      loader: support for unmapped ROM blobs
      pcie_host: expose UNMAPPED macro
      pcie_host: expose address format
      q35: use macro for MCFG property name
      q35: expose mmcfg size as a property
      i386: add ACPI table files from seabios
      acpi: add rules to compile ASL source
      acpi: pre-compiled ASL files
      acpi: ssdt pcihp: updat generated file
      loader: use file path size from fw_cfg.h
      i386: add bios linker/loader
      loader: allow adding ROMs in done callbacks
      i386: define pc guest info
      acpi/piix: add macros for acpi property names
      piix: APIs for pc guest info
      ich9: APIs for pc guest info
      pvpanic: add API to access io port
      hpet: add API to find it
      acpi: add interface to access user-installed tables
      pc: use new api to add builtin tables
      i386: ACPI table generation code from seabios
      ssdt: fix PBLK length
      ssdt-proc: update generated file
      pci: add pci_for_each_bus_depth_first
      pcihp: generalization of piix4 acpi
      piix4: add acpi pci hotplug support
      acpi-build: enable hotplug for PCI bridges

 configure                           |    9 +-
 hw/i386/acpi-build.h                |    9 +
 hw/i386/acpi-defs.h                 |  331 ++
 hw/i386/bios-linker-loader.h        |   27 +
 hw/lm32/lm32_hwsetup.h              |    2 +-
 include/exec/memory.h               |    4 +-
 include/hw/acpi/acpi.h              |    4 +
 include/hw/acpi/ich9.h              |    2 +
 include/hw/acpi/pcihp.h             |   72 +
 include/hw/acpi/piix4.h             |    8 +
 include/hw/i386/ich9.h              |    2 +
 include/hw/i386/pc.h                |   27 +
 include/hw/irq.h                    |    7 +
 include/hw/loader.h                 |    8 +-
 include/hw/nvram/fw_cfg.h           |    8 +-
 include/hw/pci-host/q35.h           |    2 +
 include/hw/pci/pci.h                |   40 +-
 include/hw/pci/pci_bus.h            |    1 +
 include/hw/pci/pcie.h               |   18 -
 include/hw/pci/pcie_host.h          |   27 +
 include/hw/sysbus.h                 |    2 +-
 include/hw/timer/hpet.h             |    2 +
 include/qom/object.h                |   73 +-
 hw/acpi/core.c                      |   40 +
 hw/acpi/ich9.c                      |   24 +
 hw/acpi/pcihp.c                     |  312 ++
 hw/acpi/piix4.c                     |  125 +-
 hw/audio/ac97.c                     |    4 +-
 hw/audio/es1370.c                   |    4 +-
 hw/audio/intel-hda.c                |    2 +-
 hw/block/nvme.c                     |    2 +-
 hw/char/serial-pci.c                |    5 +-
 hw/char/tpci200.c                   |    8 +-
 hw/core/irq.c                       |   16 +
 hw/core/loader.c                    |   31 +-
 hw/core/sysbus.c                    |    4 +-
 hw/display/qxl.c                    |    2 +-
 hw/i386/acpi-build.c                | 1420 +++++++
 hw/i386/bios-linker-loader.c        |  158 +
 hw/i386/pc.c                        |   25 +-
 hw/i386/pc_piix.c                   |    5 +
 hw/i386/pc_q35.c                    |    3 +
 hw/ide/cmd646.c                     |    2 +-
 hw/ide/ich.c                        |    3 +-
 hw/isa/lpc_ich9.c                   |   40 +
 hw/isa/vt82c686.c                   |    2 +-
 hw/misc/ivshmem.c                   |    2 +-
 hw/misc/pvpanic.c                   |   13 +-
 hw/misc/vfio.c                      |   11 +-
 hw/net/e1000.c                      |    2 +-
 hw/net/eepro100.c                   |    4 +-
 hw/net/ne2000.c                     |    3 +-
 hw/net/pcnet-pci.c                  |    3 +-
 hw/net/rtl8139.c                    |    2 +-
 hw/net/vmxnet3.c                    |   13 +-
 hw/nvram/fw_cfg.c                   |   33 +-
 hw/pci-bridge/pci_bridge_dev.c      |    2 +-
 hw/pci-host/piix.c                  |    8 +
 hw/pci-host/q35.c                   |   26 +-
 hw/pci/pci.c                        |  100 +-
 hw/pci/pcie.c                       |    4 +-
 hw/pci/pcie_aer.c                   |    4 +-
 hw/pci/pcie_host.c                  |   24 -
 hw/pci/shpc.c                       |    2 +-
 hw/scsi/esp-pci.c                   |    3 +-
 hw/scsi/lsi53c895a.c                |    2 +-
 hw/scsi/megasas.c                   |    6 +-
 hw/scsi/vmw_pvscsi.c                |    2 +-
 hw/timer/hpet.c                     |    5 +
 hw/usb/hcd-ehci-pci.c               |    2 +-
 hw/usb/hcd-ohci.c                   |    2 +-
 hw/usb/hcd-uhci.c                   |    6 +-
 hw/usb/hcd-xhci.c                   |    7 +-
 hw/virtio/virtio-pci.c              |    4 +-
 memory.c                            |    4 +-
 qom/object.c                        |   60 +
 vl.c                                |    3 +
 docs/memory.txt                     |    4 +
 hw/acpi/Makefile.objs               |    2 +-
 hw/i386/Makefile.objs               |   27 +
 hw/i386/acpi-dsdt-cpu-hotplug.dsl   |   93 +
 hw/i386/acpi-dsdt-dbug.dsl          |   41 +
 hw/i386/acpi-dsdt-hpet.dsl          |   51 +
 hw/i386/acpi-dsdt-isa.dsl           |  117 +
 hw/i386/acpi-dsdt-pci-crs.dsl       |  105 +
 hw/i386/acpi-dsdt.dsl               |  341 ++
 hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
 hw/i386/q35-acpi-dsdt.dsl           |  452 +++
 hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
 hw/i386/ssdt-misc.dsl               |  119 +
 hw/i386/ssdt-misc.hex.generated     |  386 ++
 hw/i386/ssdt-pcihp.dsl              |   50 +
 hw/i386/ssdt-pcihp.hex.generated    |  108 +
 hw/i386/ssdt-proc.dsl               |   63 +
 hw/i386/ssdt-proc.hex.generated     |  134 +
 scripts/acpi_extract.py             |  362 ++
 scripts/acpi_extract_preprocess.py  |   51 +
 scripts/update-acpi.sh              |    4 +
 98 files changed, 17366 insertions(+), 183 deletions(-)
 create mode 100644 hw/i386/acpi-build.h
 create mode 100644 hw/i386/acpi-defs.h
 create mode 100644 hw/i386/bios-linker-loader.h
 create mode 100644 include/hw/acpi/pcihp.h
 create mode 100644 include/hw/acpi/piix4.h
 create mode 100644 hw/acpi/pcihp.c
 create mode 100644 hw/i386/acpi-build.c
 create mode 100644 hw/i386/bios-linker-loader.c
 create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
 create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
 create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
 create mode 100644 hw/i386/acpi-dsdt-isa.dsl
 create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
 create mode 100644 hw/i386/acpi-dsdt.dsl
 create mode 100644 hw/i386/acpi-dsdt.hex.generated
 create mode 100644 hw/i386/q35-acpi-dsdt.dsl
 create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
 create mode 100644 hw/i386/ssdt-misc.dsl
 create mode 100644 hw/i386/ssdt-misc.hex.generated
 create mode 100644 hw/i386/ssdt-pcihp.dsl
 create mode 100644 hw/i386/ssdt-pcihp.hex.generated
 create mode 100644 hw/i386/ssdt-proc.dsl
 create mode 100644 hw/i386/ssdt-proc.hex.generated
 create mode 100755 scripts/acpi_extract.py
 create mode 100755 scripts/acpi_extract_preprocess.py
 create mode 100644 scripts/update-acpi.sh

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Paolo Bonzini]

Il 14/10/2013 16:57, Michael S. Tsirkin ha scritto:
> pci, pc, acpi fixes, enhancements
> 
> This includes some pretty big changes:
> - pci master abort support by Marcel
> - pci IRQ API rework by Marcel
> - acpi generation and pci bridge hotplug support by myself
> 
> Everything has gone through several revisions, latest versions have been on
> list for a while without any more comments, tested by several
> people.
> 
> Please pull for 1.7.
> 
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

Are you going to do another pull request with the virtio and bus-reset
fixes?

Paolo

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Mon, Oct 14, 2013 at 04:57:19PM +0200, Paolo Bonzini wrote:
> Il 14/10/2013 16:57, Michael S. Tsirkin ha scritto:
> > pci, pc, acpi fixes, enhancements
> > 
> > This includes some pretty big changes:
> > - pci master abort support by Marcel
> > - pci IRQ API rework by Marcel
> > - acpi generation and pci bridge hotplug support by myself
> > 
> > Everything has gone through several revisions, latest versions have been on
> > list for a while without any more comments, tested by several
> > people.
> > 
> > Please pull for 1.7.
> > 
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> 
> Are you going to do another pull request with the virtio and bus-reset
> fixes?
> 
> Paolo

I missed that you did the testing of the post-order changed.
I'll put them on my branch but I'd rather this kind of
change went through a bit more testing so - next pull.

For virtio I thought you said Andreas wants to merge it?

-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Paolo Bonzini]

Il 14/10/2013 17:12, Michael S. Tsirkin ha scritto:
> > Are you going to do another pull request with the virtio and bus-reset
> > fixes?
> 
> I missed that you did the testing of the post-order changed.
> I'll put them on my branch but I'd rather this kind of
> change went through a bit more testing so - next pull.

Ok.  As long as they're on your radar, I don't mind if you want to delay
them to 1.8.

> For virtio I thought you said Andreas wants to merge it?

No, there are conflicts with one of his series, but he is fine with mine
going in first and he'd rather not handle it himself.  With your (and
perhaps Andreas and Alex's) Acked-by I can send the pull request myself.

Paolo

[Qemu-devel] [PULL 01/43] memory: Change MemoryRegion priorities from unsigned to signed

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

When memory regions overlap, priority can be used to specify
which of them takes priority. By making the priority values signed
rather than unsigned, we make it more convenient to implement
a situation where one "background" region should appear only
where no other region exists: rather than having to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/exec/memory.h | 4 ++--
 include/hw/sysbus.h   | 2 +-
 hw/core/sysbus.c      | 4 ++--
 memory.c              | 4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/include/exec/memory.h b/include/exec/memory.h
index ebe0d24..480dfbf 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -153,7 +153,7 @@ struct MemoryRegion {
     bool flush_coalesced_mmio;
     MemoryRegion *alias;
     hwaddr alias_offset;
-    unsigned priority;
+    int priority;
     bool may_overlap;
     QTAILQ_HEAD(subregions, MemoryRegion) subregions;
     QTAILQ_ENTRY(MemoryRegion) subregions_link;
@@ -779,7 +779,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
 void memory_region_add_subregion_overlap(MemoryRegion *mr,
                                          hwaddr offset,
                                          MemoryRegion *subregion,
-                                         unsigned priority);
+                                         int priority);
 
 /**
  * memory_region_get_ram_addr: Get the ram address associated with a memory
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
index bb50a87..f5aaa05 100644
--- a/include/hw/sysbus.h
+++ b/include/hw/sysbus.h
@@ -68,7 +68,7 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
 void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
 void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
 void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
-                             unsigned priority);
+                             int priority);
 void sysbus_add_io(SysBusDevice *dev, hwaddr addr,
                    MemoryRegion *mem);
 void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index b84cd4a..146f50a 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -49,7 +49,7 @@ void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq)
 }
 
 static void sysbus_mmio_map_common(SysBusDevice *dev, int n, hwaddr addr,
-                                   bool may_overlap, unsigned priority)
+                                   bool may_overlap, int priority)
 {
     assert(n >= 0 && n < dev->num_mmio);
 
@@ -81,7 +81,7 @@ void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
 }
 
 void sysbus_mmio_map_overlap(SysBusDevice *dev, int n, hwaddr addr,
-                             unsigned priority)
+                             int priority)
 {
     sysbus_mmio_map_common(dev, n, addr, true, priority);
 }
diff --git a/memory.c b/memory.c
index 5a10fd0..f49d31a 100644
--- a/memory.c
+++ b/memory.c
@@ -1473,7 +1473,7 @@ void memory_region_add_subregion(MemoryRegion *mr,
 void memory_region_add_subregion_overlap(MemoryRegion *mr,
                                          hwaddr offset,
                                          MemoryRegion *subregion,
-                                         unsigned priority)
+                                         int priority)
 {
     subregion->may_overlap = true;
     subregion->priority = priority;
@@ -1506,7 +1506,7 @@ void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
 void memory_region_set_address(MemoryRegion *mr, hwaddr addr)
 {
     MemoryRegion *parent = mr->parent;
-    unsigned priority = mr->priority;
+    int priority = mr->priority;
     bool may_overlap = mr->may_overlap;
 
     if (addr == mr->addr || !parent) {
-- 
MST

[Qemu-devel] [PULL 02/43] docs/memory: Explictly state that MemoryRegion priority is signed

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

When memory regions overlap, priority can be used to specify
which of them takes priority. By making the priority values signed
rather than unsigned, we make it more convenient to implement
a situation where one "background" region should appear only
where no other region exists: rather than having to explicitly
specify a high priority for all the other regions, we can let them take
the default (zero) priority and specify a negative priority for the
background region.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 docs/memory.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/docs/memory.txt b/docs/memory.txt
index feb9fe9..174c0d7 100644
--- a/docs/memory.txt
+++ b/docs/memory.txt
@@ -80,6 +80,10 @@ guest.  This is done with memory_region_add_subregion_overlap(), which
 allows the region to overlap any other region in the same container, and
 specifies a priority that allows the core to decide which of two regions at
 the same address are visible (highest wins).
+Priority values are signed, and the default value is zero. This means that
+you can use memory_region_add_subregion_overlap() both to specify a region
+that must sit 'above' any others (with a positive priority) and also a
+background region that sits 'below' others (with a negative priority).
 
 Visibility
 ----------
-- 
MST

[Qemu-devel] [PULL 03/43] hw/pci: partially handle pci master abort

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

A MemoryRegion with negative priority was created and
it spans over all the pci address space.
It "intercepts" the accesses to unassigned pci
address space and will follow the pci spec:
 1. returns -1 on read
 2. does nothing on write

Note: setting the RECEIVED MASTER ABORT bit in the STATUS register
      of the device that initiated the transaction will be
      implemented in another series

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pci_bus.h |  1 +
 hw/pci/pci.c             | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h
index 9df1788..2ad5edb 100644
--- a/include/hw/pci/pci_bus.h
+++ b/include/hw/pci/pci_bus.h
@@ -23,6 +23,7 @@ struct PCIBus {
     PCIDevice *parent_dev;
     MemoryRegion *address_space_mem;
     MemoryRegion *address_space_io;
+    MemoryRegion master_abort_mem;
 
     QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
     QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 00554a0..25626b8 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -283,6 +283,24 @@ const char *pci_root_bus_path(PCIDevice *dev)
     return rootbus->qbus.name;
 }
 
+static uint64_t master_abort_mem_read(void *opaque, hwaddr addr, unsigned size)
+{
+   return -1ULL;
+}
+
+static void master_abort_mem_write(void *opaque, hwaddr addr, uint64_t val,
+                                   unsigned size)
+{
+}
+
+static const MemoryRegionOps master_abort_mem_ops = {
+    .read = master_abort_mem_read,
+    .write = master_abort_mem_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+#define MASTER_ABORT_MEM_PRIORITY INT_MIN
+
 static void pci_bus_init(PCIBus *bus, DeviceState *parent,
                          const char *name,
                          MemoryRegion *address_space_mem,
@@ -294,6 +312,14 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent,
     bus->address_space_mem = address_space_mem;
     bus->address_space_io = address_space_io;
 
+
+    memory_region_init_io(&bus->master_abort_mem, OBJECT(bus),
+                          &master_abort_mem_ops, bus, "pci-master-abort",
+                          memory_region_size(bus->address_space_mem));
+    memory_region_add_subregion_overlap(bus->address_space_mem,
+                                        0, &bus->master_abort_mem,
+                                        MASTER_ABORT_MEM_PRIORITY);
+
     /* host bridge */
     QLIST_INIT(&bus->child);
 
-- 
MST

[Qemu-devel] [PULL 04/43] hw/core: Add interface to allocate and free a single IRQ

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

qemu_allocate_irq returns a single qemu_irq.
The interface allows to specify an interrupt number.

qemu_free_irq frees it.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/irq.h |  7 +++++++
 hw/core/irq.c    | 16 ++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/include/hw/irq.h b/include/hw/irq.h
index 610e6b7..d08bc02 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -30,6 +30,12 @@ static inline void qemu_irq_pulse(qemu_irq irq)
  */
 qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n);
 
+/*
+ * Allocates a single IRQ. The irq is assigned with a handler, an opaque
+ * data and the interrupt number.
+ */
+qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n);
+
 /* Extends an Array of IRQs. Old IRQs have their handlers and opaque data
  * preserved. New IRQs are assigned the argument handler and opaque data.
  */
@@ -37,6 +43,7 @@ qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
                                 void *opaque, int n);
 
 void qemu_free_irqs(qemu_irq *s);
+void qemu_free_irq(qemu_irq irq);
 
 /* Returns a new IRQ with opposite polarity.  */
 qemu_irq qemu_irq_invert(qemu_irq irq);
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 2078542..03c8cb3 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -68,6 +68,17 @@ qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n)
     return qemu_extend_irqs(NULL, 0, handler, opaque, n);
 }
 
+qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n)
+{
+    struct IRQState *irq;
+
+    irq = g_new(struct IRQState, 1);
+    irq->handler = handler;
+    irq->opaque = opaque;
+    irq->n = n;
+
+    return irq;
+}
 
 void qemu_free_irqs(qemu_irq *s)
 {
@@ -75,6 +86,11 @@ void qemu_free_irqs(qemu_irq *s)
     g_free(s);
 }
 
+void qemu_free_irq(qemu_irq irq)
+{
+    g_free(irq);
+}
+
 static void qemu_notirq(void *opaque, int line, int level)
 {
     struct IRQState *irq = opaque;
-- 
MST

[Qemu-devel] [PULL 05/43] hw/pci: add pci wrappers for allocating and asserting irqs

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

Interrupt pin is selected and saved into PCI_INTERRUPT_PIN
register during device initialization. Devices should not call
directly qemu_set_irq and specify the INTx pin on each call.

Added pci_* wrappers to replace qemu_set_irq, qemu_irq_raise,
qemu_irq_lower and qemu_irq_pulse, setting the irq
based on PCI_INTERRUPT_PIN.

Added pci_allocate_irq wrapper to be used by devices that
still need PCIDevice infrastructure to assert irqs.

Renamed a static method which was named already pci_set_irq.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pci.h | 23 +++++++++++++++++++++++
 hw/pci/pci.c         | 26 ++++++++++++++++++++++----
 2 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 4b90e5d..990342c 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -632,6 +632,29 @@ PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 
+qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
+void pci_set_irq(PCIDevice *pci_dev, int level);
+
+static inline void pci_irq_assert(PCIDevice *pci_dev)
+{
+    pci_set_irq(pci_dev, 1);
+}
+
+static inline void pci_irq_deassert(PCIDevice *pci_dev)
+{
+    pci_set_irq(pci_dev, 0);
+}
+
+/*
+ * FIXME: PCI does not work this way.
+ * All the callers to this method should be fixed.
+ */
+static inline void pci_irq_pulse(PCIDevice *pci_dev)
+{
+    pci_irq_assert(pci_dev);
+    pci_irq_deassert(pci_dev);
+}
+
 static inline int pci_is_express(const PCIDevice *d)
 {
     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 25626b8..ff4b697 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -83,7 +83,7 @@ static const TypeInfo pcie_bus_info = {
 
 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
 static void pci_update_mappings(PCIDevice *d);
-static void pci_set_irq(void *opaque, int irq_num, int level);
+static void pci_irq_handler(void *opaque, int irq_num, int level);
 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
 static void pci_del_option_rom(PCIDevice *pdev);
 
@@ -161,7 +161,7 @@ void pci_device_deassert_intx(PCIDevice *dev)
 {
     int i;
     for (i = 0; i < PCI_NUM_PINS; ++i) {
-        qemu_set_irq(dev->irq[i], 0);
+        pci_irq_handler(dev, i, 0);
     }
 }
 
@@ -889,7 +889,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
     pci_dev->config_read = config_read;
     pci_dev->config_write = config_write;
     bus->devices[devfn] = pci_dev;
-    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
+    pci_dev->irq = qemu_allocate_irqs(pci_irq_handler, pci_dev, PCI_NUM_PINS);
     pci_dev->version_id = 2; /* Current pci device vmstate version */
     return pci_dev;
 }
@@ -1201,7 +1201,7 @@ void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
 /* generic PCI irq support */
 
 /* 0 <= irq_num <= 3. level must be 0 or 1 */
-static void pci_set_irq(void *opaque, int irq_num, int level)
+static void pci_irq_handler(void *opaque, int irq_num, int level)
 {
     PCIDevice *pci_dev = opaque;
     int change;
@@ -1217,6 +1217,24 @@ static void pci_set_irq(void *opaque, int irq_num, int level)
     pci_change_irq_level(pci_dev, irq_num, change);
 }
 
+static inline int pci_intx(PCIDevice *pci_dev)
+{
+    return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1;
+}
+
+qemu_irq pci_allocate_irq(PCIDevice *pci_dev)
+{
+    int intx = pci_intx(pci_dev);
+
+    return qemu_allocate_irq(pci_irq_handler, pci_dev, intx);
+}
+
+void pci_set_irq(PCIDevice *pci_dev, int level)
+{
+    int intx = pci_intx(pci_dev);
+    pci_irq_handler(pci_dev, intx, level);
+}
+
 /* Special hooks used by device assignment */
 void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq)
 {
-- 
MST

[Qemu-devel] [PULL 06/43] hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

The PCI_INTERRUPT_PIN will be used by shpc init, so
was moved before the call to shpc_init.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/pci-bridge/pci_bridge_dev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c
index a9392c7..440e187 100644
--- a/hw/pci-bridge/pci_bridge_dev.c
+++ b/hw/pci-bridge/pci_bridge_dev.c
@@ -53,6 +53,7 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
     if (err) {
         goto bridge_error;
     }
+    dev->config[PCI_INTERRUPT_PIN] = 0x1;
     memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev));
     err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
     if (err) {
@@ -73,7 +74,6 @@ static int pci_bridge_dev_initfn(PCIDevice *dev)
      * Check whether that works well. */
     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
 		     PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
-    dev->config[PCI_INTERRUPT_PIN] = 0x1;
     return 0;
 msi_error:
     slotid_cap_cleanup(dev);
-- 
MST

[Qemu-devel] [PULL 07/43] hw/vmxnet3: set interrupts using pci irq wrappers

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

pci_set_irq uses PCI_INTERRUPT_PIN config register
to compute device INTx pin to assert/deassert.

An assert is used to ensure that intx received
from the quest OS corresponds to PCI_INTERRUPT_PIN.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/net/vmxnet3.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c
index 49c2466..19687aa 100644
--- a/hw/net/vmxnet3.c
+++ b/hw/net/vmxnet3.c
@@ -336,7 +336,7 @@ static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx)
     }
 
     VMW_IRPRN("Asserting line for interrupt %u", int_idx);
-    qemu_set_irq(d->irq[int_idx], 1);
+    pci_irq_assert(d);
     return true;
 }
 
@@ -356,7 +356,7 @@ static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx)
     assert(!s->msi_used || !msi_enabled(d));
 
     VMW_IRPRN("Deasserting line for interrupt %u", lidx);
-    qemu_set_irq(d->irq[lidx], 0);
+    pci_irq_deassert(d);
 }
 
 static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx)
@@ -1299,6 +1299,12 @@ static void vmxnet3_update_features(VMXNET3State *s)
     }
 }
 
+static bool vmxnet3_verify_intx(VMXNET3State *s, int intx)
+{
+    return s->msix_used || s->msi_used || (intx ==
+           (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1));
+}
+
 static void vmxnet3_activate_device(VMXNET3State *s)
 {
     int i;
@@ -1332,6 +1338,7 @@ static void vmxnet3_activate_device(VMXNET3State *s)
 
     s->event_int_idx =
         VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx);
+    assert(vmxnet3_verify_intx(s, s->event_int_idx));
     VMW_CFPRN("Events interrupt line is %u", s->event_int_idx);
 
     s->auto_int_masking =
@@ -1364,6 +1371,7 @@ static void vmxnet3_activate_device(VMXNET3State *s)
         /* Read interrupt number for this TX queue */
         s->txq_descr[i].intr_idx =
             VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx);
+        assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx));
 
         VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx);
 
@@ -1411,6 +1419,7 @@ static void vmxnet3_activate_device(VMXNET3State *s)
         /* Read interrupt number for this RX queue */
         s->rxq_descr[i].intr_idx =
             VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx);
+        assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx));
 
         VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx);
 
-- 
MST

[Qemu-devel] [PULL 08/43] hw/vfio: set interrupts using pci irq wrappers

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.

save INTX pin into the config register before calling
pci_set_irq

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/misc/vfio.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
index a1c08fb..9d02e49 100644
--- a/hw/misc/vfio.c
+++ b/hw/misc/vfio.c
@@ -297,7 +297,7 @@ static void vfio_intx_interrupt(void *opaque)
             'A' + vdev->intx.pin);
 
     vdev->intx.pending = true;
-    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 1);
+    pci_irq_assert(&vdev->pdev);
     vfio_mmap_set_enabled(vdev, false);
     if (vdev->intx.mmap_timeout) {
         timer_mod(vdev->intx.mmap_timer,
@@ -315,7 +315,7 @@ static void vfio_eoi(VFIODevice *vdev)
             vdev->host.bus, vdev->host.slot, vdev->host.function);
 
     vdev->intx.pending = false;
-    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
+    pci_irq_deassert(&vdev->pdev);
     vfio_unmask_intx(vdev);
 }
 
@@ -341,7 +341,7 @@ static void vfio_enable_intx_kvm(VFIODevice *vdev)
     qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev);
     vfio_mask_intx(vdev);
     vdev->intx.pending = false;
-    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
+    pci_irq_deassert(&vdev->pdev);
 
     /* Get an eventfd for resample/unmask */
     if (event_notifier_init(&vdev->intx.unmask, 0)) {
@@ -417,7 +417,7 @@ static void vfio_disable_intx_kvm(VFIODevice *vdev)
      */
     vfio_mask_intx(vdev);
     vdev->intx.pending = false;
-    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
+    pci_irq_deassert(&vdev->pdev);
 
     /* Tell KVM to stop listening for an INTx irqfd */
     if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
@@ -488,6 +488,7 @@ static int vfio_enable_intx(VFIODevice *vdev)
     vfio_disable_interrupts(vdev);
 
     vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */
+    pci_config_set_interrupt_pin(vdev->pdev.config, pin);
 
 #ifdef CONFIG_KVM
     /*
@@ -547,7 +548,7 @@ static void vfio_disable_intx(VFIODevice *vdev)
     vfio_disable_intx_kvm(vdev);
     vfio_disable_irqindex(vdev, VFIO_PCI_INTX_IRQ_INDEX);
     vdev->intx.pending = false;
-    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
+    pci_irq_deassert(&vdev->pdev);
     vfio_mmap_set_enabled(vdev, true);
 
     fd = event_notifier_get_fd(&vdev->intx.interrupt);
-- 
MST

Re: [Qemu-devel] [PULL 08/43] hw/vfio: set interrupts using pci irq wrappers

[Alex Williamson]

On Mon, 2013-10-14 at 17:58 +0300, Michael S. Tsirkin wrote:
> From: Marcel Apfelbaum <marcel.a@redhat.com>
> 
> pci_set_irq and the other pci irq wrappers use
> PCI_INTERRUPT_PIN config register to compute device
> INTx pin to assert/deassert.
> 
> save INTX pin into the config register before calling
> pci_set_irq
> 
> Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

I realize this is a pull request, but for the record

Acked-by: Alex Williamson <alex.williamson@redhat.com>

> ---
>  hw/misc/vfio.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/hw/misc/vfio.c b/hw/misc/vfio.c
> index a1c08fb..9d02e49 100644
> --- a/hw/misc/vfio.c
> +++ b/hw/misc/vfio.c
> @@ -297,7 +297,7 @@ static void vfio_intx_interrupt(void *opaque)
>              'A' + vdev->intx.pin);
>  
>      vdev->intx.pending = true;
> -    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 1);
> +    pci_irq_assert(&vdev->pdev);
>      vfio_mmap_set_enabled(vdev, false);
>      if (vdev->intx.mmap_timeout) {
>          timer_mod(vdev->intx.mmap_timer,
> @@ -315,7 +315,7 @@ static void vfio_eoi(VFIODevice *vdev)
>              vdev->host.bus, vdev->host.slot, vdev->host.function);
>  
>      vdev->intx.pending = false;
> -    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
> +    pci_irq_deassert(&vdev->pdev);
>      vfio_unmask_intx(vdev);
>  }
>  
> @@ -341,7 +341,7 @@ static void vfio_enable_intx_kvm(VFIODevice *vdev)
>      qemu_set_fd_handler(irqfd.fd, NULL, NULL, vdev);
>      vfio_mask_intx(vdev);
>      vdev->intx.pending = false;
> -    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
> +    pci_irq_deassert(&vdev->pdev);
>  
>      /* Get an eventfd for resample/unmask */
>      if (event_notifier_init(&vdev->intx.unmask, 0)) {
> @@ -417,7 +417,7 @@ static void vfio_disable_intx_kvm(VFIODevice *vdev)
>       */
>      vfio_mask_intx(vdev);
>      vdev->intx.pending = false;
> -    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
> +    pci_irq_deassert(&vdev->pdev);
>  
>      /* Tell KVM to stop listening for an INTx irqfd */
>      if (kvm_vm_ioctl(kvm_state, KVM_IRQFD, &irqfd)) {
> @@ -488,6 +488,7 @@ static int vfio_enable_intx(VFIODevice *vdev)
>      vfio_disable_interrupts(vdev);
>  
>      vdev->intx.pin = pin - 1; /* Pin A (1) -> irq[0] */
> +    pci_config_set_interrupt_pin(vdev->pdev.config, pin);
>  
>  #ifdef CONFIG_KVM
>      /*
> @@ -547,7 +548,7 @@ static void vfio_disable_intx(VFIODevice *vdev)
>      vfio_disable_intx_kvm(vdev);
>      vfio_disable_irqindex(vdev, VFIO_PCI_INTX_IRQ_INDEX);
>      vdev->intx.pending = false;
> -    qemu_set_irq(vdev->pdev.irq[vdev->intx.pin], 0);
> +    pci_irq_deassert(&vdev->pdev);
>      vfio_mmap_set_enabled(vdev, true);
>  
>      fd = event_notifier_get_fd(&vdev->intx.interrupt);

[Qemu-devel] [PULL 09/43] hw: set interrupts using pci irq wrappers

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

pci_set_irq and the other pci irq wrappers use
PCI_INTERRUPT_PIN config register to compute device
INTx pin to assert/deassert.

An irq is allocated using pci_allocate_irq wrapper
only if is needed by non pci devices.

Removed irq related fields from state if not used anymore.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/audio/ac97.c        | 4 ++--
 hw/audio/es1370.c      | 4 ++--
 hw/audio/intel-hda.c   | 2 +-
 hw/block/nvme.c        | 2 +-
 hw/char/serial-pci.c   | 5 +++--
 hw/char/tpci200.c      | 8 ++++----
 hw/display/qxl.c       | 2 +-
 hw/ide/cmd646.c        | 2 +-
 hw/ide/ich.c           | 3 ++-
 hw/isa/vt82c686.c      | 2 +-
 hw/misc/ivshmem.c      | 2 +-
 hw/net/e1000.c         | 2 +-
 hw/net/eepro100.c      | 4 ++--
 hw/net/ne2000.c        | 3 ++-
 hw/net/pcnet-pci.c     | 3 ++-
 hw/net/rtl8139.c       | 2 +-
 hw/pci/shpc.c          | 2 +-
 hw/scsi/esp-pci.c      | 3 ++-
 hw/scsi/lsi53c895a.c   | 2 +-
 hw/scsi/megasas.c      | 6 +++---
 hw/scsi/vmw_pvscsi.c   | 2 +-
 hw/usb/hcd-ehci-pci.c  | 2 +-
 hw/usb/hcd-ohci.c      | 2 +-
 hw/usb/hcd-uhci.c      | 6 ++----
 hw/usb/hcd-xhci.c      | 7 ++-----
 hw/virtio/virtio-pci.c | 4 ++--
 26 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c
index 01b4dfb..03f4846 100644
--- a/hw/audio/ac97.c
+++ b/hw/audio/ac97.c
@@ -280,12 +280,12 @@ static void update_sr (AC97LinkState *s, AC97BusMasterRegs *r, uint32_t new_sr)
     if (level) {
         s->glob_sta |= masks[r - s->bm_regs];
         dolog ("set irq level=1\n");
-        qemu_set_irq (s->dev.irq[0], 1);
+        pci_irq_assert(&s->dev);
     }
     else {
         s->glob_sta &= ~masks[r - s->bm_regs];
         dolog ("set irq level=0\n");
-        qemu_set_irq (s->dev.irq[0], 0);
+        pci_irq_deassert(&s->dev);
     }
 }
 
diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c
index adb66ce..1ec7ace 100644
--- a/hw/audio/es1370.c
+++ b/hw/audio/es1370.c
@@ -323,7 +323,7 @@ static void es1370_update_status (ES1370State *s, uint32_t new_status)
     else {
         s->status = new_status & ~STAT_INTR;
     }
-    qemu_set_irq (s->dev.irq[0], !!level);
+    pci_set_irq(&s->dev, !!level);
 }
 
 static void es1370_reset (ES1370State *s)
@@ -349,7 +349,7 @@ static void es1370_reset (ES1370State *s)
             s->dac_voice[i] = NULL;
         }
     }
-    qemu_irq_lower (s->dev.irq[0]);
+    pci_irq_deassert(&s->dev);
 }
 
 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index a6666c6..4327264 100644
--- a/hw/audio/intel-hda.c
+++ b/hw/audio/intel-hda.c
@@ -269,7 +269,7 @@ static void intel_hda_update_irq(IntelHDAState *d)
             msi_notify(&d->pci, 0);
         }
     } else {
-        qemu_set_irq(d->pci.irq[0], level);
+        pci_set_irq(&d->pci, level);
     }
 }
 
diff --git a/hw/block/nvme.c b/hw/block/nvme.c
index 5dee229..2882ffe 100644
--- a/hw/block/nvme.c
+++ b/hw/block/nvme.c
@@ -69,7 +69,7 @@ static void nvme_isr_notify(NvmeCtrl *n, NvmeCQueue *cq)
         if (msix_enabled(&(n->parent_obj))) {
             msix_notify(&(n->parent_obj), cq->vector);
         } else {
-            qemu_irq_pulse(n->parent_obj.irq[0]);
+            pci_irq_pulse(&n->parent_obj);
         }
     }
 }
diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c
index aec6705..991c99f 100644
--- a/hw/char/serial-pci.c
+++ b/hw/char/serial-pci.c
@@ -61,7 +61,7 @@ static int serial_pci_init(PCIDevice *dev)
     }
 
     pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
-    s->irq = pci->dev.irq[0];
+    s->irq = pci_allocate_irq(&pci->dev);
 
     memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
     pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
@@ -79,7 +79,7 @@ static void multi_serial_irq_mux(void *opaque, int n, int level)
             pending = 1;
         }
     }
-    qemu_set_irq(pci->dev.irq[0], pending);
+    pci_set_irq(&pci->dev, pending);
 }
 
 static int multi_serial_pci_init(PCIDevice *dev)
@@ -132,6 +132,7 @@ static void serial_pci_exit(PCIDevice *dev)
 
     serial_exit_core(s);
     memory_region_destroy(&s->io);
+    qemu_free_irq(s->irq);
 }
 
 static void multi_serial_pci_exit(PCIDevice *dev)
diff --git a/hw/char/tpci200.c b/hw/char/tpci200.c
index e04ff26..a49d2ed 100644
--- a/hw/char/tpci200.c
+++ b/hw/char/tpci200.c
@@ -134,8 +134,8 @@ static void tpci200_set_irq(void *opaque, int intno, int level)
     /* Check if the interrupt is edge sensitive */
     if (dev->ctrl[ip_n] & CTRL_INT_EDGE(intno)) {
         if (level) {
-            qemu_set_irq(dev->dev.irq[0], !dev->int_set);
-            qemu_set_irq(dev->dev.irq[0],  dev->int_set);
+            pci_set_irq(&dev->dev, !dev->int_set);
+            pci_set_irq(&dev->dev,  dev->int_set);
         }
     } else {
         unsigned i, j;
@@ -153,10 +153,10 @@ static void tpci200_set_irq(void *opaque, int intno, int level)
         }
 
         if (level_status && !dev->int_set) {
-            qemu_irq_raise(dev->dev.irq[0]);
+            pci_irq_assert(&dev->dev);
             dev->int_set = 1;
         } else if (!level_status && dev->int_set) {
-            qemu_irq_lower(dev->dev.irq[0]);
+            pci_irq_deassert(&dev->dev);
             dev->int_set = 0;
         }
     }
diff --git a/hw/display/qxl.c b/hw/display/qxl.c
index c50e285..0e2231c 100644
--- a/hw/display/qxl.c
+++ b/hw/display/qxl.c
@@ -1103,7 +1103,7 @@ static void qxl_update_irq(PCIQXLDevice *d)
     uint32_t pending = le32_to_cpu(d->ram->int_pending);
     uint32_t mask    = le32_to_cpu(d->ram->int_mask);
     int level = !!(pending & mask);
-    qemu_set_irq(d->pci.irq[0], level);
+    pci_set_irq(&d->pci, level);
     qxl_ring_set_dirty(d);
 }
 
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index 0500a7a..a8e35fe 100644
--- a/hw/ide/cmd646.c
+++ b/hw/ide/cmd646.c
@@ -230,7 +230,7 @@ static void cmd646_update_irq(PCIIDEState *d)
                  !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) ||
         ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) &&
          !(pd->config[MRDMODE] & MRDMODE_BLK_CH1));
-    qemu_set_irq(pd->irq[0], pci_level);
+    pci_set_irq(pd, pci_level);
 }
 
 /* the PCI irq level is the logical OR of the two channels */
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index bff952b..1c7c058 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -116,7 +116,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)
     dev->config[0x90]   = 1 << 6; /* Address Map Register - AHCI mode */
 
     msi_init(dev, 0x50, 1, true, false);
-    d->ahci.irq = dev->irq[0];
+    d->ahci.irq = pci_allocate_irq(dev);
 
     pci_register_bar(dev, ICH9_IDP_BAR, PCI_BASE_ADDRESS_SPACE_IO,
                      &d->ahci.idp);
@@ -145,6 +145,7 @@ static void pci_ich9_uninit(PCIDevice *dev)
 
     msi_uninit(dev);
     ahci_uninit(&d->ahci);
+    qemu_free_irq(d->ahci.irq);
 }
 
 static void ich_ahci_class_init(ObjectClass *klass, void *data)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index 8fe4fcb..5fb8086 100644
--- a/hw/isa/vt82c686.c
+++ b/hw/isa/vt82c686.c
@@ -185,7 +185,7 @@ static void pm_update_sci(VT686PMState *s)
                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
                    ACPI_BITMASK_TIMER_ENABLE)) != 0);
-    qemu_set_irq(s->dev.irq[0], sci_level);
+    pci_set_irq(&s->dev, sci_level);
     /* schedule a timer interruption if needed */
     acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c
index 2838866..8d144ba 100644
--- a/hw/misc/ivshmem.c
+++ b/hw/misc/ivshmem.c
@@ -133,7 +133,7 @@ static void ivshmem_update_irq(IVShmemState *s, int val)
            isr ? 1 : 0, s->intrstatus, s->intrmask);
     }
 
-    qemu_set_irq(d->irq[0], (isr != 0));
+    pci_set_irq(d, (isr != 0));
 }
 
 static void ivshmem_IntrMask_write(IVShmemState *s, uint32_t val)
diff --git a/hw/net/e1000.c b/hw/net/e1000.c
index d3f274c..a37a3df 100644
--- a/hw/net/e1000.c
+++ b/hw/net/e1000.c
@@ -325,7 +325,7 @@ set_interrupt_cause(E1000State *s, int index, uint32_t val)
     }
 
     s->mit_irq_level = (pending_ints != 0);
-    qemu_set_irq(d->irq[0], s->mit_irq_level);
+    pci_set_irq(d, s->mit_irq_level);
 }
 
 static void
diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c
index ffa60d5..3b891ca 100644
--- a/hw/net/eepro100.c
+++ b/hw/net/eepro100.c
@@ -409,7 +409,7 @@ static void disable_interrupt(EEPRO100State * s)
 {
     if (s->int_stat) {
         TRACE(INT, logout("interrupt disabled\n"));
-        qemu_irq_lower(s->dev.irq[0]);
+        pci_irq_deassert(&s->dev);
         s->int_stat = 0;
     }
 }
@@ -418,7 +418,7 @@ static void enable_interrupt(EEPRO100State * s)
 {
     if (!s->int_stat) {
         TRACE(INT, logout("interrupt enabled\n"));
-        qemu_irq_raise(s->dev.irq[0]);
+        pci_irq_assert(&s->dev);
         s->int_stat = 1;
     }
 }
diff --git a/hw/net/ne2000.c b/hw/net/ne2000.c
index c961258..a94cf74 100644
--- a/hw/net/ne2000.c
+++ b/hw/net/ne2000.c
@@ -731,7 +731,7 @@ static int pci_ne2000_init(PCIDevice *pci_dev)
     s = &d->ne2000;
     ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
-    s->irq = d->dev.irq[0];
+    s->irq = pci_allocate_irq(&d->dev);
 
     qemu_macaddr_default_if_unset(&s->c.macaddr);
     ne2000_reset(s);
@@ -752,6 +752,7 @@ static void pci_ne2000_exit(PCIDevice *pci_dev)
 
     memory_region_destroy(&s->io);
     qemu_del_nic(s->nic);
+    qemu_free_irq(s->irq);
 }
 
 static Property ne2000_properties[] = {
diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
index a893165..311594d 100644
--- a/hw/net/pcnet-pci.c
+++ b/hw/net/pcnet-pci.c
@@ -282,6 +282,7 @@ static void pci_pcnet_uninit(PCIDevice *dev)
 {
     PCIPCNetState *d = PCI_PCNET(dev);
 
+    qemu_free_irq(d->state.irq);
     memory_region_destroy(&d->state.mmio);
     memory_region_destroy(&d->io_bar);
     timer_del(d->state.poll_timer);
@@ -331,7 +332,7 @@ static int pci_pcnet_init(PCIDevice *pci_dev)
 
     pci_register_bar(pci_dev, 1, 0, &s->mmio);
 
-    s->irq = pci_dev->irq[0];
+    s->irq = pci_allocate_irq(pci_dev);
     s->phys_mem_read = pci_physical_memory_read;
     s->phys_mem_write = pci_physical_memory_write;
     s->dma_opaque = pci_dev;
diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c
index c31199f..7d72b21 100644
--- a/hw/net/rtl8139.c
+++ b/hw/net/rtl8139.c
@@ -716,7 +716,7 @@ static void rtl8139_update_irq(RTL8139State *s)
     DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
         s->IntrMask);
 
-    qemu_set_irq(d->irq[0], (isr != 0));
+    pci_set_irq(d, (isr != 0));
 }
 
 static int rtl8139_RxWrap(RTL8139State *s)
diff --git a/hw/pci/shpc.c b/hw/pci/shpc.c
index eb092fd..0bbd36e 100644
--- a/hw/pci/shpc.c
+++ b/hw/pci/shpc.c
@@ -172,7 +172,7 @@ static void shpc_interrupt_update(PCIDevice *d)
     if (msi_enabled(d) && shpc->msi_requested != level)
         msi_notify(d, 0);
     else
-        qemu_set_irq(d->irq[0], level);
+        pci_set_irq(d, level);
     shpc->msi_requested = level;
 }
 
diff --git a/hw/scsi/esp-pci.c b/hw/scsi/esp-pci.c
index 99bf8ec..48c8b82 100644
--- a/hw/scsi/esp-pci.c
+++ b/hw/scsi/esp-pci.c
@@ -361,7 +361,7 @@ static int esp_pci_scsi_init(PCIDevice *dev)
                           "esp-io", 0x80);
 
     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->io);
-    s->irq = dev->irq[0];
+    s->irq = pci_allocate_irq(dev);
 
     scsi_bus_new(&s->bus, sizeof(s->bus), d, &esp_pci_scsi_info, NULL);
     if (!d->hotplugged) {
@@ -378,6 +378,7 @@ static void esp_pci_scsi_uninit(PCIDevice *d)
 {
     PCIESPState *pci = PCI_ESP(d);
 
+    qemu_free_irq(pci->esp.irq);
     memory_region_destroy(&pci->io);
 }
 
diff --git a/hw/scsi/lsi53c895a.c b/hw/scsi/lsi53c895a.c
index 0c36842..0e51b94 100644
--- a/hw/scsi/lsi53c895a.c
+++ b/hw/scsi/lsi53c895a.c
@@ -433,7 +433,7 @@ static void lsi_update_irq(LSIState *s)
                 level, s->dstat, s->sist1, s->sist0);
         last_level = level;
     }
-    qemu_set_irq(d->irq[0], level);
+    pci_set_irq(d, level);
 
     if (!level && lsi_irq_on_rsl(s) && !(s->scntl1 & LSI_SCNTL1_CON)) {
         DPRINTF("Handled IRQs & disconnected, looking for pending "
diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c
index 09b51b3..7c5a1a2 100644
--- a/hw/scsi/megasas.c
+++ b/hw/scsi/megasas.c
@@ -535,7 +535,7 @@ static void megasas_complete_frame(MegasasState *s, uint64_t context)
                 msix_notify(pci_dev, 0);
             } else {
                 trace_megasas_irq_raise();
-                qemu_irq_raise(pci_dev->irq[0]);
+                pci_irq_assert(pci_dev);
             }
         }
     } else {
@@ -1936,7 +1936,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
         s->intr_mask = val;
         if (!megasas_intr_enabled(s) && !msix_enabled(pci_dev)) {
             trace_megasas_irq_lower();
-            qemu_irq_lower(pci_dev->irq[0]);
+            pci_irq_deassert(pci_dev);
         }
         if (megasas_intr_enabled(s)) {
             trace_megasas_intr_enabled();
@@ -1952,7 +1952,7 @@ static void megasas_mmio_write(void *opaque, hwaddr addr,
             stl_le_phys(s->producer_pa, s->reply_queue_head);
             if (!msix_enabled(pci_dev)) {
                 trace_megasas_irq_lower();
-                qemu_irq_lower(pci_dev->irq[0]);
+                pci_irq_deassert(pci_dev);
             }
         }
         break;
diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c
index 819d671..94b328f 100644
--- a/hw/scsi/vmw_pvscsi.c
+++ b/hw/scsi/vmw_pvscsi.c
@@ -330,7 +330,7 @@ pvscsi_update_irq_status(PVSCSIState *s)
         return;
     }
 
-    qemu_set_irq(d->irq[0], !!should_raise);
+    pci_set_irq(d, !!should_raise);
 }
 
 static void
diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c
index 4d21a0b..0c98594 100644
--- a/hw/usb/hcd-ehci-pci.c
+++ b/hw/usb/hcd-ehci-pci.c
@@ -60,7 +60,7 @@ static int usb_ehci_pci_initfn(PCIDevice *dev)
     pci_conf[0x6e] = 0x00;
     pci_conf[0x6f] = 0xc0;  /* USBLEFCTLSTS */
 
-    s->irq = dev->irq[3];
+    s->irq = pci_allocate_irq(dev);
     s->as = pci_get_address_space(dev);
 
     usb_ehci_realize(s, DEVICE(dev), NULL);
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 35f0878..2b36ee5 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -1944,7 +1944,7 @@ static int usb_ohci_initfn_pci(PCIDevice *dev)
                       pci_get_address_space(dev)) != 0) {
         return -1;
     }
-    ohci->state.irq = dev->irq[0];
+    ohci->state.irq = pci_allocate_irq(dev);
 
     pci_register_bar(dev, 0, 0, &ohci->state.mem);
     return 0;
diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c
index becc7fa..238d1d2 100644
--- a/hw/usb/hcd-uhci.c
+++ b/hw/usb/hcd-uhci.c
@@ -164,7 +164,6 @@ struct UHCIState {
 
     /* Interrupts that should be raised at the end of the current frame.  */
     uint32_t pending_int_mask;
-    int irq_pin;
 
     /* Active packets */
     QTAILQ_HEAD(, UHCIQueue) queues;
@@ -381,7 +380,7 @@ static void uhci_update_irq(UHCIState *s)
     } else {
         level = 0;
     }
-    qemu_set_irq(s->dev.irq[s->irq_pin], level);
+    pci_set_irq(&s->dev, level);
 }
 
 static void uhci_reset(void *opaque)
@@ -1240,8 +1239,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev)
     /* TODO: reset value should be 0. */
     pci_conf[USB_SBRN] = USB_RELEASE_1; // release number
 
-    s->irq_pin = u->info.irq_pin;
-    pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1);
+    pci_config_set_interrupt_pin(pci_conf, u->info.irq_pin + 1);
 
     if (s->masterbus) {
         USBPort *ports[NB_PORTS];
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index f02231d..cffefd7 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -449,7 +449,6 @@ struct XHCIState {
     /*< public >*/
 
     USBBus bus;
-    qemu_irq irq;
     MemoryRegion mem;
     MemoryRegion mem_cap;
     MemoryRegion mem_oper;
@@ -737,7 +736,7 @@ static void xhci_intx_update(XHCIState *xhci)
     }
 
     trace_usb_xhci_irq_intx(level);
-    qemu_set_irq(xhci->irq, level);
+    pci_set_irq(pci_dev, level);
 }
 
 static void xhci_msix_update(XHCIState *xhci, int v)
@@ -795,7 +794,7 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
 
     if (v == 0) {
         trace_usb_xhci_irq_intx(1);
-        qemu_set_irq(xhci->irq, 1);
+        pci_irq_assert(pci_dev);
     }
 }
 
@@ -3416,8 +3415,6 @@ static int usb_xhci_initfn(struct PCIDevice *dev)
 
     xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
 
-    xhci->irq = dev->irq[0];
-
     memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
     memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
                           "capabilities", LEN_CAP);
diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
index 4825802..7647be8 100644
--- a/hw/virtio/virtio-pci.c
+++ b/hw/virtio/virtio-pci.c
@@ -116,7 +116,7 @@ static void virtio_pci_notify(DeviceState *d, uint16_t vector)
     if (msix_enabled(&proxy->pci_dev))
         msix_notify(&proxy->pci_dev, vector);
     else
-        qemu_set_irq(proxy->pci_dev.irq[0], proxy->vdev->isr & 1);
+        pci_set_irq(&proxy->pci_dev, proxy->vdev->isr & 1);
 }
 
 static void virtio_pci_save_config(DeviceState *d, QEMUFile *f)
@@ -362,7 +362,7 @@ static uint32_t virtio_ioport_read(VirtIOPCIProxy *proxy, uint32_t addr)
         /* reading from the ISR also clears it. */
         ret = vdev->isr;
         vdev->isr = 0;
-        qemu_set_irq(proxy->pci_dev.irq[0], 0);
+        pci_irq_deassert(&proxy->pci_dev);
         break;
     case VIRTIO_MSI_CONFIG_VECTOR:
         ret = vdev->config_vector;
-- 
MST

[Qemu-devel] [PULL 10/43] hw/pcie: AER and hot-plug events must use device's interrupt

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

The fields hpev_intx and aer_intx were removed because
both AER and hot-plug events must use device's interrupt.
Assert/deassert interrupts using pci irq wrappers instead.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pcie.h | 18 ------------------
 hw/pci/pcie.c         |  4 ++--
 hw/pci/pcie_aer.c     |  4 ++--
 3 files changed, 4 insertions(+), 22 deletions(-)

diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
index c010007..1966169 100644
--- a/include/hw/pci/pcie.h
+++ b/include/hw/pci/pcie.h
@@ -64,15 +64,6 @@ struct PCIExpressDevice {
     uint8_t exp_cap;
 
     /* SLOT */
-    unsigned int hpev_intx;     /* INTx for hot plug event (0-3:INT[A-D]#)
-                                 * default is 0 = INTA#
-                                 * If the chip wants to use other interrupt
-                                 * line, initialize this member with the
-                                 * desired number.
-                                 * If the chip dynamically changes this member,
-                                 * also initialize it when loaded as
-                                 * appropreately.
-                                 */
     bool hpev_notified; /* Logical AND of conditions for hot plug event.
                          Following 6.7.3.4:
                          Software Notification of Hot-Plug Events, an interrupt
@@ -82,15 +73,6 @@ struct PCIExpressDevice {
     /* AER */
     uint16_t aer_cap;
     PCIEAERLog aer_log;
-    unsigned int aer_intx;      /* INTx for error reporting
-                                 * default is 0 = INTA#
-                                 * If the chip wants to use other interrupt
-                                 * line, initialize this member with the
-                                 * desired number.
-                                 * If the chip dynamically changes this member,
-                                 * also initialize it when loaded as
-                                 * appropreately.
-                                 */
 };
 
 /* PCI express capability helper functions */
diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
index 50af3c1..268a696 100644
--- a/hw/pci/pcie.c
+++ b/hw/pci/pcie.c
@@ -187,7 +187,7 @@ static void hotplug_event_notify(PCIDevice *dev)
     } else if (msi_enabled(dev)) {
         msi_notify(dev, pcie_cap_flags_get_vector(dev));
     } else {
-        qemu_set_irq(dev->irq[dev->exp.hpev_intx], dev->exp.hpev_notified);
+        pci_set_irq(dev, dev->exp.hpev_notified);
     }
 }
 
@@ -195,7 +195,7 @@ static void hotplug_event_clear(PCIDevice *dev)
 {
     hotplug_event_update_event_status(dev);
     if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified) {
-        qemu_set_irq(dev->irq[dev->exp.hpev_intx], 0);
+        pci_irq_deassert(dev);
     }
 }
 
diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c
index ca762ab..32aa0c6 100644
--- a/hw/pci/pcie_aer.c
+++ b/hw/pci/pcie_aer.c
@@ -285,7 +285,7 @@ static void pcie_aer_root_notify(PCIDevice *dev)
     } else if (msi_enabled(dev)) {
         msi_notify(dev, pcie_aer_root_get_vector(dev));
     } else {
-        qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
+        pci_irq_assert(dev);
     }
 }
 
@@ -768,7 +768,7 @@ void pcie_aer_root_write_config(PCIDevice *dev,
     uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
     /* 6.2.4.1.2 Interrupt Generation */
     if (!msix_enabled(dev) && !msi_enabled(dev)) {
-        qemu_set_irq(dev->irq[dev->exp.aer_intx], !!(root_cmd & enabled_cmd));
+        pci_set_irq(dev, !!(root_cmd & enabled_cmd));
         return;
     }
 
-- 
MST

[Qemu-devel] [PULL 11/43] hw/pci: removed irq field from PCIDevice

[Michael S. Tsirkin]

From: Marcel Apfelbaum <marcel.a@redhat.com>

Instead of exposing the the irq field,
pci wrappers to qemu_set_irq or qemu_irq_*
can be used.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pci.h | 3 ---
 hw/pci/pci.c         | 2 --
 2 files changed, 5 deletions(-)

diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 990342c..37ffa53 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -247,9 +247,6 @@ struct PCIDevice {
     PCIConfigReadFunc *config_read;
     PCIConfigWriteFunc *config_write;
 
-    /* IRQ objects for the INTA-INTD pins.  */
-    qemu_irq *irq;
-
     /* Legacy PCI VGA regions */
     MemoryRegion *vga_regions[QEMU_PCI_VGA_NUM_REGIONS];
     bool has_vga;
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ff4b697..ae23c58 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -889,14 +889,12 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
     pci_dev->config_read = config_read;
     pci_dev->config_write = config_write;
     bus->devices[devfn] = pci_dev;
-    pci_dev->irq = qemu_allocate_irqs(pci_irq_handler, pci_dev, PCI_NUM_PINS);
     pci_dev->version_id = 2; /* Current pci device vmstate version */
     return pci_dev;
 }
 
 static void do_pci_unregister_device(PCIDevice *pci_dev)
 {
-    qemu_free_irqs(pci_dev->irq);
     pci_dev->bus->devices[pci_dev->devfn] = NULL;
     pci_config_free(pci_dev);
 
-- 
MST

[Qemu-devel] [PULL 12/43] cleanup object.h: include error.h directly

[Michael S. Tsirkin]

From: Igor Mammedov <imammedo@redhat.com>

qapi/error.h is simple enough to be included in qom/object.h
direcly and prepares qom/object.h to use Error typedef.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/qom/object.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/qom/object.h b/include/qom/object.h
index 1a7b71a..d9a0063 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -18,9 +18,9 @@
 #include <stdint.h>
 #include <stdbool.h>
 #include "qemu/queue.h"
+#include "qapi/error.h"
 
 struct Visitor;
-struct Error;
 
 struct TypeImpl;
 typedef struct TypeImpl *Type;
-- 
MST

[Qemu-devel] [PULL 13/43] qom: cleanup struct Error references

[Michael S. Tsirkin]

now that a typedef for struct Error is available,
use it in qom/object.h to match coding style rules.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/qom/object.h | 50 +++++++++++++++++++++++++-------------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/include/qom/object.h b/include/qom/object.h
index d9a0063..6c1e7d3 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -301,7 +301,7 @@ typedef void (ObjectPropertyAccessor)(Object *obj,
                                       struct Visitor *v,
                                       void *opaque,
                                       const char *name,
-                                      struct Error **errp);
+                                      Error **errp);
 
 /**
  * ObjectPropertyRelease:
@@ -790,9 +790,9 @@ void object_property_add(Object *obj, const char *name, const char *type,
                          ObjectPropertyAccessor *get,
                          ObjectPropertyAccessor *set,
                          ObjectPropertyRelease *release,
-                         void *opaque, struct Error **errp);
+                         void *opaque, Error **errp);
 
-void object_property_del(Object *obj, const char *name, struct Error **errp);
+void object_property_del(Object *obj, const char *name, Error **errp);
 
 /**
  * object_property_find:
@@ -803,7 +803,7 @@ void object_property_del(Object *obj, const char *name, struct Error **errp);
  * Look up a property for an object and return its #ObjectProperty if found.
  */
 ObjectProperty *object_property_find(Object *obj, const char *name,
-                                     struct Error **errp);
+                                     Error **errp);
 
 void object_unparent(Object *obj);
 
@@ -818,7 +818,7 @@ void object_unparent(Object *obj);
  * Reads a property from a object.
  */
 void object_property_get(Object *obj, struct Visitor *v, const char *name,
-                         struct Error **errp);
+                         Error **errp);
 
 /**
  * object_property_set_str:
@@ -829,7 +829,7 @@ void object_property_get(Object *obj, struct Visitor *v, const char *name,
  * Writes a string value to a property.
  */
 void object_property_set_str(Object *obj, const char *value,
-                             const char *name, struct Error **errp);
+                             const char *name, Error **errp);
 
 /**
  * object_property_get_str:
@@ -842,7 +842,7 @@ void object_property_set_str(Object *obj, const char *value,
  * The caller should free the string.
  */
 char *object_property_get_str(Object *obj, const char *name,
-                              struct Error **errp);
+                              Error **errp);
 
 /**
  * object_property_set_link:
@@ -853,7 +853,7 @@ char *object_property_get_str(Object *obj, const char *name,
  * Writes an object's canonical path to a property.
  */
 void object_property_set_link(Object *obj, Object *value,
-                              const char *name, struct Error **errp);
+                              const char *name, Error **errp);
 
 /**
  * object_property_get_link:
@@ -866,7 +866,7 @@ void object_property_set_link(Object *obj, Object *value,
  * string or not a valid object path).
  */
 Object *object_property_get_link(Object *obj, const char *name,
-                                 struct Error **errp);
+                                 Error **errp);
 
 /**
  * object_property_set_bool:
@@ -877,7 +877,7 @@ Object *object_property_get_link(Object *obj, const char *name,
  * Writes a bool value to a property.
  */
 void object_property_set_bool(Object *obj, bool value,
-                              const char *name, struct Error **errp);
+                              const char *name, Error **errp);
 
 /**
  * object_property_get_bool:
@@ -889,7 +889,7 @@ void object_property_set_bool(Object *obj, bool value,
  * an error occurs (including when the property value is not a bool).
  */
 bool object_property_get_bool(Object *obj, const char *name,
-                              struct Error **errp);
+                              Error **errp);
 
 /**
  * object_property_set_int:
@@ -900,7 +900,7 @@ bool object_property_get_bool(Object *obj, const char *name,
  * Writes an integer value to a property.
  */
 void object_property_set_int(Object *obj, int64_t value,
-                             const char *name, struct Error **errp);
+                             const char *name, Error **errp);
 
 /**
  * object_property_get_int:
@@ -912,7 +912,7 @@ void object_property_set_int(Object *obj, int64_t value,
  * an error occurs (including when the property value is not an integer).
  */
 int64_t object_property_get_int(Object *obj, const char *name,
-                                struct Error **errp);
+                                Error **errp);
 
 /**
  * object_property_set:
@@ -926,7 +926,7 @@ int64_t object_property_get_int(Object *obj, const char *name,
  * Writes a property to a object.
  */
 void object_property_set(Object *obj, struct Visitor *v, const char *name,
-                         struct Error **errp);
+                         Error **errp);
 
 /**
  * object_property_parse:
@@ -938,7 +938,7 @@ void object_property_set(Object *obj, struct Visitor *v, const char *name,
  * Parses a string and writes the result into a property of an object.
  */
 void object_property_parse(Object *obj, const char *string,
-                           const char *name, struct Error **errp);
+                           const char *name, Error **errp);
 
 /**
  * object_property_print:
@@ -950,7 +950,7 @@ void object_property_parse(Object *obj, const char *string,
  * caller shall free the string.
  */
 char *object_property_print(Object *obj, const char *name,
-                            struct Error **errp);
+                            Error **errp);
 
 /**
  * object_property_get_type:
@@ -961,7 +961,7 @@ char *object_property_print(Object *obj, const char *name,
  * Returns:  The type name of the property.
  */
 const char *object_property_get_type(Object *obj, const char *name,
-                                     struct Error **errp);
+                                     Error **errp);
 
 /**
  * object_get_root:
@@ -1054,7 +1054,7 @@ Object *object_resolve_path_component(Object *parent, const gchar *part);
  * The child object itself can be retrieved using object_property_get_link().
  */
 void object_property_add_child(Object *obj, const char *name,
-                               Object *child, struct Error **errp);
+                               Object *child, Error **errp);
 
 /**
  * object_property_add_link:
@@ -1077,7 +1077,7 @@ void object_property_add_child(Object *obj, const char *name,
  */
 void object_property_add_link(Object *obj, const char *name,
                               const char *type, Object **child,
-                              struct Error **errp);
+                              Error **errp);
 
 /**
  * object_property_add_str:
@@ -1092,9 +1092,9 @@ void object_property_add_link(Object *obj, const char *name,
  * property of type 'string'.
  */
 void object_property_add_str(Object *obj, const char *name,
-                             char *(*get)(Object *, struct Error **),
-                             void (*set)(Object *, const char *, struct Error **),
-                             struct Error **errp);
+                             char *(*get)(Object *, Error **),
+                             void (*set)(Object *, const char *, Error **),
+                             Error **errp);
 
 /**
  * object_property_add_bool:
@@ -1108,9 +1108,9 @@ void object_property_add_str(Object *obj, const char *name,
  * property of type 'bool'.
  */
 void object_property_add_bool(Object *obj, const char *name,
-                              bool (*get)(Object *, struct Error **),
-                              void (*set)(Object *, bool, struct Error **),
-                              struct Error **errp);
+                              bool (*get)(Object *, Error **),
+                              void (*set)(Object *, bool, Error **),
+                              Error **errp);
 
 /**
  * object_child_foreach:
-- 
MST

[Qemu-devel] [PULL 14/43] qom: add pointer to int property helpers

[Michael S. Tsirkin]

Make it easy to add read-only helpers for simple
integer properties in memory.

Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/qom/object.h | 21 ++++++++++++++++++
 qom/object.c         | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 81 insertions(+)

diff --git a/include/qom/object.h b/include/qom/object.h
index 6c1e7d3..d02172a 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -795,6 +795,27 @@ void object_property_add(Object *obj, const char *name, const char *type,
 void object_property_del(Object *obj, const char *name, Error **errp);
 
 /**
+ * object_property_add_uint8_ptr:
+ * object_property_add_uint16_ptr:
+ * object_property_add_uint32_ptr:
+ * object_property_add_uint64_ptr:
+ * @obj: the object to add a property to
+ * @name: the name of the property
+ * @v: pointer to value
+ *
+ * Add an integer property in memory.  This function will add a
+ * property of the appropriate type.
+ */
+void object_property_add_uint8_ptr(Object *obj, const char *name,
+                                   const uint8_t *v, Error **errp);
+void object_property_add_uint16_ptr(Object *obj, const char *name,
+                                    const uint16_t *v, Error **errp);
+void object_property_add_uint32_ptr(Object *obj, const char *name,
+                                    const uint32_t *v, Error **errp);
+void object_property_add_uint64_ptr(Object *obj, const char *name,
+                                    const uint64_t *v, Error **Errp);
+
+/**
  * object_property_find:
  * @obj: the object
  * @name: the name of the property
diff --git a/qom/object.c b/qom/object.c
index e90e382..b617f26 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -1344,6 +1344,66 @@ static char *qdev_get_type(Object *obj, Error **errp)
     return g_strdup(object_get_typename(obj));
 }
 
+static void property_get_uint8_ptr(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    uint8_t value = *(uint8_t *)opaque;
+    visit_type_uint8(v, &value, name, errp);
+}
+
+static void property_get_uint16_ptr(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    uint16_t value = *(uint16_t *)opaque;
+    visit_type_uint16(v, &value, name, errp);
+}
+
+static void property_get_uint32_ptr(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    uint32_t value = *(uint32_t *)opaque;
+    visit_type_uint32(v, &value, name, errp);
+}
+
+static void property_get_uint64_ptr(Object *obj, Visitor *v,
+                                   void *opaque, const char *name,
+                                   Error **errp)
+{
+    uint64_t value = *(uint64_t *)opaque;
+    visit_type_uint64(v, &value, name, errp);
+}
+
+void object_property_add_uint8_ptr(Object *obj, const char *name,
+                                   const uint8_t *v, Error **errp)
+{
+    object_property_add(obj, name, "uint8", property_get_uint8_ptr,
+                        NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint16_ptr(Object *obj, const char *name,
+                                    const uint16_t *v, Error **errp)
+{
+    object_property_add(obj, name, "uint16", property_get_uint16_ptr,
+                        NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint32_ptr(Object *obj, const char *name,
+                                    const uint32_t *v, Error **errp)
+{
+    object_property_add(obj, name, "uint32", property_get_uint32_ptr,
+                        NULL, NULL, (void *)v, errp);
+}
+
+void object_property_add_uint64_ptr(Object *obj, const char *name,
+                                    const uint64_t *v, Error **errp)
+{
+    object_property_add(obj, name, "uint64", property_get_uint64_ptr,
+                        NULL, NULL, (void *)v, errp);
+}
+
 static void object_instance_init(Object *obj)
 {
     object_property_add_str(obj, "type", qdev_get_type, NULL, NULL);
-- 
MST

[Qemu-devel] [PULL 15/43] pci: fix up w64 size calculation helper

[Michael S. Tsirkin]

BAR base was calculated incorrectly.
Use existing pci_bar_address to get it right.

Tested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/pci/pci.c | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index ae23c58..a98c8a0 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -2306,7 +2306,7 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
     Range *range = opaque;
     PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
     uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND);
-    int r;
+    int i;
 
     if (!(cmd & PCI_COMMAND_MEMORY)) {
         return;
@@ -2325,17 +2325,21 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque)
             range_extend(range, &pref_range);
         }
     }
-    for (r = 0; r < PCI_NUM_REGIONS; ++r) {
-        PCIIORegion *region = &dev->io_regions[r];
+    for (i = 0; i < PCI_NUM_REGIONS; ++i) {
+        PCIIORegion *r = &dev->io_regions[i];
         Range region_range;
 
-        if (!region->size ||
-            (region->type & PCI_BASE_ADDRESS_SPACE_IO) ||
-            !(region->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+        if (!r->size ||
+            (r->type & PCI_BASE_ADDRESS_SPACE_IO) ||
+            !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) {
+            continue;
+        }
+        region_range.begin = pci_bar_address(dev, i, r->type, r->size);
+        region_range.end = region_range.begin + r->size;
+
+        if (region_range.begin == PCI_BAR_UNMAPPED) {
             continue;
         }
-        region_range.begin = pci_get_quad(dev->config + pci_bar(dev, r));
-        region_range.end = region_range.begin + region->size;
 
         region_range.begin = MAX(region_range.begin, 0x1ULL << 32);
 
-- 
MST

[Qemu-devel] [PULL 16/43] fw_cfg: interface to trigger callback on read

[Michael S. Tsirkin]

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/nvram/fw_cfg.h |  4 ++++
 hw/nvram/fw_cfg.c         | 33 ++++++++++++++++++++++++++++-----
 2 files changed, 32 insertions(+), 5 deletions(-)

diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index f60dd67..2ab0fc2 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -60,6 +60,7 @@ typedef struct FWCfgFiles {
 } FWCfgFiles;
 
 typedef void (*FWCfgCallback)(void *opaque, uint8_t *data);
+typedef void (*FWCfgReadCallback)(void *opaque, uint32_t offset);
 
 void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len);
 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value);
@@ -70,6 +71,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
                          void *callback_opaque, void *data, size_t len);
 void fw_cfg_add_file(FWCfgState *s, const char *filename, void *data,
                      size_t len);
+void fw_cfg_add_file_callback(FWCfgState *s, const char *filename,
+                              FWCfgReadCallback callback, void *callback_opaque,
+                              void *data, size_t len);
 FWCfgState *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
                         hwaddr crl_addr, hwaddr data_addr);
 
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index d0820e5..f5dc3ea 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -42,6 +42,7 @@ typedef struct FWCfgEntry {
     uint8_t *data;
     void *callback_opaque;
     FWCfgCallback callback;
+    FWCfgReadCallback read_callback;
 } FWCfgEntry;
 
 struct FWCfgState {
@@ -249,8 +250,12 @@ static uint8_t fw_cfg_read(FWCfgState *s)
 
     if (s->cur_entry == FW_CFG_INVALID || !e->data || s->cur_offset >= e->len)
         ret = 0;
-    else
+    else {
+        if (e->read_callback) {
+            e->read_callback(e->callback_opaque, s->cur_offset);
+        }
         ret = e->data[s->cur_offset++];
+    }
 
     trace_fw_cfg_read(s, ret);
     return ret;
@@ -381,7 +386,10 @@ static const VMStateDescription vmstate_fw_cfg = {
     }
 };
 
-void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+static void fw_cfg_add_bytes_read_callback(FWCfgState *s, uint16_t key,
+                                           FWCfgReadCallback callback,
+                                           void *callback_opaque,
+                                           void *data, size_t len)
 {
     int arch = !!(key & FW_CFG_ARCH_LOCAL);
 
@@ -391,6 +399,13 @@ void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
 
     s->entries[arch][key].data = data;
     s->entries[arch][key].len = (uint32_t)len;
+    s->entries[arch][key].read_callback = callback;
+    s->entries[arch][key].callback_opaque = callback_opaque;
+}
+
+void fw_cfg_add_bytes(FWCfgState *s, uint16_t key, void *data, size_t len)
+{
+    fw_cfg_add_bytes_read_callback(s, key, NULL, NULL, data, len);
 }
 
 void fw_cfg_add_string(FWCfgState *s, uint16_t key, const char *value)
@@ -444,8 +459,9 @@ void fw_cfg_add_callback(FWCfgState *s, uint16_t key, FWCfgCallback callback,
     s->entries[arch][key].callback = callback;
 }
 
-void fw_cfg_add_file(FWCfgState *s,  const char *filename,
-                     void *data, size_t len)
+void fw_cfg_add_file_callback(FWCfgState *s,  const char *filename,
+                              FWCfgReadCallback callback, void *callback_opaque,
+                              void *data, size_t len)
 {
     int i, index;
     size_t dsize;
@@ -459,7 +475,8 @@ void fw_cfg_add_file(FWCfgState *s,  const char *filename,
     index = be32_to_cpu(s->files->count);
     assert(index < FW_CFG_FILE_SLOTS);
 
-    fw_cfg_add_bytes(s, FW_CFG_FILE_FIRST + index, data, len);
+    fw_cfg_add_bytes_read_callback(s, FW_CFG_FILE_FIRST + index,
+                                   callback, callback_opaque, data, len);
 
     pstrcpy(s->files->f[index].name, sizeof(s->files->f[index].name),
             filename);
@@ -477,6 +494,12 @@ void fw_cfg_add_file(FWCfgState *s,  const char *filename,
     s->files->count = cpu_to_be32(index+1);
 }
 
+void fw_cfg_add_file(FWCfgState *s,  const char *filename,
+                     void *data, size_t len)
+{
+    fw_cfg_add_file_callback(s, filename, NULL, NULL, data, len);
+}
+
 static void fw_cfg_machine_ready(struct Notifier *n, void *data)
 {
     size_t len;
-- 
MST

[Qemu-devel] [PULL 17/43] loader: support for unmapped ROM blobs

[Michael S. Tsirkin]

Support ROM blobs not mapped into guest memory:
same as ROM files really but use caller's buffer.

Support invoking callback on access and
return memory pointer making it easier
for caller to update memory if necessary.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/lm32/lm32_hwsetup.h |  2 +-
 include/hw/loader.h    |  7 ++++---
 hw/core/loader.c       | 23 ++++++++++++++++++++---
 3 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h
index 3449bd8..9fd5e69 100644
--- a/hw/lm32/lm32_hwsetup.h
+++ b/hw/lm32/lm32_hwsetup.h
@@ -73,7 +73,7 @@ static inline void hwsetup_free(HWSetup *hw)
 static inline void hwsetup_create_rom(HWSetup *hw,
         hwaddr base)
 {
-    rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
+    rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base, NULL, NULL, NULL);
 }
 
 static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 6145736..e0c576b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -40,8 +40,9 @@ extern bool rom_file_in_ram;
 
 int rom_add_file(const char *file, const char *fw_dir,
                  hwaddr addr, int32_t bootindex);
-int rom_add_blob(const char *name, const void *blob, size_t len,
-                 hwaddr addr);
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+                   hwaddr addr, const char *fw_file_name,
+                   FWCfgReadCallback fw_callback, void *callback_opaque);
 int rom_add_elf_program(const char *name, void *data, size_t datasize,
                         size_t romsize, hwaddr addr);
 int rom_load_all(void);
@@ -53,7 +54,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
 #define rom_add_file_fixed(_f, _a, _i)          \
     rom_add_file(_f, NULL, _a, _i)
 #define rom_add_blob_fixed(_f, _b, _l, _a)      \
-    rom_add_blob(_f, _b, _l, _a)
+    (rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) ? 0 : -1)
 
 #define PC_ROM_MIN_VGA     0xc0000
 #define PC_ROM_MIN_OPTION  0xc8000
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 7b3d3ee..449bd4c 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -700,10 +700,12 @@ err:
     return -1;
 }
 
-int rom_add_blob(const char *name, const void *blob, size_t len,
-                 hwaddr addr)
+void *rom_add_blob(const char *name, const void *blob, size_t len,
+                   hwaddr addr, const char *fw_file_name,
+                   FWCfgReadCallback fw_callback, void *callback_opaque)
 {
     Rom *rom;
+    void *data = NULL;
 
     rom           = g_malloc0(sizeof(*rom));
     rom->name     = g_strdup(name);
@@ -713,7 +715,22 @@ int rom_add_blob(const char *name, const void *blob, size_t len,
     rom->data     = g_malloc0(rom->datasize);
     memcpy(rom->data, blob, len);
     rom_insert(rom);
-    return 0;
+    if (fw_file_name && fw_cfg) {
+        char devpath[100];
+
+        snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
+
+        if (rom_file_in_ram) {
+            data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
+        } else {
+            data = rom->data;
+        }
+
+        fw_cfg_add_file_callback(fw_cfg, fw_file_name,
+                                 fw_callback, callback_opaque,
+                                 data, rom->romsize);
+    }
+    return data;
 }
 
 /* This function is specific for elf program because we don't need to allocate
-- 
MST

Re: [Qemu-devel] [PULL 17/43] loader: support for unmapped ROM blobs

[Alexander Graf]

On 14.10.2013, at 16:58, Michael S. Tsirkin <mst@redhat.com> wrote:

> Support ROM blobs not mapped into guest memory:
> same as ROM files really but use caller's buffer.
> 
> Support invoking callback on access and
> return memory pointer making it easier
> for caller to update memory if necessary.
> 
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> Tested-by: Gerd Hoffmann <kraxel@redhat.com>
> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> Tested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

This patch breaks -M bamboo. Let explain inline why.

> ---
> hw/lm32/lm32_hwsetup.h |  2 +-
> include/hw/loader.h    |  7 ++++---
> hw/core/loader.c       | 23 ++++++++++++++++++++---
> 3 files changed, 25 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/lm32/lm32_hwsetup.h b/hw/lm32/lm32_hwsetup.h
> index 3449bd8..9fd5e69 100644
> --- a/hw/lm32/lm32_hwsetup.h
> +++ b/hw/lm32/lm32_hwsetup.h
> @@ -73,7 +73,7 @@ static inline void hwsetup_free(HWSetup *hw)
> static inline void hwsetup_create_rom(HWSetup *hw,
>         hwaddr base)
> {
> -    rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base);
> +    rom_add_blob("hwsetup", hw->data, TARGET_PAGE_SIZE, base, NULL, NULL, NULL);
> }
> 
> static inline void hwsetup_add_u8(HWSetup *hw, uint8_t u)
> diff --git a/include/hw/loader.h b/include/hw/loader.h
> index 6145736..e0c576b 100644
> --- a/include/hw/loader.h
> +++ b/include/hw/loader.h
> @@ -40,8 +40,9 @@ extern bool rom_file_in_ram;
> 
> int rom_add_file(const char *file, const char *fw_dir,
>                  hwaddr addr, int32_t bootindex);
> -int rom_add_blob(const char *name, const void *blob, size_t len,
> -                 hwaddr addr);
> +void *rom_add_blob(const char *name, const void *blob, size_t len,
> +                   hwaddr addr, const char *fw_file_name,
> +                   FWCfgReadCallback fw_callback, void *callback_opaque);
> int rom_add_elf_program(const char *name, void *data, size_t datasize,
>                         size_t romsize, hwaddr addr);
> int rom_load_all(void);
> @@ -53,7 +54,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
> #define rom_add_file_fixed(_f, _a, _i)          \
>     rom_add_file(_f, NULL, _a, _i)
> #define rom_add_blob_fixed(_f, _b, _l, _a)      \
> -    rom_add_blob(_f, _b, _l, _a)
> +    (rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) ? 0 : -1)

^

> 
> #define PC_ROM_MIN_VGA     0xc0000
> #define PC_ROM_MIN_OPTION  0xc8000
> diff --git a/hw/core/loader.c b/hw/core/loader.c
> index 7b3d3ee..449bd4c 100644
> --- a/hw/core/loader.c
> +++ b/hw/core/loader.c
> @@ -700,10 +700,12 @@ err:
>     return -1;
> }
> 
> -int rom_add_blob(const char *name, const void *blob, size_t len,
> -                 hwaddr addr)
> +void *rom_add_blob(const char *name, const void *blob, size_t len,
> +                   hwaddr addr, const char *fw_file_name,
> +                   FWCfgReadCallback fw_callback, void *callback_opaque)
> {
>     Rom *rom;
> +    void *data = NULL;

data = NULL

> 
>     rom           = g_malloc0(sizeof(*rom));
>     rom->name     = g_strdup(name);
> @@ -713,7 +715,22 @@ int rom_add_blob(const char *name, const void *blob, size_t len,
>     rom->data     = g_malloc0(rom->datasize);
>     memcpy(rom->data, blob, len);
>     rom_insert(rom);
> -    return 0;
> +    if (fw_file_name && fw_cfg) {

We never execute this for rom_add_blob_fixed(), so ...

> +        char devpath[100];
> +
> +        snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
> +
> +        if (rom_file_in_ram) {
> +            data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
> +        } else {
> +            data = rom->data;
> +        }
> +
> +        fw_cfg_add_file_callback(fw_cfg, fw_file_name,
> +                                 fw_callback, callback_opaque,
> +                                 data, rom->romsize);
> +    }
> +    return data;

... we always return NULL here.

That means that rom_add_blob_fixed() always returns -1. If rom_add_blob_fixed() returns != 0, we abort loading the device tree as blob during bamboo machine init.


Alex

Re: [Qemu-devel] [PULL 17/43] loader: support for unmapped ROM blobs

[Michael S. Tsirkin]

On Fri, Nov 08, 2013 at 01:54:18AM +0100, Alexander Graf wrote:
> 
> On 14.10.2013, at 16:58, Michael S. Tsirkin <mst@redhat.com> wrote:
> 
> > Support ROM blobs not mapped into guest memory:
> > same as ROM files really but use caller's buffer.
> > 
> > Support invoking callback on access and
> > return memory pointer making it easier
> > for caller to update memory if necessary.
> > 
> > Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> > Tested-by: Gerd Hoffmann <kraxel@redhat.com>
> > Reviewed-by: Laszlo Ersek <lersek@redhat.com>
> > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > Tested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> 
> This patch breaks -M bamboo. Let explain inline why.

Thanks a lot for the report and the explanation.
rom_add_blob never fails, so I think it's
easiest to just avoid checking the return value.
If we do, we can remove the return value from rom_add_blob_fixed, too.

Could you please confirm that the below helps?

-->

loader: drop return value for rom_add_blob_fixed

rom_add_blob never fails, and neither does rom_add_blob_fixed,
so there's no need to return value from it.

In fact, rom_add_blob_fixed was erroneously returning -1 unconditionally
which made the only system that checked the return value -M bamboo fail
to start.

Drop the return value and drop checks from ppc440_bamboo to
fix this failure.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

---

diff --git a/include/hw/loader.h b/include/hw/loader.h
index 58eca98..7a23d6b 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -55,7 +55,7 @@ void do_info_roms(Monitor *mon, const QDict *qdict);
 #define rom_add_file_fixed(_f, _a, _i)          \
     rom_add_file(_f, NULL, _a, _i)
 #define rom_add_blob_fixed(_f, _b, _l, _a)      \
-    (rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL) ? 0 : -1)
+    rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL)
 
 #define PC_ROM_MIN_VGA     0xc0000
 #define PC_ROM_MIN_OPTION  0xc8000
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 655e499..67597df 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -110,8 +110,9 @@ static int bamboo_load_device_tree(hwaddr addr,
     qemu_devtree_setprop_cell(fdt, "/cpus/cpu@0", "timebase-frequency",
                               tb_freq);
 
-    ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
+    rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
     g_free(fdt);
+    return 0;
 
 out:
 

[Qemu-devel] [PULL 18/43] pcie_host: expose UNMAPPED macro

[Michael S. Tsirkin]

Make it possible to test unmapped status through QMP.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pcie_host.h | 3 +++
 hw/pci/pcie_host.c         | 3 ---
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 1228e36..bac3c67 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,9 @@
 #define PCIE_HOST_BRIDGE(obj) \
     OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
 
+/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
+#define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
+
 struct PCIExpressHost {
     PCIHostState pci;
 
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index b70e5ad..410ac08 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -104,9 +104,6 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
     .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
-#define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
-
 int pcie_host_init(PCIExpressHost *e)
 {
     e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
-- 
MST

[Qemu-devel] [PULL 19/43] pcie_host: expose address format

[Michael S. Tsirkin]

Callers pass in the address so it's helpful for
them to be able to decode it.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pcie_host.h | 21 +++++++++++++++++++++
 hw/pci/pcie_host.c         | 21 ---------------------
 2 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index bac3c67..da0f275 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -54,4 +54,25 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
                             hwaddr addr,
                             uint32_t size);
 
+/*
+ * PCI express ECAM (Enhanced Configuration Address Mapping) format.
+ * AKA mmcfg address
+ * bit 20 - 28: bus number
+ * bit 15 - 19: device number
+ * bit 12 - 14: function number
+ * bit  0 - 11: offset in configuration space of a given device
+ */
+#define PCIE_MMCFG_SIZE_MAX             (1ULL << 28)
+#define PCIE_MMCFG_SIZE_MIN             (1ULL << 20)
+#define PCIE_MMCFG_BUS_BIT              20
+#define PCIE_MMCFG_BUS_MASK             0x1ff
+#define PCIE_MMCFG_DEVFN_BIT            12
+#define PCIE_MMCFG_DEVFN_MASK           0xff
+#define PCIE_MMCFG_CONFOFFSET_MASK      0xfff
+#define PCIE_MMCFG_BUS(addr)            (((addr) >> PCIE_MMCFG_BUS_BIT) & \
+                                         PCIE_MMCFG_BUS_MASK)
+#define PCIE_MMCFG_DEVFN(addr)          (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
+                                         PCIE_MMCFG_DEVFN_MASK)
+#define PCIE_MMCFG_CONFOFFSET(addr)     ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
+
 #endif /* PCIE_HOST_H */
diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
index 410ac08..c6e1b57 100644
--- a/hw/pci/pcie_host.c
+++ b/hw/pci/pcie_host.c
@@ -24,27 +24,6 @@
 #include "hw/pci/pcie_host.h"
 #include "exec/address-spaces.h"
 
-/*
- * PCI express mmcfig address
- * bit 20 - 28: bus number
- * bit 15 - 19: device number
- * bit 12 - 14: function number
- * bit  0 - 11: offset in configuration space of a given device
- */
-#define PCIE_MMCFG_SIZE_MAX             (1ULL << 28)
-#define PCIE_MMCFG_SIZE_MIN             (1ULL << 20)
-#define PCIE_MMCFG_BUS_BIT              20
-#define PCIE_MMCFG_BUS_MASK             0x1ff
-#define PCIE_MMCFG_DEVFN_BIT            12
-#define PCIE_MMCFG_DEVFN_MASK           0xff
-#define PCIE_MMCFG_CONFOFFSET_MASK      0xfff
-#define PCIE_MMCFG_BUS(addr)            (((addr) >> PCIE_MMCFG_BUS_BIT) & \
-                                         PCIE_MMCFG_BUS_MASK)
-#define PCIE_MMCFG_DEVFN(addr)          (((addr) >> PCIE_MMCFG_DEVFN_BIT) & \
-                                         PCIE_MMCFG_DEVFN_MASK)
-#define PCIE_MMCFG_CONFOFFSET(addr)     ((addr) & PCIE_MMCFG_CONFOFFSET_MASK)
-
-
 /* a helper function to get a PCIDevice for a given mmconfig address */
 static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s,
                                                      uint32_t mmcfg_addr)
-- 
MST

[Qemu-devel] [PULL 20/43] q35: use macro for MCFG property name

[Michael S. Tsirkin]

Useful to make it accessible through QOM.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pcie_host.h | 2 ++
 hw/pci-host/q35.c          | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index da0f275..33d75bd 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -28,6 +28,8 @@
 #define PCIE_HOST_BRIDGE(obj) \
     OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
 
+#define PCIE_HOST_MCFG_BASE "MCFG"
+
 /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
 #define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
 
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index 23dbeea..e46f286 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -110,7 +110,7 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
 }
 
 static Property mch_props[] = {
-    DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr,
+    DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
     DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
                      mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
-- 
MST

[Qemu-devel] [PULL 21/43] q35: expose mmcfg size as a property

[Michael S. Tsirkin]

Address is already exposed, expose size for symmetry.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pcie_host.h |  1 +
 hw/pci-host/q35.c          | 14 ++++++++++++++
 2 files changed, 15 insertions(+)

diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
index 33d75bd..acca45e 100644
--- a/include/hw/pci/pcie_host.h
+++ b/include/hw/pci/pcie_host.h
@@ -29,6 +29,7 @@
     OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
 
 #define PCIE_HOST_MCFG_BASE "MCFG"
+#define PCIE_HOST_MCFG_SIZE "mcfg_size"
 
 /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
 #define PCIE_BASE_ADDR_UNMAPPED  ((hwaddr)-1ULL)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index e46f286..a051b58 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
     visit_type_uint64(v, &w64.end, name, errp);
 }
 
+static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
+                                    void *opaque, const char *name,
+                                    Error **errp)
+{
+    PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
+    uint32_t value = e->size;
+
+    visit_type_uint32(v, &value, name, errp);
+}
+
 static Property mch_props[] = {
     DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr,
                         MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
@@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj)
                         q35_host_get_pci_hole64_end,
                         NULL, NULL, NULL, NULL);
 
+    object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
+                        q35_host_get_mmcfg_size,
+                        NULL, NULL, NULL, NULL);
+
     /* Leave enough space for the biggest MCFG BAR */
     /* TODO: this matches current bios behaviour, but
      * it's not a power of two, which means an MTRR
-- 
MST

[Qemu-devel] [PULL 22/43] i386: add ACPI table files from seabios

[Michael S. Tsirkin]

This adds ASL code as well as scripts for processing it,
imported from seabios git tree
commit 51684b7ced75fb76776e8ee84833fcfb6ecf12dd

Will be used for runtime acpi table generation.

Note:
This patch reuses some code from SeaBIOS, which was originally under
LGPLv2 and then relicensed to GPLv3 or LGPLv3, in QEMU under GPLv2+. This
relicensing has been acked by all contributors that had contributed to the
code since the v2->v3 relicense. ACKs approving the v2+ relicensing are
listed below. The list might include ACKs from people not holding
copyright on any parts of the reused code, but it's better to err on the
side of caution and include them.

Affected SeaBIOS files (GPLv2+ license headers added)
<http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/5949>:

 src/acpi-dsdt-cpu-hotplug.dsl
 src/acpi-dsdt-dbug.dsl
 src/acpi-dsdt-hpet.dsl
 src/acpi-dsdt-isa.dsl
 src/acpi-dsdt-pci-crs.dsl
 src/acpi.c
 src/acpi.h
 src/ssdt-misc.dsl
 src/ssdt-pcihp.dsl
 src/ssdt-proc.dsl
 tools/acpi_extract.py
 tools/acpi_extract_preprocess.py

Each one of the listed people agreed to the following:

> If you allow the use of your contribution in QEMU under the
> terms of GPLv2 or later as proposed by this patch,
> please respond to this mail including the line:
>
> Acked-by: Name <email address>

  Acked-by: Gerd Hoffmann <kraxel@redhat.com>
  Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
  Acked-by: Jason Baron <jbaron@akamai.com>
  Acked-by: David Woodhouse <David.Woodhouse@intel.com>
  Acked-by: Gleb Natapov <gleb@redhat.com>
  Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
  Acked-by: Dave Frodin <dave.frodin@se-eng.com>
  Acked-by: Paolo Bonzini <pbonzini@redhat.com>
  Acked-by: Kevin O'Connor <kevin@koconnor.net>
  Acked-by: Laszlo Ersek <lersek@redhat.com>
  Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
  Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
  Acked-by: Magnus Christensson <magnus.christensson@intel.com>
  Acked-by: Hu Tao <hutao@cn.fujitsu.com>
  Acked-by: Eduardo Habkost <ehabkost@redhat.com>

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Hu Tao <hutao@cn.fujitsu.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/acpi-dsdt-cpu-hotplug.dsl  |  93 ++++++++
 hw/i386/acpi-dsdt-dbug.dsl         |  41 ++++
 hw/i386/acpi-dsdt-hpet.dsl         |  51 +++++
 hw/i386/acpi-dsdt-isa.dsl          | 117 ++++++++++
 hw/i386/acpi-dsdt-pci-crs.dsl      | 105 +++++++++
 hw/i386/acpi-dsdt.dsl              | 343 ++++++++++++++++++++++++++++
 hw/i386/q35-acpi-dsdt.dsl          | 452 +++++++++++++++++++++++++++++++++++++
 hw/i386/ssdt-misc.dsl              | 119 ++++++++++
 hw/i386/ssdt-pcihp.dsl             |  51 +++++
 hw/i386/ssdt-proc.dsl              |  63 ++++++
 scripts/acpi_extract.py            | 362 +++++++++++++++++++++++++++++
 scripts/acpi_extract_preprocess.py |  51 +++++
 12 files changed, 1848 insertions(+)
 create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
 create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
 create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
 create mode 100644 hw/i386/acpi-dsdt-isa.dsl
 create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
 create mode 100644 hw/i386/acpi-dsdt.dsl
 create mode 100644 hw/i386/q35-acpi-dsdt.dsl
 create mode 100644 hw/i386/ssdt-misc.dsl
 create mode 100644 hw/i386/ssdt-pcihp.dsl
 create mode 100644 hw/i386/ssdt-proc.dsl
 create mode 100755 scripts/acpi_extract.py
 create mode 100755 scripts/acpi_extract_preprocess.py

diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
new file mode 100644
index 0000000..c96ac42
--- /dev/null
+++ b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
@@ -0,0 +1,93 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * CPU hotplug
+ ****************************************************************/
+
+Scope(\_SB) {
+    /* Objects filled in by run-time generated SSDT */
+    External(NTFY, MethodObj)
+    External(CPON, PkgObj)
+
+    /* Methods called by run-time generated SSDT Processor objects */
+    Method(CPMA, 1, NotSerialized) {
+        // _MAT method - create an madt apic buffer
+        // Arg0 = Processor ID = Local APIC ID
+        // Local0 = CPON flag for this cpu
+        Store(DerefOf(Index(CPON, Arg0)), Local0)
+        // Local1 = Buffer (in madt apic form) to return
+        Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
+        // Update the processor id, lapic id, and enable/disable status
+        Store(Arg0, Index(Local1, 2))
+        Store(Arg0, Index(Local1, 3))
+        Store(Local0, Index(Local1, 4))
+        Return (Local1)
+    }
+    Method(CPST, 1, NotSerialized) {
+        // _STA method - return ON status of cpu
+        // Arg0 = Processor ID = Local APIC ID
+        // Local0 = CPON flag for this cpu
+        Store(DerefOf(Index(CPON, Arg0)), Local0)
+        If (Local0) {
+            Return (0xF)
+        } Else {
+            Return (0x0)
+        }
+    }
+    Method(CPEJ, 2, NotSerialized) {
+        // _EJ0 method - eject callback
+        Sleep(200)
+    }
+
+    /* CPU hotplug notify method */
+    OperationRegion(PRST, SystemIO, 0xaf00, 32)
+    Field(PRST, ByteAcc, NoLock, Preserve) {
+        PRS, 256
+    }
+    Method(PRSC, 0) {
+        // Local5 = active cpu bitmap
+        Store(PRS, Local5)
+        // Local2 = last read byte from bitmap
+        Store(Zero, Local2)
+        // Local0 = Processor ID / APIC ID iterator
+        Store(Zero, Local0)
+        While (LLess(Local0, SizeOf(CPON))) {
+            // Local1 = CPON flag for this cpu
+            Store(DerefOf(Index(CPON, Local0)), Local1)
+            If (And(Local0, 0x07)) {
+                // Shift down previously read bitmap byte
+                ShiftRight(Local2, 1, Local2)
+            } Else {
+                // Read next byte from cpu bitmap
+                Store(DerefOf(Index(Local5, ShiftRight(Local0, 3))), Local2)
+            }
+            // Local3 = active state for this cpu
+            Store(And(Local2, 1), Local3)
+
+            If (LNotEqual(Local1, Local3)) {
+                // State change - update CPON with new state
+                Store(Local3, Index(CPON, Local0))
+                // Do CPU notify
+                If (LEqual(Local3, 1)) {
+                    NTFY(Local0, 1)
+                } Else {
+                    NTFY(Local0, 3)
+                }
+            }
+            Increment(Local0)
+        }
+    }
+}
diff --git a/hw/i386/acpi-dsdt-dbug.dsl b/hw/i386/acpi-dsdt-dbug.dsl
new file mode 100644
index 0000000..86230f7
--- /dev/null
+++ b/hw/i386/acpi-dsdt-dbug.dsl
@@ -0,0 +1,41 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * Debugging
+ ****************************************************************/
+
+Scope(\) {
+    /* Debug Output */
+    OperationRegion(DBG, SystemIO, 0x0402, 0x01)
+    Field(DBG, ByteAcc, NoLock, Preserve) {
+        DBGB,   8,
+    }
+
+    /* Debug method - use this method to send output to the QEMU
+     * BIOS debug port.  This method handles strings, integers,
+     * and buffers.  For example: DBUG("abc") DBUG(0x123) */
+    Method(DBUG, 1) {
+        ToHexString(Arg0, Local0)
+        ToBuffer(Local0, Local0)
+        Subtract(SizeOf(Local0), 1, Local1)
+        Store(Zero, Local2)
+        While (LLess(Local2, Local1)) {
+            Store(DerefOf(Index(Local0, Local2)), DBGB)
+            Increment(Local2)
+        }
+        Store(0x0A, DBGB)
+    }
+}
diff --git a/hw/i386/acpi-dsdt-hpet.dsl b/hw/i386/acpi-dsdt-hpet.dsl
new file mode 100644
index 0000000..dfde174
--- /dev/null
+++ b/hw/i386/acpi-dsdt-hpet.dsl
@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/****************************************************************
+ * HPET
+ ****************************************************************/
+
+Scope(\_SB) {
+    Device(HPET) {
+        Name(_HID, EISAID("PNP0103"))
+        Name(_UID, 0)
+        OperationRegion(HPTM, SystemMemory, 0xFED00000, 0x400)
+        Field(HPTM, DWordAcc, Lock, Preserve) {
+            VEND, 32,
+            PRD, 32,
+        }
+        Method(_STA, 0, NotSerialized) {
+            Store(VEND, Local0)
+            Store(PRD, Local1)
+            ShiftRight(Local0, 16, Local0)
+            If (LOr(LEqual(Local0, 0), LEqual(Local0, 0xffff))) {
+                Return (0x0)
+            }
+            If (LOr(LEqual(Local1, 0), LGreater(Local1, 100000000))) {
+                Return (0x0)
+            }
+            Return (0x0F)
+        }
+        Name(_CRS, ResourceTemplate() {
+#if 0       /* This makes WinXP BSOD for not yet figured reasons. */
+            IRQNoFlags() {2, 8}
+#endif
+            Memory32Fixed(ReadOnly,
+                0xFED00000,         // Address Base
+                0x00000400,         // Address Length
+                )
+        })
+    }
+}
diff --git a/hw/i386/acpi-dsdt-isa.dsl b/hw/i386/acpi-dsdt-isa.dsl
new file mode 100644
index 0000000..89caa16
--- /dev/null
+++ b/hw/i386/acpi-dsdt-isa.dsl
@@ -0,0 +1,117 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Common legacy ISA style devices. */
+Scope(\_SB.PCI0.ISA) {
+
+    Device(RTC) {
+        Name(_HID, EisaId("PNP0B00"))
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x0070, 0x0070, 0x10, 0x02)
+            IRQNoFlags() { 8 }
+            IO(Decode16, 0x0072, 0x0072, 0x02, 0x06)
+        })
+    }
+
+    Device(KBD) {
+        Name(_HID, EisaId("PNP0303"))
+        Method(_STA, 0, NotSerialized) {
+            Return (0x0f)
+        }
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x0060, 0x0060, 0x01, 0x01)
+            IO(Decode16, 0x0064, 0x0064, 0x01, 0x01)
+            IRQNoFlags() { 1 }
+        })
+    }
+
+    Device(MOU) {
+        Name(_HID, EisaId("PNP0F13"))
+        Method(_STA, 0, NotSerialized) {
+            Return (0x0f)
+        }
+        Name(_CRS, ResourceTemplate() {
+            IRQNoFlags() { 12 }
+        })
+    }
+
+    Device(FDC0) {
+        Name(_HID, EisaId("PNP0700"))
+        Method(_STA, 0, NotSerialized) {
+            Store(FDEN, Local0)
+            If (LEqual(Local0, 0)) {
+                Return (0x00)
+            } Else {
+                Return (0x0F)
+            }
+        }
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x03F2, 0x03F2, 0x00, 0x04)
+            IO(Decode16, 0x03F7, 0x03F7, 0x00, 0x01)
+            IRQNoFlags() { 6 }
+            DMA(Compatibility, NotBusMaster, Transfer8) { 2 }
+        })
+    }
+
+    Device(LPT) {
+        Name(_HID, EisaId("PNP0400"))
+        Method(_STA, 0, NotSerialized) {
+            Store(LPEN, Local0)
+            If (LEqual(Local0, 0)) {
+                Return (0x00)
+            } Else {
+                Return (0x0F)
+            }
+        }
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x0378, 0x0378, 0x08, 0x08)
+            IRQNoFlags() { 7 }
+        })
+    }
+
+    Device(COM1) {
+        Name(_HID, EisaId("PNP0501"))
+        Name(_UID, 0x01)
+        Method(_STA, 0, NotSerialized) {
+            Store(CAEN, Local0)
+            If (LEqual(Local0, 0)) {
+                Return (0x00)
+            } Else {
+                Return (0x0F)
+            }
+        }
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x03F8, 0x03F8, 0x00, 0x08)
+            IRQNoFlags() { 4 }
+        })
+    }
+
+    Device(COM2) {
+        Name(_HID, EisaId("PNP0501"))
+        Name(_UID, 0x02)
+        Method(_STA, 0, NotSerialized) {
+            Store(CBEN, Local0)
+            If (LEqual(Local0, 0)) {
+                Return (0x00)
+            } Else {
+                Return (0x0F)
+            }
+        }
+        Name(_CRS, ResourceTemplate() {
+            IO(Decode16, 0x02F8, 0x02F8, 0x00, 0x08)
+            IRQNoFlags() { 3 }
+        })
+    }
+}
diff --git a/hw/i386/acpi-dsdt-pci-crs.dsl b/hw/i386/acpi-dsdt-pci-crs.dsl
new file mode 100644
index 0000000..b375a19
--- /dev/null
+++ b/hw/i386/acpi-dsdt-pci-crs.dsl
@@ -0,0 +1,105 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* PCI CRS (current resources) definition. */
+Scope(\_SB.PCI0) {
+
+    Name(CRES, ResourceTemplate() {
+        WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode,
+            0x0000,             // Address Space Granularity
+            0x0000,             // Address Range Minimum
+            0x00FF,             // Address Range Maximum
+            0x0000,             // Address Translation Offset
+            0x0100,             // Address Length
+            ,, )
+        IO(Decode16,
+            0x0CF8,             // Address Range Minimum
+            0x0CF8,             // Address Range Maximum
+            0x01,               // Address Alignment
+            0x08,               // Address Length
+            )
+        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+            0x0000,             // Address Space Granularity
+            0x0000,             // Address Range Minimum
+            0x0CF7,             // Address Range Maximum
+            0x0000,             // Address Translation Offset
+            0x0CF8,             // Address Length
+            ,, , TypeStatic)
+        WordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+            0x0000,             // Address Space Granularity
+            0x0D00,             // Address Range Minimum
+            0xFFFF,             // Address Range Maximum
+            0x0000,             // Address Translation Offset
+            0xF300,             // Address Length
+            ,, , TypeStatic)
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+            0x00000000,         // Address Space Granularity
+            0x000A0000,         // Address Range Minimum
+            0x000BFFFF,         // Address Range Maximum
+            0x00000000,         // Address Translation Offset
+            0x00020000,         // Address Length
+            ,, , AddressRangeMemory, TypeStatic)
+        DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+            0x00000000,         // Address Space Granularity
+            0xE0000000,         // Address Range Minimum
+            0xFEBFFFFF,         // Address Range Maximum
+            0x00000000,         // Address Translation Offset
+            0x1EC00000,         // Address Length
+            ,, PW32, AddressRangeMemory, TypeStatic)
+    })
+
+    Name(CR64, ResourceTemplate() {
+        QWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+            0x00000000,          // Address Space Granularity
+            0x8000000000,        // Address Range Minimum
+            0xFFFFFFFFFF,        // Address Range Maximum
+            0x00000000,          // Address Translation Offset
+            0x8000000000,        // Address Length
+            ,, PW64, AddressRangeMemory, TypeStatic)
+    })
+
+    Method(_CRS, 0) {
+        /* Fields provided by dynamically created ssdt */
+        External(P0S, IntObj)
+        External(P0E, IntObj)
+        External(P1V, IntObj)
+        External(P1S, BuffObj)
+        External(P1E, BuffObj)
+        External(P1L, BuffObj)
+
+        /* fixup 32bit pci io window */
+        CreateDWordField(CRES, \_SB.PCI0.PW32._MIN, PS32)
+        CreateDWordField(CRES, \_SB.PCI0.PW32._MAX, PE32)
+        CreateDWordField(CRES, \_SB.PCI0.PW32._LEN, PL32)
+        Store(P0S, PS32)
+        Store(P0E, PE32)
+        Store(Add(Subtract(P0E, P0S), 1), PL32)
+
+        If (LEqual(P1V, Zero)) {
+            Return (CRES)
+        }
+
+        /* fixup 64bit pci io window */
+        CreateQWordField(CR64, \_SB.PCI0.PW64._MIN, PS64)
+        CreateQWordField(CR64, \_SB.PCI0.PW64._MAX, PE64)
+        CreateQWordField(CR64, \_SB.PCI0.PW64._LEN, PL64)
+        Store(P1S, PS64)
+        Store(P1E, PE64)
+        Store(P1L, PL64)
+        /* add window and return result */
+        ConcatenateResTemplate(CRES, CR64, Local0)
+        Return (Local0)
+    }
+}
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
new file mode 100644
index 0000000..90efce0
--- /dev/null
+++ b/hw/i386/acpi-dsdt.dsl
@@ -0,0 +1,343 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+ACPI_EXTRACT_ALL_CODE AcpiDsdtAmlCode
+
+DefinitionBlock (
+    "acpi-dsdt.aml",    // Output Filename
+    "DSDT",             // Signature
+    0x01,               // DSDT Compliance Revision
+    "BXPC",             // OEMID
+    "BXDSDT",           // TABLE ID
+    0x1                 // OEM Revision
+    )
+{
+
+#include "acpi-dsdt-dbug.dsl"
+
+
+/****************************************************************
+ * PCI Bus definition
+ ****************************************************************/
+
+    Scope(\_SB) {
+        Device(PCI0) {
+            Name(_HID, EisaId("PNP0A03"))
+            Name(_ADR, 0x00)
+            Name(_UID, 1)
+        }
+    }
+
+#include "acpi-dsdt-pci-crs.dsl"
+#include "acpi-dsdt-hpet.dsl"
+
+
+/****************************************************************
+ * VGA
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(VGA) {
+            Name(_ADR, 0x00020000)
+            OperationRegion(PCIC, PCI_Config, Zero, 0x4)
+            Field(PCIC, DWordAcc, NoLock, Preserve) {
+                VEND, 32
+            }
+            Method(_S1D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S2D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S3D, 0, NotSerialized) {
+                If (LEqual(VEND, 0x1001b36)) {
+                    Return (0x03)           // QXL
+                } Else {
+                    Return (0x00)
+                }
+            }
+        }
+    }
+
+
+/****************************************************************
+ * PIIX4 PM
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(PX13) {
+            Name(_ADR, 0x00010003)
+            OperationRegion(P13C, PCI_Config, 0x00, 0xff)
+        }
+    }
+
+
+/****************************************************************
+ * PIIX3 ISA bridge
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(ISA) {
+            Name(_ADR, 0x00010000)
+
+            /* PIIX PCI to ISA irq remapping */
+            OperationRegion(P40C, PCI_Config, 0x60, 0x04)
+
+            /* enable bits */
+            Field(\_SB.PCI0.PX13.P13C, AnyAcc, NoLock, Preserve) {
+                Offset(0x5f),
+                , 7,
+                LPEN, 1,         // LPT
+                Offset(0x67),
+                , 3,
+                CAEN, 1,         // COM1
+                , 3,
+                CBEN, 1,         // COM2
+            }
+            Name(FDEN, 1)
+        }
+    }
+
+#include "acpi-dsdt-isa.dsl"
+
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        OperationRegion(PCST, SystemIO, 0xae00, 0x08)
+        Field(PCST, DWordAcc, NoLock, WriteAsZeros) {
+            PCIU, 32,
+            PCID, 32,
+        }
+
+        OperationRegion(SEJ, SystemIO, 0xae08, 0x04)
+        Field(SEJ, DWordAcc, NoLock, WriteAsZeros) {
+            B0EJ, 32,
+        }
+
+        /* Methods called by bulk generated PCI devices below */
+
+        /* Methods called by hotplug devices */
+        Method(PCEJ, 1, NotSerialized) {
+            // _EJ0 method - eject callback
+            Store(ShiftLeft(1, Arg0), B0EJ)
+            Return (0x0)
+        }
+
+        /* Hotplug notification method supplied by SSDT */
+        External(\_SB.PCI0.PCNT, MethodObj)
+
+        /* PCI hotplug notify method */
+        Method(PCNF, 0) {
+            // Local0 = iterator
+            Store(Zero, Local0)
+            While (LLess(Local0, 31)) {
+                Increment(Local0)
+                If (And(PCIU, ShiftLeft(1, Local0))) {
+                    PCNT(Local0, 1)
+                }
+                If (And(PCID, ShiftLeft(1, Local0))) {
+                    PCNT(Local0, 3)
+                }
+            }
+        }
+    }
+
+
+/****************************************************************
+ * PCI IRQs
+ ****************************************************************/
+
+    Scope(\_SB) {
+        Scope(PCI0) {
+            Name(_PRT, Package() {
+                /* PCI IRQ routing table, example from ACPI 2.0a specification,
+                   section 6.2.8.1 */
+                /* Note: we provide the same info as the PCI routing
+                   table of the Bochs BIOS */
+
+#define prt_slot(nr, lnk0, lnk1, lnk2, lnk3) \
+    Package() { nr##ffff, 0, lnk0, 0 }, \
+    Package() { nr##ffff, 1, lnk1, 0 }, \
+    Package() { nr##ffff, 2, lnk2, 0 }, \
+    Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot0(nr) prt_slot(nr, LNKD, LNKA, LNKB, LNKC)
+#define prt_slot1(nr) prt_slot(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot2(nr) prt_slot(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot3(nr) prt_slot(nr, LNKC, LNKD, LNKA, LNKB)
+
+                prt_slot0(0x0000),
+                /* Device 1 is power mgmt device, and can only use irq 9 */
+                prt_slot(0x0001, LNKS, LNKB, LNKC, LNKD),
+                prt_slot2(0x0002),
+                prt_slot3(0x0003),
+                prt_slot0(0x0004),
+                prt_slot1(0x0005),
+                prt_slot2(0x0006),
+                prt_slot3(0x0007),
+                prt_slot0(0x0008),
+                prt_slot1(0x0009),
+                prt_slot2(0x000a),
+                prt_slot3(0x000b),
+                prt_slot0(0x000c),
+                prt_slot1(0x000d),
+                prt_slot2(0x000e),
+                prt_slot3(0x000f),
+                prt_slot0(0x0010),
+                prt_slot1(0x0011),
+                prt_slot2(0x0012),
+                prt_slot3(0x0013),
+                prt_slot0(0x0014),
+                prt_slot1(0x0015),
+                prt_slot2(0x0016),
+                prt_slot3(0x0017),
+                prt_slot0(0x0018),
+                prt_slot1(0x0019),
+                prt_slot2(0x001a),
+                prt_slot3(0x001b),
+                prt_slot0(0x001c),
+                prt_slot1(0x001d),
+                prt_slot2(0x001e),
+                prt_slot3(0x001f),
+            })
+        }
+
+        Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
+            PRQ0,   8,
+            PRQ1,   8,
+            PRQ2,   8,
+            PRQ3,   8
+        }
+
+        Method(IQST, 1, NotSerialized) {
+            // _STA method - get status
+            If (And(0x80, Arg0)) {
+                Return (0x09)
+            }
+            Return (0x0B)
+        }
+        Method(IQCR, 1, NotSerialized) {
+            // _CRS method - get current settings
+            Name(PRR0, ResourceTemplate() {
+                Interrupt(, Level, ActiveHigh, Shared) { 0 }
+            })
+            CreateDWordField(PRR0, 0x05, PRRI)
+            If (LLess(Arg0, 0x80)) {
+                Store(Arg0, PRRI)
+            }
+            Return (PRR0)
+        }
+
+#define define_link(link, uid, reg)                             \
+        Device(link) {                                          \
+            Name(_HID, EISAID("PNP0C0F"))                       \
+            Name(_UID, uid)                                     \
+            Name(_PRS, ResourceTemplate() {                     \
+                Interrupt(, Level, ActiveHigh, Shared) {        \
+                    5, 10, 11                                   \
+                }                                               \
+            })                                                  \
+            Method(_STA, 0, NotSerialized) {                    \
+                Return (IQST(reg))                              \
+            }                                                   \
+            Method(_DIS, 0, NotSerialized) {                    \
+                Or(reg, 0x80, reg)                              \
+            }                                                   \
+            Method(_CRS, 0, NotSerialized) {                    \
+                Return (IQCR(reg))                              \
+            }                                                   \
+            Method(_SRS, 1, NotSerialized) {                    \
+                CreateDWordField(Arg0, 0x05, PRRI)              \
+                Store(PRRI, reg)                                \
+            }                                                   \
+        }
+
+        define_link(LNKA, 0, PRQ0)
+        define_link(LNKB, 1, PRQ1)
+        define_link(LNKC, 2, PRQ2)
+        define_link(LNKD, 3, PRQ3)
+
+        Device(LNKS) {
+            Name(_HID, EISAID("PNP0C0F"))
+            Name(_UID, 4)
+            Name(_PRS, ResourceTemplate() {
+                Interrupt(, Level, ActiveHigh, Shared) { 9 }
+            })
+
+            // The SCI cannot be disabled and is always attached to GSI 9,
+            // so these are no-ops.  We only need this link to override the
+            // polarity to active high and match the content of the MADT.
+            Method(_STA, 0, NotSerialized) { Return (0x0b) }
+            Method(_DIS, 0, NotSerialized) { }
+            Method(_CRS, 0, NotSerialized) { Return (_PRS) }
+            Method(_SRS, 1, NotSerialized) { }
+        }
+    }
+
+#include "acpi-dsdt-cpu-hotplug.dsl"
+
+
+/****************************************************************
+ * General purpose events
+ ****************************************************************/
+
+    Scope(\_GPE) {
+        Name(_HID, "ACPI0006")
+
+        Method(_L00) {
+        }
+        Method(_E01) {
+            // PCI hotplug event
+            \_SB.PCI0.PCNF()
+        }
+        Method(_E02) {
+            // CPU hotplug event
+            \_SB.PRSC()
+        }
+        Method(_L03) {
+        }
+        Method(_L04) {
+        }
+        Method(_L05) {
+        }
+        Method(_L06) {
+        }
+        Method(_L07) {
+        }
+        Method(_L08) {
+        }
+        Method(_L09) {
+        }
+        Method(_L0A) {
+        }
+        Method(_L0B) {
+        }
+        Method(_L0C) {
+        }
+        Method(_L0D) {
+        }
+        Method(_L0E) {
+        }
+        Method(_L0F) {
+        }
+    }
+}
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
new file mode 100644
index 0000000..21c89b0
--- /dev/null
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -0,0 +1,452 @@
+/*
+ * Bochs/QEMU ACPI DSDT ASL definition
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+/*
+ * Copyright (c) 2010 Isaku Yamahata
+ *                    yamahata at valinux co jp
+ * Based on acpi-dsdt.dsl, but heavily modified for q35 chipset.
+ */
+
+ACPI_EXTRACT_ALL_CODE Q35AcpiDsdtAmlCode
+
+DefinitionBlock (
+    "q35-acpi-dsdt.aml",// Output Filename
+    "DSDT",             // Signature
+    0x01,               // DSDT Compliance Revision
+    "BXPC",             // OEMID
+    "BXDSDT",           // TABLE ID
+    0x2                 // OEM Revision
+    )
+{
+
+#include "acpi-dsdt-dbug.dsl"
+
+    Scope(\_SB) {
+        OperationRegion(PCST, SystemIO, 0xae00, 0x0c)
+        OperationRegion(PCSB, SystemIO, 0xae0c, 0x01)
+        Field(PCSB, AnyAcc, NoLock, WriteAsZeros) {
+            PCIB, 8,
+        }
+    }
+
+
+/****************************************************************
+ * PCI Bus definition
+ ****************************************************************/
+
+    Scope(\_SB) {
+        Device(PCI0) {
+            Name(_HID, EisaId("PNP0A08"))
+            Name(_CID, EisaId("PNP0A03"))
+            Name(_ADR, 0x00)
+            Name(_UID, 1)
+
+            // _OSC: based on sample of ACPI3.0b spec
+            Name(SUPP, 0) // PCI _OSC Support Field value
+            Name(CTRL, 0) // PCI _OSC Control Field value
+            Method(_OSC, 4) {
+                // Create DWORD-addressable fields from the Capabilities Buffer
+                CreateDWordField(Arg3, 0, CDW1)
+
+                // Check for proper UUID
+                If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+                    // Create DWORD-addressable fields from the Capabilities Buffer
+                    CreateDWordField(Arg3, 4, CDW2)
+                    CreateDWordField(Arg3, 8, CDW3)
+
+                    // Save Capabilities DWORD2 & 3
+                    Store(CDW2, SUPP)
+                    Store(CDW3, CTRL)
+
+                    // Always allow native PME, AER (no dependencies)
+                    // Never allow SHPC (no SHPC controller in this system)
+                    And(CTRL, 0x1D, CTRL)
+
+#if 0 // For now, nothing to do
+                    If (Not(And(CDW1, 1))) { // Query flag clear?
+                        // Disable GPEs for features granted native control.
+                        If (And(CTRL, 0x01)) { // Hot plug control granted?
+                            Store(0, HPCE) // clear the hot plug SCI enable bit
+                            Store(1, HPCS) // clear the hot plug SCI status bit
+                        }
+                        If (And(CTRL, 0x04)) { // PME control granted?
+                            Store(0, PMCE) // clear the PME SCI enable bit
+                            Store(1, PMCS) // clear the PME SCI status bit
+                        }
+                        If (And(CTRL, 0x10)) { // OS restoring PCI Express cap structure?
+                            // Set status to not restore PCI Express cap structure
+                            // upon resume from S3
+                            Store(1, S3CR)
+                        }
+                    }
+#endif
+                    If (LNotEqual(Arg1, One)) {
+                        // Unknown revision
+                        Or(CDW1, 0x08, CDW1)
+                    }
+                    If (LNotEqual(CDW3, CTRL)) {
+                        // Capabilities bits were masked
+                        Or(CDW1, 0x10, CDW1)
+                    }
+                    // Update DWORD3 in the buffer
+                    Store(CTRL, CDW3)
+                } Else {
+                    Or(CDW1, 4, CDW1) // Unrecognized UUID
+                }
+                Return (Arg3)
+            }
+        }
+    }
+
+#include "acpi-dsdt-pci-crs.dsl"
+#include "acpi-dsdt-hpet.dsl"
+
+
+/****************************************************************
+ * VGA
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        Device(VGA) {
+            Name(_ADR, 0x00010000)
+            Method(_S1D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S2D, 0, NotSerialized) {
+                Return (0x00)
+            }
+            Method(_S3D, 0, NotSerialized) {
+                Return (0x00)
+            }
+        }
+    }
+
+
+/****************************************************************
+ * LPC ISA bridge
+ ****************************************************************/
+
+    Scope(\_SB.PCI0) {
+        /* PCI D31:f0 LPC ISA bridge */
+        Device(ISA) {
+            /* PCI D31:f0 */
+            Name(_ADR, 0x001f0000)
+
+            /* ICH9 PCI to ISA irq remapping */
+            OperationRegion(PIRQ, PCI_Config, 0x60, 0x0C)
+
+            OperationRegion(LPCD, PCI_Config, 0x80, 0x2)
+            Field(LPCD, AnyAcc, NoLock, Preserve) {
+                COMA,   3,
+                    ,   1,
+                COMB,   3,
+
+                Offset(0x01),
+                LPTD,   2,
+                    ,   2,
+                FDCD,   2
+            }
+            OperationRegion(LPCE, PCI_Config, 0x82, 0x2)
+            Field(LPCE, AnyAcc, NoLock, Preserve) {
+                CAEN,   1,
+                CBEN,   1,
+                LPEN,   1,
+                FDEN,   1
+            }
+        }
+    }
+
+#include "acpi-dsdt-isa.dsl"
+
+
+/****************************************************************
+ * PCI IRQs
+ ****************************************************************/
+
+    /* Zero => PIC mode, One => APIC Mode */
+    Name(\PICF, Zero)
+    Method(\_PIC, 1, NotSerialized) {
+        Store(Arg0, \PICF)
+    }
+
+    Scope(\_SB) {
+        Scope(PCI0) {
+#define prt_slot_lnk(nr, lnk0, lnk1, lnk2, lnk3)  \
+    Package() { nr##ffff, 0, lnk0, 0 },           \
+    Package() { nr##ffff, 1, lnk1, 0 },           \
+    Package() { nr##ffff, 2, lnk2, 0 },           \
+    Package() { nr##ffff, 3, lnk3, 0 }
+
+#define prt_slot_lnkA(nr) prt_slot_lnk(nr, LNKA, LNKB, LNKC, LNKD)
+#define prt_slot_lnkB(nr) prt_slot_lnk(nr, LNKB, LNKC, LNKD, LNKA)
+#define prt_slot_lnkC(nr) prt_slot_lnk(nr, LNKC, LNKD, LNKA, LNKB)
+#define prt_slot_lnkD(nr) prt_slot_lnk(nr, LNKD, LNKA, LNKB, LNKC)
+
+#define prt_slot_lnkE(nr) prt_slot_lnk(nr, LNKE, LNKF, LNKG, LNKH)
+#define prt_slot_lnkF(nr) prt_slot_lnk(nr, LNKF, LNKG, LNKH, LNKE)
+#define prt_slot_lnkG(nr) prt_slot_lnk(nr, LNKG, LNKH, LNKE, LNKF)
+#define prt_slot_lnkH(nr) prt_slot_lnk(nr, LNKH, LNKE, LNKF, LNKG)
+
+            Name(PRTP, package() {
+                prt_slot_lnkE(0x0000),
+                prt_slot_lnkF(0x0001),
+                prt_slot_lnkG(0x0002),
+                prt_slot_lnkH(0x0003),
+                prt_slot_lnkE(0x0004),
+                prt_slot_lnkF(0x0005),
+                prt_slot_lnkG(0x0006),
+                prt_slot_lnkH(0x0007),
+                prt_slot_lnkE(0x0008),
+                prt_slot_lnkF(0x0009),
+                prt_slot_lnkG(0x000a),
+                prt_slot_lnkH(0x000b),
+                prt_slot_lnkE(0x000c),
+                prt_slot_lnkF(0x000d),
+                prt_slot_lnkG(0x000e),
+                prt_slot_lnkH(0x000f),
+                prt_slot_lnkE(0x0010),
+                prt_slot_lnkF(0x0011),
+                prt_slot_lnkG(0x0012),
+                prt_slot_lnkH(0x0013),
+                prt_slot_lnkE(0x0014),
+                prt_slot_lnkF(0x0015),
+                prt_slot_lnkG(0x0016),
+                prt_slot_lnkH(0x0017),
+                prt_slot_lnkE(0x0018),
+
+                /* INTA -> PIRQA for slot 25 - 31
+                   see the default value of D<N>IR */
+                prt_slot_lnkA(0x0019),
+                prt_slot_lnkA(0x001a),
+                prt_slot_lnkA(0x001b),
+                prt_slot_lnkA(0x001c),
+                prt_slot_lnkA(0x001d),
+
+                /* PCIe->PCI bridge. use PIRQ[E-H] */
+                prt_slot_lnkE(0x001e),
+
+                prt_slot_lnkA(0x001f)
+            })
+
+#define prt_slot_gsi(nr, gsi0, gsi1, gsi2, gsi3)  \
+    Package() { nr##ffff, 0, gsi0, 0 },           \
+    Package() { nr##ffff, 1, gsi1, 0 },           \
+    Package() { nr##ffff, 2, gsi2, 0 },           \
+    Package() { nr##ffff, 3, gsi3, 0 }
+
+#define prt_slot_gsiA(nr) prt_slot_gsi(nr, GSIA, GSIB, GSIC, GSID)
+#define prt_slot_gsiB(nr) prt_slot_gsi(nr, GSIB, GSIC, GSID, GSIA)
+#define prt_slot_gsiC(nr) prt_slot_gsi(nr, GSIC, GSID, GSIA, GSIB)
+#define prt_slot_gsiD(nr) prt_slot_gsi(nr, GSID, GSIA, GSIB, GSIC)
+
+#define prt_slot_gsiE(nr) prt_slot_gsi(nr, GSIE, GSIF, GSIG, GSIH)
+#define prt_slot_gsiF(nr) prt_slot_gsi(nr, GSIF, GSIG, GSIH, GSIE)
+#define prt_slot_gsiG(nr) prt_slot_gsi(nr, GSIG, GSIH, GSIE, GSIF)
+#define prt_slot_gsiH(nr) prt_slot_gsi(nr, GSIH, GSIE, GSIF, GSIG)
+
+            Name(PRTA, package() {
+                prt_slot_gsiE(0x0000),
+                prt_slot_gsiF(0x0001),
+                prt_slot_gsiG(0x0002),
+                prt_slot_gsiH(0x0003),
+                prt_slot_gsiE(0x0004),
+                prt_slot_gsiF(0x0005),
+                prt_slot_gsiG(0x0006),
+                prt_slot_gsiH(0x0007),
+                prt_slot_gsiE(0x0008),
+                prt_slot_gsiF(0x0009),
+                prt_slot_gsiG(0x000a),
+                prt_slot_gsiH(0x000b),
+                prt_slot_gsiE(0x000c),
+                prt_slot_gsiF(0x000d),
+                prt_slot_gsiG(0x000e),
+                prt_slot_gsiH(0x000f),
+                prt_slot_gsiE(0x0010),
+                prt_slot_gsiF(0x0011),
+                prt_slot_gsiG(0x0012),
+                prt_slot_gsiH(0x0013),
+                prt_slot_gsiE(0x0014),
+                prt_slot_gsiF(0x0015),
+                prt_slot_gsiG(0x0016),
+                prt_slot_gsiH(0x0017),
+                prt_slot_gsiE(0x0018),
+
+                /* INTA -> PIRQA for slot 25 - 31, but 30
+                   see the default value of D<N>IR */
+                prt_slot_gsiA(0x0019),
+                prt_slot_gsiA(0x001a),
+                prt_slot_gsiA(0x001b),
+                prt_slot_gsiA(0x001c),
+                prt_slot_gsiA(0x001d),
+
+                /* PCIe->PCI bridge. use PIRQ[E-H] */
+                prt_slot_gsiE(0x001e),
+
+                prt_slot_gsiA(0x001f)
+            })
+
+            Method(_PRT, 0, NotSerialized) {
+                /* PCI IRQ routing table, example from ACPI 2.0a specification,
+                   section 6.2.8.1 */
+                /* Note: we provide the same info as the PCI routing
+                   table of the Bochs BIOS */
+                If (LEqual(\PICF, Zero)) {
+                    Return (PRTP)
+                } Else {
+                    Return (PRTA)
+                }
+            }
+        }
+
+        Field(PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) {
+            PRQA,   8,
+            PRQB,   8,
+            PRQC,   8,
+            PRQD,   8,
+
+            Offset(0x08),
+            PRQE,   8,
+            PRQF,   8,
+            PRQG,   8,
+            PRQH,   8
+        }
+
+        Method(IQST, 1, NotSerialized) {
+            // _STA method - get status
+            If (And(0x80, Arg0)) {
+                Return (0x09)
+            }
+            Return (0x0B)
+        }
+        Method(IQCR, 1, NotSerialized) {
+            // _CRS method - get current settings
+            Name(PRR0, ResourceTemplate() {
+                Interrupt(, Level, ActiveHigh, Shared) { 0 }
+            })
+            CreateDWordField(PRR0, 0x05, PRRI)
+            Store(And(Arg0, 0x0F), PRRI)
+            Return (PRR0)
+        }
+
+#define define_link(link, uid, reg)                             \
+        Device(link) {                                          \
+            Name(_HID, EISAID("PNP0C0F"))                       \
+            Name(_UID, uid)                                     \
+            Name(_PRS, ResourceTemplate() {                     \
+                Interrupt(, Level, ActiveHigh, Shared) {        \
+                    5, 10, 11                                   \
+                }                                               \
+            })                                                  \
+            Method(_STA, 0, NotSerialized) {                    \
+                Return (IQST(reg))                              \
+            }                                                   \
+            Method(_DIS, 0, NotSerialized) {                    \
+                Or(reg, 0x80, reg)                              \
+            }                                                   \
+            Method(_CRS, 0, NotSerialized) {                    \
+                Return (IQCR(reg))                              \
+            }                                                   \
+            Method(_SRS, 1, NotSerialized) {                    \
+                CreateDWordField(Arg0, 0x05, PRRI)              \
+                Store(PRRI, reg)                                \
+            }                                                   \
+        }
+
+        define_link(LNKA, 0, PRQA)
+        define_link(LNKB, 1, PRQB)
+        define_link(LNKC, 2, PRQC)
+        define_link(LNKD, 3, PRQD)
+        define_link(LNKE, 4, PRQE)
+        define_link(LNKF, 5, PRQF)
+        define_link(LNKG, 6, PRQG)
+        define_link(LNKH, 7, PRQH)
+
+#define define_gsi_link(link, uid, gsi)                         \
+        Device(link) {                                          \
+            Name(_HID, EISAID("PNP0C0F"))                       \
+            Name(_UID, uid)                                     \
+            Name(_PRS, ResourceTemplate() {                     \
+                Interrupt(, Level, ActiveHigh, Shared) {        \
+                    gsi                                         \
+                }                                               \
+            })                                                  \
+            Name(_CRS, ResourceTemplate() {                     \
+                Interrupt(, Level, ActiveHigh, Shared) {        \
+                    gsi                                         \
+                }                                               \
+            })                                                  \
+            Method(_SRS, 1, NotSerialized) {                    \
+            }                                                   \
+        }
+
+        define_gsi_link(GSIA, 0, 0x10)
+        define_gsi_link(GSIB, 0, 0x11)
+        define_gsi_link(GSIC, 0, 0x12)
+        define_gsi_link(GSID, 0, 0x13)
+        define_gsi_link(GSIE, 0, 0x14)
+        define_gsi_link(GSIF, 0, 0x15)
+        define_gsi_link(GSIG, 0, 0x16)
+        define_gsi_link(GSIH, 0, 0x17)
+    }
+
+#include "acpi-dsdt-cpu-hotplug.dsl"
+
+
+/****************************************************************
+ * General purpose events
+ ****************************************************************/
+
+    Scope(\_GPE) {
+        Name(_HID, "ACPI0006")
+
+        Method(_L00) {
+        }
+        Method(_L01) {
+            // CPU hotplug event
+            \_SB.PRSC()
+        }
+        Method(_L02) {
+        }
+        Method(_L03) {
+        }
+        Method(_L04) {
+        }
+        Method(_L05) {
+        }
+        Method(_L06) {
+        }
+        Method(_L07) {
+        }
+        Method(_L08) {
+        }
+        Method(_L09) {
+        }
+        Method(_L0A) {
+        }
+        Method(_L0B) {
+        }
+        Method(_L0C) {
+        }
+        Method(_L0D) {
+        }
+        Method(_L0E) {
+        }
+        Method(_L0F) {
+        }
+    }
+}
diff --git a/hw/i386/ssdt-misc.dsl b/hw/i386/ssdt-misc.dsl
new file mode 100644
index 0000000..a4484b8
--- /dev/null
+++ b/hw/i386/ssdt-misc.dsl
@@ -0,0 +1,119 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_misc_aml
+
+DefinitionBlock ("ssdt-misc.aml", "SSDT", 0x01, "BXPC", "BXSSDTSUSP", 0x1)
+{
+
+/****************************************************************
+ * PCI memory ranges
+ ****************************************************************/
+
+    Scope(\) {
+       ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_start
+       Name(P0S, 0x12345678)
+       ACPI_EXTRACT_NAME_DWORD_CONST acpi_pci32_end
+       Name(P0E, 0x12345678)
+       ACPI_EXTRACT_NAME_BYTE_CONST acpi_pci64_valid
+       Name(P1V, 0x12)
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_start
+       Name(P1S, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_end
+       Name(P1E, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+       ACPI_EXTRACT_NAME_BUFFER8 acpi_pci64_length
+       Name(P1L, Buffer() { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 })
+    }
+
+
+/****************************************************************
+ * Suspend
+ ****************************************************************/
+
+    Scope(\) {
+    /*
+     * S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
+     * must match piix4 emulation.
+     */
+
+        ACPI_EXTRACT_NAME_STRING acpi_s3_name
+        Name(_S3, Package(0x04) {
+            One,  /* PM1a_CNT.SLP_TYP */
+            One,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+        ACPI_EXTRACT_NAME_STRING acpi_s4_name
+        ACPI_EXTRACT_PKG_START acpi_s4_pkg
+        Name(_S4, Package(0x04) {
+            0x2,  /* PM1a_CNT.SLP_TYP */
+            0x2,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+        Name(_S5, Package(0x04) {
+            Zero,  /* PM1a_CNT.SLP_TYP */
+            Zero,  /* PM1b_CNT.SLP_TYP */
+            Zero,  /* reserved */
+            Zero   /* reserved */
+        })
+    }
+
+    External(\_SB.PCI0, DeviceObj)
+    External(\_SB.PCI0.ISA, DeviceObj)
+
+    Scope(\_SB.PCI0.ISA) {
+        Device(PEVT) {
+            Name(_HID, "QEMU0001")
+            /* PEST will be patched to be Zero if no such device */
+            ACPI_EXTRACT_NAME_WORD_CONST ssdt_isa_pest
+            Name(PEST, 0xFFFF)
+            OperationRegion(PEOR, SystemIO, PEST, 0x01)
+            Field(PEOR, ByteAcc, NoLock, Preserve) {
+                PEPT,   8,
+            }
+
+            Method(_STA, 0, NotSerialized) {
+                Store(PEST, Local0)
+                If (LEqual(Local0, Zero)) {
+                    Return (0x00)
+                } Else {
+                    Return (0x0F)
+                }
+            }
+
+            Method(RDPT, 0, NotSerialized) {
+                Store(PEPT, Local0)
+                Return (Local0)
+            }
+
+            Method(WRPT, 1, NotSerialized) {
+                Store(Arg0, PEPT)
+            }
+
+            Name(_CRS, ResourceTemplate() {
+                IO(Decode16, 0x00, 0x00, 0x01, 0x01, IO)
+            })
+
+            CreateWordField(_CRS, IO._MIN, IOMN)
+            CreateWordField(_CRS, IO._MAX, IOMX)
+
+            Method(_INI, 0, NotSerialized) {
+                Store(PEST, IOMN)
+                Store(PEST, IOMX)
+            }
+        }
+    }
+}
diff --git a/hw/i386/ssdt-pcihp.dsl b/hw/i386/ssdt-pcihp.dsl
new file mode 100644
index 0000000..d29a5b9
--- /dev/null
+++ b/hw/i386/ssdt-pcihp.dsl
@@ -0,0 +1,51 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml
+
+DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+{
+
+/****************************************************************
+ * PCI hotplug
+ ****************************************************************/
+
+    /* Objects supplied by DSDT */
+    External(\_SB.PCI0, DeviceObj)
+    External(\_SB.PCI0.PCEJ, MethodObj)
+
+    Scope(\_SB.PCI0) {
+
+        /* Bulk generated PCI hotplug devices */
+        ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start
+        ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
+        ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
+
+        // Method _EJ0 can be patched by BIOS to EJ0_
+        // at runtime, if the slot is detected to not support hotplug.
+        // Extract the offset of the address dword and the
+        // _EJ0 name to allow this patching.
+        Device(SAA) {
+            ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
+            Name(_SUN, 0xAA)
+            ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
+            Name(_ADR, 0xAA0000)
+            ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0
+            Method(_EJ0, 1) {
+                Return (PCEJ(_SUN))
+            }
+        }
+    }
+}
diff --git a/hw/i386/ssdt-proc.dsl b/hw/i386/ssdt-proc.dsl
new file mode 100644
index 0000000..58333c7
--- /dev/null
+++ b/hw/i386/ssdt-proc.dsl
@@ -0,0 +1,63 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* This file is the basis for the ssdt table generated in src/acpi.c.
+ * It defines the contents of the per-cpu Processor() object.  At
+ * runtime, a dynamically generated SSDT will contain one copy of this
+ * AML snippet for every possible cpu in the system.  The objects will
+ * be placed in the \_SB_ namespace.
+ *
+ * In addition to the aml code generated from this file, the
+ * src/acpi.c file creates a NTFY method with an entry for each cpu:
+ *     Method(NTFY, 2) {
+ *         If (LEqual(Arg0, 0x00)) { Notify(CP00, Arg1) }
+ *         If (LEqual(Arg0, 0x01)) { Notify(CP01, Arg1) }
+ *         ...
+ *     }
+ * and a CPON array with the list of active and inactive cpus:
+ *     Name(CPON, Package() { One, One, ..., Zero, Zero, ... })
+ */
+
+ACPI_EXTRACT_ALL_CODE ssdp_proc_aml
+
+DefinitionBlock ("ssdt-proc.aml", "SSDT", 0x01, "BXPC", "BXSSDT", 0x1)
+{
+    ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
+    ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
+    ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
+    Processor(CPAA, 0xAA, 0x0000b010, 0x06) {
+        ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
+        Name(ID, 0xAA)
+/*
+ * The src/acpi.c code requires the above ACP_EXTRACT tags so that it can update
+ * CPAA and 0xAA with the appropriate CPU id (see
+ * SD_OFFSET_CPUHEX/CPUID1/CPUID2).  Don't change the above without
+ * also updating the C code.
+ */
+        Name(_HID, "ACPI0007")
+        External(CPMA, MethodObj)
+        External(CPST, MethodObj)
+        External(CPEJ, MethodObj)
+        Method(_MAT, 0) {
+            Return (CPMA(ID))
+        }
+        Method(_STA, 0) {
+            Return (CPST(ID))
+        }
+        Method(_EJ0, 1, NotSerialized) {
+            CPEJ(ID, Arg0)
+        }
+    }
+}
diff --git a/scripts/acpi_extract.py b/scripts/acpi_extract.py
new file mode 100755
index 0000000..22ea468
--- /dev/null
+++ b/scripts/acpi_extract.py
@@ -0,0 +1,362 @@
+#!/usr/bin/python
+# Copyright (C) 2011 Red Hat, Inc., Michael S. Tsirkin <mst@redhat.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, see <http://www.gnu.org/licenses/>.
+
+# Process mixed ASL/AML listing (.lst file) produced by iasl -l
+# Locate and execute ACPI_EXTRACT directives, output offset info
+#
+# Documentation of ACPI_EXTRACT_* directive tags:
+#
+# These directive tags output offset information from AML for BIOS runtime
+# table generation.
+# Each directive is of the form:
+# ACPI_EXTRACT_<TYPE> <array_name> <Operator> (...)
+# and causes the extractor to create an array
+# named <array_name> with offset, in the generated AML,
+# of an object of a given type in the following <Operator>.
+#
+# A directive must fit on a single code line.
+#
+# Object type in AML is verified, a mismatch causes a build failure.
+#
+# Directives and operators currently supported are:
+# ACPI_EXTRACT_NAME_DWORD_CONST - extract a Dword Const object from Name()
+# ACPI_EXTRACT_NAME_WORD_CONST - extract a Word Const object from Name()
+# ACPI_EXTRACT_NAME_BYTE_CONST - extract a Byte Const object from Name()
+# ACPI_EXTRACT_METHOD_STRING - extract a NameString from Method()
+# ACPI_EXTRACT_NAME_STRING - extract a NameString from Name()
+# ACPI_EXTRACT_PROCESSOR_START - start of Processor() block
+# ACPI_EXTRACT_PROCESSOR_STRING - extract a NameString from Processor()
+# ACPI_EXTRACT_PROCESSOR_END - offset at last byte of Processor() + 1
+# ACPI_EXTRACT_PKG_START - start of Package block
+#
+# ACPI_EXTRACT_ALL_CODE - create an array storing the generated AML bytecode
+#
+# ACPI_EXTRACT is not allowed anywhere else in code, except in comments.
+
+import re;
+import sys;
+import fileinput;
+
+aml = []
+asl = []
+output = {}
+debug = ""
+
+class asl_line:
+    line = None
+    lineno = None
+    aml_offset = None
+
+def die(diag):
+    sys.stderr.write("Error: %s; %s\n" % (diag, debug))
+    sys.exit(1)
+
+#Store an ASL command, matching AML offset, and input line (for debugging)
+def add_asl(lineno, line):
+    l = asl_line()
+    l.line = line
+    l.lineno = lineno
+    l.aml_offset = len(aml)
+    asl.append(l)
+
+#Store an AML byte sequence
+#Verify that offset output by iasl matches # of bytes so far
+def add_aml(offset, line):
+    o = int(offset, 16);
+    # Sanity check: offset must match size of code so far
+    if (o != len(aml)):
+        die("Offset 0x%x != 0x%x" % (o, len(aml)))
+    # Strip any trailing dots and ASCII dump after "
+    line = re.sub(r'\s*\.*\s*".*$',"", line)
+    # Strip traling whitespace
+    line = re.sub(r'\s+$',"", line)
+    # Strip leading whitespace
+    line = re.sub(r'^\s+',"", line)
+    # Split on whitespace
+    code = re.split(r'\s+', line)
+    for c in code:
+        # Require a legal hex number, two digits
+        if (not(re.search(r'^[0-9A-Fa-f][0-9A-Fa-f]$', c))):
+            die("Unexpected octet %s" % c);
+        aml.append(int(c, 16));
+
+# Process aml bytecode array, decoding AML
+def aml_pkglen_bytes(offset):
+    # PkgLength can be multibyte. Bits 8-7 give the # of extra bytes.
+    pkglenbytes = aml[offset] >> 6;
+    return pkglenbytes + 1
+
+def aml_pkglen(offset):
+    pkgstart = offset
+    pkglenbytes = aml_pkglen_bytes(offset)
+    pkglen = aml[offset] & 0x3F
+    # If multibyte, first nibble only uses bits 0-3
+    if ((pkglenbytes > 1) and (pkglen & 0x30)):
+        die("PkgLen bytes 0x%x but first nibble 0x%x expected 0x0X" %
+            (pkglen, pkglen))
+    offset += 1
+    pkglenbytes -= 1
+    for i in range(pkglenbytes):
+        pkglen |= aml[offset + i] << (i * 8 + 4)
+    if (len(aml) < pkgstart + pkglen):
+        die("PckgLen 0x%x at offset 0x%x exceeds AML size 0x%x" %
+            (pkglen, offset, len(aml)))
+    return pkglen
+
+# Given method offset, find its NameString offset
+def aml_method_string(offset):
+    #0x14 MethodOp PkgLength NameString MethodFlags TermList
+    if (aml[offset] != 0x14):
+        die( "Method offset 0x%x: expected 0x14 actual 0x%x" %
+             (offset, aml[offset]));
+    offset += 1;
+    pkglenbytes = aml_pkglen_bytes(offset)
+    offset += pkglenbytes;
+    return offset;
+
+# Given name offset, find its NameString offset
+def aml_name_string(offset):
+    #0x08 NameOp NameString DataRef
+    if (aml[offset] != 0x08):
+        die( "Name offset 0x%x: expected 0x08 actual 0x%x" %
+             (offset, aml[offset]));
+    offset += 1
+    # Block Name Modifier. Skip it.
+    if (aml[offset] == 0x5c or aml[offset] == 0x5e):
+        offset += 1
+    return offset;
+
+# Given data offset, find 8 byte buffer offset
+def aml_data_buffer8(offset):
+    #0x08 NameOp NameString DataRef
+    expect = [0x11, 0x0B, 0x0A, 0x08]
+    if (aml[offset:offset+4] != expect):
+        die( "Name offset 0x%x: expected %s actual %s" %
+             (offset, aml[offset:offset+4], expect))
+    return offset + len(expect)
+
+# Given data offset, find dword const offset
+def aml_data_dword_const(offset):
+    #0x08 NameOp NameString DataRef
+    if (aml[offset] != 0x0C):
+        die( "Name offset 0x%x: expected 0x0C actual 0x%x" %
+             (offset, aml[offset]));
+    return offset + 1;
+
+# Given data offset, find word const offset
+def aml_data_word_const(offset):
+    #0x08 NameOp NameString DataRef
+    if (aml[offset] != 0x0B):
+        die( "Name offset 0x%x: expected 0x0B actual 0x%x" %
+             (offset, aml[offset]));
+    return offset + 1;
+
+# Given data offset, find byte const offset
+def aml_data_byte_const(offset):
+    #0x08 NameOp NameString DataRef
+    if (aml[offset] != 0x0A):
+        die( "Name offset 0x%x: expected 0x0A actual 0x%x" %
+             (offset, aml[offset]));
+    return offset + 1;
+
+# Find name'd buffer8
+def aml_name_buffer8(offset):
+    return aml_data_buffer8(aml_name_string(offset) + 4)
+
+# Given name offset, find dword const offset
+def aml_name_dword_const(offset):
+    return aml_data_dword_const(aml_name_string(offset) + 4)
+
+# Given name offset, find word const offset
+def aml_name_word_const(offset):
+    return aml_data_word_const(aml_name_string(offset) + 4)
+
+# Given name offset, find byte const offset
+def aml_name_byte_const(offset):
+    return aml_data_byte_const(aml_name_string(offset) + 4)
+
+def aml_device_start(offset):
+    #0x5B 0x82 DeviceOp PkgLength NameString
+    if ((aml[offset] != 0x5B) or (aml[offset + 1] != 0x82)):
+        die( "Name offset 0x%x: expected 0x5B 0x82 actual 0x%x 0x%x" %
+             (offset, aml[offset], aml[offset + 1]));
+    return offset
+
+def aml_device_string(offset):
+    #0x5B 0x82 DeviceOp PkgLength NameString
+    start = aml_device_start(offset)
+    offset += 2
+    pkglenbytes = aml_pkglen_bytes(offset)
+    offset += pkglenbytes
+    return offset
+
+def aml_device_end(offset):
+    start = aml_device_start(offset)
+    offset += 2
+    pkglenbytes = aml_pkglen_bytes(offset)
+    pkglen = aml_pkglen(offset)
+    return offset + pkglen
+
+def aml_processor_start(offset):
+    #0x5B 0x83 ProcessorOp PkgLength NameString ProcID
+    if ((aml[offset] != 0x5B) or (aml[offset + 1] != 0x83)):
+        die( "Name offset 0x%x: expected 0x5B 0x83 actual 0x%x 0x%x" %
+             (offset, aml[offset], aml[offset + 1]));
+    return offset
+
+def aml_processor_string(offset):
+    #0x5B 0x83 ProcessorOp PkgLength NameString ProcID
+    start = aml_processor_start(offset)
+    offset += 2
+    pkglenbytes = aml_pkglen_bytes(offset)
+    offset += pkglenbytes
+    return offset
+
+def aml_processor_end(offset):
+    start = aml_processor_start(offset)
+    offset += 2
+    pkglenbytes = aml_pkglen_bytes(offset)
+    pkglen = aml_pkglen(offset)
+    return offset + pkglen
+
+def aml_package_start(offset):
+    offset = aml_name_string(offset) + 4
+    # 0x12 PkgLength NumElements PackageElementList
+    if (aml[offset] != 0x12):
+        die( "Name offset 0x%x: expected 0x12 actual 0x%x" %
+             (offset, aml[offset]));
+    offset += 1
+    return offset + aml_pkglen_bytes(offset) + 1
+
+lineno = 0
+for line in fileinput.input():
+    # Strip trailing newline
+    line = line.rstrip();
+    # line number and debug string to output in case of errors
+    lineno = lineno + 1
+    debug = "input line %d: %s" % (lineno, line)
+    #ASL listing: space, then line#, then ...., then code
+    pasl = re.compile('^\s+([0-9]+)(:\s\s|\.\.\.\.)\s*')
+    m = pasl.search(line)
+    if (m):
+        add_asl(lineno, pasl.sub("", line));
+    # AML listing: offset in hex, then ...., then code
+    paml = re.compile('^([0-9A-Fa-f]+)(:\s\s|\.\.\.\.)\s*')
+    m = paml.search(line)
+    if (m):
+        add_aml(m.group(1), paml.sub("", line))
+
+# Now go over code
+# Track AML offset of a previous non-empty ASL command
+prev_aml_offset = -1
+for i in range(len(asl)):
+    debug = "input line %d: %s" % (asl[i].lineno, asl[i].line)
+
+    l = asl[i].line
+
+    # skip if not an extract directive
+    a = len(re.findall(r'ACPI_EXTRACT', l))
+    if (not a):
+        # If not empty, store AML offset. Will be used for sanity checks
+        # IASL seems to put {}. at random places in the listing.
+        # Ignore any non-words for the purpose of this test.
+        m = re.search(r'\w+', l)
+        if (m):
+                prev_aml_offset = asl[i].aml_offset
+        continue
+
+    if (a > 1):
+        die("Expected at most one ACPI_EXTRACT per line, actual %d" % a)
+
+    mext = re.search(r'''
+                      ^\s* # leading whitespace
+                      /\*\s* # start C comment
+                      (ACPI_EXTRACT_\w+) # directive: group(1)
+                      \s+ # whitspace separates directive from array name
+                      (\w+) # array name: group(2)
+                      \s*\*/ # end of C comment
+                      \s*$ # trailing whitespace
+                      ''', l, re.VERBOSE)
+    if (not mext):
+        die("Stray ACPI_EXTRACT in input")
+
+    # previous command must have produced some AML,
+    # otherwise we are in a middle of a block
+    if (prev_aml_offset == asl[i].aml_offset):
+        die("ACPI_EXTRACT directive in the middle of a block")
+
+    directive = mext.group(1)
+    array = mext.group(2)
+    offset = asl[i].aml_offset
+
+    if (directive == "ACPI_EXTRACT_ALL_CODE"):
+        if array in output:
+            die("%s directive used more than once" % directive)
+        output[array] = aml
+        continue
+    if (directive == "ACPI_EXTRACT_NAME_BUFFER8"):
+        offset = aml_name_buffer8(offset)
+    elif (directive == "ACPI_EXTRACT_NAME_DWORD_CONST"):
+        offset = aml_name_dword_const(offset)
+    elif (directive == "ACPI_EXTRACT_NAME_WORD_CONST"):
+        offset = aml_name_word_const(offset)
+    elif (directive == "ACPI_EXTRACT_NAME_BYTE_CONST"):
+        offset = aml_name_byte_const(offset)
+    elif (directive == "ACPI_EXTRACT_NAME_STRING"):
+        offset = aml_name_string(offset)
+    elif (directive == "ACPI_EXTRACT_METHOD_STRING"):
+        offset = aml_method_string(offset)
+    elif (directive == "ACPI_EXTRACT_DEVICE_START"):
+        offset = aml_device_start(offset)
+    elif (directive == "ACPI_EXTRACT_DEVICE_STRING"):
+        offset = aml_device_string(offset)
+    elif (directive == "ACPI_EXTRACT_DEVICE_END"):
+        offset = aml_device_end(offset)
+    elif (directive == "ACPI_EXTRACT_PROCESSOR_START"):
+        offset = aml_processor_start(offset)
+    elif (directive == "ACPI_EXTRACT_PROCESSOR_STRING"):
+        offset = aml_processor_string(offset)
+    elif (directive == "ACPI_EXTRACT_PROCESSOR_END"):
+        offset = aml_processor_end(offset)
+    elif (directive == "ACPI_EXTRACT_PKG_START"):
+        offset = aml_package_start(offset)
+    else:
+        die("Unsupported directive %s" % directive)
+
+    if array not in output:
+        output[array] = []
+    output[array].append(offset)
+
+debug = "at end of file"
+
+def get_value_type(maxvalue):
+    #Use type large enough to fit the table
+    if (maxvalue >= 0x10000):
+            return "int"
+    elif (maxvalue >= 0x100):
+            return "short"
+    else:
+            return "char"
+
+# Pretty print output
+for array in output.keys():
+    otype = get_value_type(max(output[array]))
+    odata = []
+    for value in output[array]:
+        odata.append("0x%x" % value)
+    sys.stdout.write("static unsigned %s %s[] = {\n" % (otype, array))
+    sys.stdout.write(",\n".join(odata))
+    sys.stdout.write('\n};\n');
diff --git a/scripts/acpi_extract_preprocess.py b/scripts/acpi_extract_preprocess.py
new file mode 100755
index 0000000..69d10d6
--- /dev/null
+++ b/scripts/acpi_extract_preprocess.py
@@ -0,0 +1,51 @@
+#!/usr/bin/python
+# Copyright (C) 2011 Red Hat, Inc., Michael S. Tsirkin <mst@redhat.com>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, see <http://www.gnu.org/licenses/>.
+
+# Read a preprocessed ASL listing and put each ACPI_EXTRACT
+# directive in a comment, to make iasl skip it.
+# We also put each directive on a new line, the machinery
+# in tools/acpi_extract.py requires this.
+
+import re;
+import sys;
+import fileinput;
+
+def die(diag):
+    sys.stderr.write("Error: %s\n" % (diag))
+    sys.exit(1)
+
+# Note: () around pattern make split return matched string as part of list
+psplit = re.compile(r''' (
+                          \b # At word boundary
+                          ACPI_EXTRACT_\w+ # directive
+                          \s+ # some whitespace
+                          \w+ # array name
+                         )''', re.VERBOSE);
+
+lineno = 0
+for line in fileinput.input():
+    # line number and debug string to output in case of errors
+    lineno = lineno + 1
+    debug = "input line %d: %s" % (lineno, line.rstrip())
+
+    s = psplit.split(line);
+    # The way split works, each odd item is the matching ACPI_EXTRACT directive.
+    # Put each in a comment, and on a line by itself.
+    for i in range(len(s)):
+        if (i % 2):
+            sys.stdout.write("\n/* %s */\n" % s[i])
+        else:
+            sys.stdout.write(s[i])
-- 
MST

[Qemu-devel] [PULL 23/43] acpi: add rules to compile ASL source

[Michael S. Tsirkin]

Detect presence of IASL compiler and use it
to process ASL source. If not there, use pre-compiled
files in-tree. Add script to update the in-tree files.

Note: distros are known to silently update iasl
so detect correct iasl flags for the installed version on each run as
opposed to at configure time.

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 configure              |  9 ++++++++-
 hw/i386/Makefile.objs  | 22 ++++++++++++++++++++++
 scripts/update-acpi.sh |  4 ++++
 3 files changed, 34 insertions(+), 1 deletion(-)
 create mode 100644 scripts/update-acpi.sh

diff --git a/configure b/configure
index 2b83936..15405e1 100755
--- a/configure
+++ b/configure
@@ -119,6 +119,7 @@ path_of() {
 # default parameters
 source_path=`dirname "$0"`
 cpu=""
+iasl="iasl"
 interp_prefix="/usr/gnemul/qemu-%M"
 static="no"
 cross_prefix=""
@@ -257,6 +258,8 @@ for opt do
   ;;
   --cxx=*) CXX="$optarg"
   ;;
+  --iasl=*) iasl="$optarg"
+  ;;
   --source-path=*) source_path="$optarg"
   ;;
   --cpu=*) cpu="$optarg"
@@ -1055,6 +1058,7 @@ echo "Advanced options (experts only):"
 echo "  --source-path=PATH       path of source code [$source_path]"
 echo "  --cross-prefix=PREFIX    use PREFIX for compile tools [$cross_prefix]"
 echo "  --cc=CC                  use C compiler CC [$cc]"
+echo "  --iasl=IASL              use ACPI compiler IASL [$iasl]"
 echo "  --host-cc=CC             use C compiler CC [$host_cc] for code run at"
 echo "                           build time"
 echo "  --cxx=CXX                use C++ compiler CXX [$cxx]"
@@ -4239,6 +4243,9 @@ else
 fi
 echo "PYTHON=$python" >> $config_host_mak
 echo "CC=$cc" >> $config_host_mak
+if $iasl -h > /dev/null 2>&1; then
+  echo "IASL=$iasl" >> $config_host_mak
+fi
 echo "CC_I386=$cc_i386" >> $config_host_mak
 echo "HOST_CC=$host_cc" >> $config_host_mak
 echo "CXX=$cxx" >> $config_host_mak
@@ -4691,7 +4698,7 @@ for rom in seabios vgabios ; do
     echo "BCC=bcc" >> $config_mak
     echo "CPP=$cpp" >> $config_mak
     echo "OBJCOPY=objcopy" >> $config_mak
-    echo "IASL=iasl" >> $config_mak
+    echo "IASL=$iasl" >> $config_mak
     echo "LD=$ld" >> $config_mak
 done
 
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 45e6165..f950707 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -5,3 +5,25 @@ obj-y += pc_sysfw.o
 obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
 
 obj-y += kvmvapic.o
+
+iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
+    ; then echo "$(2)"; else echo "$(3)"; fi ;)
+
+ifdef IASL
+#IASL Present. Generate hex files from .dsl
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.dsl $(SRC_PATH)/scripts/acpi_extract_preprocess.py $(SRC_PATH)/scripts/acpi_extract.py
+	$(call quiet-command, cpp -P $< -o $*.dsl.i.orig, "  CPP $(TARGET_DIR)$*.dsl.i.orig")
+	$(call quiet-command, $(PYTHON) $(SRC_PATH)/scripts/acpi_extract_preprocess.py $*.dsl.i.orig > $*.dsl.i, "  ACPI_PREPROCESS $(TARGET_DIR)$*.dsl.i")
+	$(call quiet-command, $(IASL) $(call iasl-option,$(IASL),-Pn,) -vs -l -tc -p $* $*.dsl.i $(if $(V), , > /dev/null) 2>&1 ,"  IASL $(TARGET_DIR)$*.dsl.i")
+	$(call quiet-command, $(SRC_PATH)/scripts/acpi_extract.py $*.lst > $*.off, "  ACPI_EXTRACT $(TARGET_DIR)$*.off")
+	$(call quiet-command, cat $*.off > $@, "  CAT $(TARGET_DIR)$@")
+else
+#IASL Not present. Restore pre-generated hex files.
+hw/i386/%.hex: $(SRC_PATH)/hw/i386/%.hex.generated
+	$(call quiet-command, cp -f $< $@, "  CP $(TARGET_DIR)$@")
+endif
+
+.PHONY: cleanhex
+cleanhex:
+	rm -f hw/i386/*hex
+clean: cleanhex
diff --git a/scripts/update-acpi.sh b/scripts/update-acpi.sh
new file mode 100644
index 0000000..b5f05ff
--- /dev/null
+++ b/scripts/update-acpi.sh
@@ -0,0 +1,4 @@
+cd x86_64-softmmu
+for file in hw/i386/*.hex; do
+    cp -f $file ../$file.generated
+done
-- 
MST

[Qemu-devel] [PULL 24/43] acpi: pre-compiled ASL files

[Michael S. Tsirkin]

Add pre-compiled ASL files. Useful for systems that
do not have IASL.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
 hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
 hw/i386/ssdt-misc.hex.generated     |  386 ++
 hw/i386/ssdt-pcihp.hex.generated    |  108 +
 hw/i386/ssdt-proc.hex.generated     |  134 +
 5 files changed, 12383 insertions(+)
 create mode 100644 hw/i386/acpi-dsdt.hex.generated
 create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
 create mode 100644 hw/i386/ssdt-misc.hex.generated
 create mode 100644 hw/i386/ssdt-pcihp.hex.generated
 create mode 100644 hw/i386/ssdt-proc.hex.generated

diff --git a/hw/i386/acpi-dsdt.hex.generated b/hw/i386/acpi-dsdt.hex.generated
new file mode 100644
index 0000000..2c01107
--- /dev/null
+++ b/hw/i386/acpi-dsdt.hex.generated
@@ -0,0 +1,4409 @@
+static unsigned char AcpiDsdtAmlCode[] = {
+0x44,
+0x53,
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+0x37,
+0x11,
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+};
diff --git a/hw/i386/q35-acpi-dsdt.hex.generated b/hw/i386/q35-acpi-dsdt.hex.generated
new file mode 100644
index 0000000..32c16ff
--- /dev/null
+++ b/hw/i386/q35-acpi-dsdt.hex.generated
@@ -0,0 +1,7346 @@
+static unsigned char Q35AcpiDsdtAmlCode[] = {
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+0x53,
+0x54,
+0x1,
+0x70,
+0x83,
+0x88,
+0x43,
+0x50,
+0x4f,
+0x4e,
+0x68,
+0x0,
+0x60,
+0xa0,
+0x5,
+0x60,
+0xa4,
+0xa,
+0xf,
+0xa1,
+0x3,
+0xa4,
+0x0,
+0x14,
+0xa,
+0x43,
+0x50,
+0x45,
+0x4a,
+0x2,
+0x5b,
+0x22,
+0xa,
+0xc8,
+0x5b,
+0x80,
+0x50,
+0x52,
+0x53,
+0x54,
+0x1,
+0xb,
+0x0,
+0xaf,
+0xa,
+0x20,
+0x5b,
+0x81,
+0xc,
+0x50,
+0x52,
+0x53,
+0x54,
+0x1,
+0x50,
+0x52,
+0x53,
+0x5f,
+0x40,
+0x10,
+0x14,
+0x4a,
+0x6,
+0x50,
+0x52,
+0x53,
+0x43,
+0x0,
+0x70,
+0x50,
+0x52,
+0x53,
+0x5f,
+0x65,
+0x70,
+0x0,
+0x62,
+0x70,
+0x0,
+0x60,
+0xa2,
+0x46,
+0x5,
+0x95,
+0x60,
+0x87,
+0x43,
+0x50,
+0x4f,
+0x4e,
+0x70,
+0x83,
+0x88,
+0x43,
+0x50,
+0x4f,
+0x4e,
+0x60,
+0x0,
+0x61,
+0xa0,
+0xa,
+0x7b,
+0x60,
+0xa,
+0x7,
+0x0,
+0x7a,
+0x62,
+0x1,
+0x62,
+0xa1,
+0xc,
+0x70,
+0x83,
+0x88,
+0x65,
+0x7a,
+0x60,
+0xa,
+0x3,
+0x0,
+0x0,
+0x62,
+0x70,
+0x7b,
+0x62,
+0x1,
+0x0,
+0x63,
+0xa0,
+0x22,
+0x92,
+0x93,
+0x61,
+0x63,
+0x70,
+0x63,
+0x88,
+0x43,
+0x50,
+0x4f,
+0x4e,
+0x60,
+0x0,
+0xa0,
+0xa,
+0x93,
+0x63,
+0x1,
+0x4e,
+0x54,
+0x46,
+0x59,
+0x60,
+0x1,
+0xa1,
+0x8,
+0x4e,
+0x54,
+0x46,
+0x59,
+0x60,
+0xa,
+0x3,
+0x75,
+0x60,
+0x10,
+0x4f,
+0x8,
+0x5f,
+0x47,
+0x50,
+0x45,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xd,
+0x41,
+0x43,
+0x50,
+0x49,
+0x30,
+0x30,
+0x30,
+0x36,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x30,
+0x0,
+0x14,
+0x10,
+0x5f,
+0x4c,
+0x30,
+0x31,
+0x0,
+0x5c,
+0x2e,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x52,
+0x53,
+0x43,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x32,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x33,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x34,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x35,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x36,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x37,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x38,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x39,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x41,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x42,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x43,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x44,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x45,
+0x0,
+0x14,
+0x6,
+0x5f,
+0x4c,
+0x30,
+0x46,
+0x0
+};
diff --git a/hw/i386/ssdt-misc.hex.generated b/hw/i386/ssdt-misc.hex.generated
new file mode 100644
index 0000000..55e3bd2
--- /dev/null
+++ b/hw/i386/ssdt-misc.hex.generated
@@ -0,0 +1,386 @@
+static unsigned char acpi_pci64_length[] = {
+0x6f
+};
+static unsigned char acpi_s4_pkg[] = {
+0x8f
+};
+static unsigned char acpi_s3_name[] = {
+0x7c
+};
+static unsigned char acpi_pci32_start[] = {
+0x2f
+};
+static unsigned char acpi_pci64_valid[] = {
+0x43
+};
+static unsigned char ssdp_misc_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0x62,
+0x1,
+0x0,
+0x0,
+0x1,
+0x76,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x53,
+0x55,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x23,
+0x8,
+0x13,
+0x20,
+0x10,
+0x42,
+0x5,
+0x5c,
+0x0,
+0x8,
+0x50,
+0x30,
+0x53,
+0x5f,
+0xc,
+0x78,
+0x56,
+0x34,
+0x12,
+0x8,
+0x50,
+0x30,
+0x45,
+0x5f,
+0xc,
+0x78,
+0x56,
+0x34,
+0x12,
+0x8,
+0x50,
+0x31,
+0x56,
+0x5f,
+0xa,
+0x12,
+0x8,
+0x50,
+0x31,
+0x53,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x8,
+0x50,
+0x31,
+0x45,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x8,
+0x50,
+0x31,
+0x4c,
+0x5f,
+0x11,
+0xb,
+0xa,
+0x8,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x0,
+0x10,
+0x29,
+0x5c,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x33,
+0x5f,
+0x12,
+0x6,
+0x4,
+0x1,
+0x1,
+0x0,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x34,
+0x5f,
+0x12,
+0x8,
+0x4,
+0xa,
+0x2,
+0xa,
+0x2,
+0x0,
+0x0,
+0x8,
+0x5f,
+0x53,
+0x35,
+0x5f,
+0x12,
+0x6,
+0x4,
+0x0,
+0x0,
+0x0,
+0x0,
+0x10,
+0x40,
+0xc,
+0x5c,
+0x2f,
+0x3,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x49,
+0x53,
+0x41,
+0x5f,
+0x5b,
+0x82,
+0x4d,
+0xa,
+0x50,
+0x45,
+0x56,
+0x54,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xd,
+0x51,
+0x45,
+0x4d,
+0x55,
+0x30,
+0x30,
+0x30,
+0x31,
+0x0,
+0x8,
+0x50,
+0x45,
+0x53,
+0x54,
+0xb,
+0xff,
+0xff,
+0x5b,
+0x80,
+0x50,
+0x45,
+0x4f,
+0x52,
+0x1,
+0x50,
+0x45,
+0x53,
+0x54,
+0x1,
+0x5b,
+0x81,
+0xb,
+0x50,
+0x45,
+0x4f,
+0x52,
+0x1,
+0x50,
+0x45,
+0x50,
+0x54,
+0x8,
+0x14,
+0x18,
+0x5f,
+0x53,
+0x54,
+0x41,
+0x0,
+0x70,
+0x50,
+0x45,
+0x53,
+0x54,
+0x60,
+0xa0,
+0x6,
+0x93,
+0x60,
+0x0,
+0xa4,
+0x0,
+0xa1,
+0x4,
+0xa4,
+0xa,
+0xf,
+0x14,
+0xe,
+0x52,
+0x44,
+0x50,
+0x54,
+0x0,
+0x70,
+0x50,
+0x45,
+0x50,
+0x54,
+0x60,
+0xa4,
+0x60,
+0x14,
+0xc,
+0x57,
+0x52,
+0x50,
+0x54,
+0x1,
+0x70,
+0x68,
+0x50,
+0x45,
+0x50,
+0x54,
+0x8,
+0x5f,
+0x43,
+0x52,
+0x53,
+0x11,
+0xd,
+0xa,
+0xa,
+0x47,
+0x1,
+0x0,
+0x0,
+0x0,
+0x0,
+0x1,
+0x1,
+0x79,
+0x0,
+0x8b,
+0x5f,
+0x43,
+0x52,
+0x53,
+0xa,
+0x2,
+0x49,
+0x4f,
+0x4d,
+0x4e,
+0x8b,
+0x5f,
+0x43,
+0x52,
+0x53,
+0xa,
+0x4,
+0x49,
+0x4f,
+0x4d,
+0x58,
+0x14,
+0x18,
+0x5f,
+0x49,
+0x4e,
+0x49,
+0x0,
+0x70,
+0x50,
+0x45,
+0x53,
+0x54,
+0x49,
+0x4f,
+0x4d,
+0x4e,
+0x70,
+0x50,
+0x45,
+0x53,
+0x54,
+0x49,
+0x4f,
+0x4d,
+0x58
+};
+static unsigned char ssdt_isa_pest[] = {
+0xd0
+};
+static unsigned char acpi_s4_name[] = {
+0x88
+};
+static unsigned char acpi_pci64_start[] = {
+0x4d
+};
+static unsigned char acpi_pci64_end[] = {
+0x5e
+};
+static unsigned char acpi_pci32_end[] = {
+0x39
+};
diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
new file mode 100644
index 0000000..0d32a27
--- /dev/null
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -0,0 +1,108 @@
+static unsigned char ssdt_pcihp_name[] = {
+0x33
+};
+static unsigned char ssdt_pcihp_adr[] = {
+0x44
+};
+static unsigned char ssdt_pcihp_end[] = {
+0x58
+};
+static unsigned char ssdp_pcihp_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0x58,
+0x0,
+0x0,
+0x0,
+0x1,
+0x77,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x50,
+0x43,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x10,
+0x33,
+0x5c,
+0x2e,
+0x5f,
+0x53,
+0x42,
+0x5f,
+0x50,
+0x43,
+0x49,
+0x30,
+0x5b,
+0x82,
+0x26,
+0x53,
+0x41,
+0x41,
+0x5f,
+0x8,
+0x5f,
+0x53,
+0x55,
+0x4e,
+0xa,
+0xaa,
+0x8,
+0x5f,
+0x41,
+0x44,
+0x52,
+0xc,
+0x0,
+0x0,
+0xaa,
+0x0,
+0x14,
+0xf,
+0x5f,
+0x45,
+0x4a,
+0x30,
+0x1,
+0xa4,
+0x50,
+0x43,
+0x45,
+0x4a,
+0x5f,
+0x53,
+0x55,
+0x4e
+};
+static unsigned char ssdt_pcihp_start[] = {
+0x30
+};
+static unsigned char ssdt_pcihp_id[] = {
+0x3d
+};
+static unsigned char ssdt_pcihp_ej0[] = {
+0x4a
+};
diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
new file mode 100644
index 0000000..a28172e
--- /dev/null
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -0,0 +1,134 @@
+static unsigned char ssdt_proc_name[] = {
+0x28
+};
+static unsigned char ssdp_proc_aml[] = {
+0x53,
+0x53,
+0x44,
+0x54,
+0x78,
+0x0,
+0x0,
+0x0,
+0x1,
+0xb3,
+0x42,
+0x58,
+0x50,
+0x43,
+0x0,
+0x0,
+0x42,
+0x58,
+0x53,
+0x53,
+0x44,
+0x54,
+0x0,
+0x0,
+0x1,
+0x0,
+0x0,
+0x0,
+0x49,
+0x4e,
+0x54,
+0x4c,
+0x28,
+0x5,
+0x10,
+0x20,
+0x5b,
+0x83,
+0x42,
+0x5,
+0x43,
+0x50,
+0x41,
+0x41,
+0xaa,
+0x10,
+0xb0,
+0x0,
+0x0,
+0x6,
+0x8,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0xa,
+0xaa,
+0x8,
+0x5f,
+0x48,
+0x49,
+0x44,
+0xd,
+0x41,
+0x43,
+0x50,
+0x49,
+0x30,
+0x30,
+0x30,
+0x37,
+0x0,
+0x14,
+0xf,
+0x5f,
+0x4d,
+0x41,
+0x54,
+0x0,
+0xa4,
+0x43,
+0x50,
+0x4d,
+0x41,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x14,
+0xf,
+0x5f,
+0x53,
+0x54,
+0x41,
+0x0,
+0xa4,
+0x43,
+0x50,
+0x53,
+0x54,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x14,
+0xf,
+0x5f,
+0x45,
+0x4a,
+0x30,
+0x1,
+0x43,
+0x50,
+0x45,
+0x4a,
+0x49,
+0x44,
+0x5f,
+0x5f,
+0x68
+};
+static unsigned char ssdt_proc_id[] = {
+0x38
+};
+static unsigned char ssdt_proc_end[] = {
+0x78
+};
+static unsigned char ssdt_proc_start[] = {
+0x24
+};
-- 
MST

[Qemu-devel] [PULL 25/43] acpi: ssdt pcihp: updat generated file

[Michael S. Tsirkin]

update generated file, not sure what changed

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/ssdt-pcihp.hex.generated | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
index 0d32a27..b3c2cd5 100644
--- a/hw/i386/ssdt-pcihp.hex.generated
+++ b/hw/i386/ssdt-pcihp.hex.generated
@@ -17,7 +17,7 @@ static unsigned char ssdp_pcihp_aml[] = {
 0x0,
 0x0,
 0x1,
-0x77,
+0x76,
 0x42,
 0x58,
 0x50,
@@ -40,9 +40,9 @@ static unsigned char ssdp_pcihp_aml[] = {
 0x4e,
 0x54,
 0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
 0x20,
 0x10,
 0x33,
-- 
MST

Re: [Qemu-devel] [PULL 25/43] acpi: ssdt pcihp: updat generated file

[Anthony Liguori]

"Michael S. Tsirkin" <mst@redhat.com> writes:

> update generated file, not sure what changed
>
> Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> Tested-by: Gerd Hoffmann <kraxel@redhat.com>
> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> Tested-by: Igor Mammedov <imammedo@redhat.com>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

How in the world did this get reviewed by's????

Regards,

Anthony Liguori

> ---
>  hw/i386/ssdt-pcihp.hex.generated | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
> index 0d32a27..b3c2cd5 100644
> --- a/hw/i386/ssdt-pcihp.hex.generated
> +++ b/hw/i386/ssdt-pcihp.hex.generated
> @@ -17,7 +17,7 @@ static unsigned char ssdp_pcihp_aml[] = {
>  0x0,
>  0x0,
>  0x1,
> -0x77,
> +0x76,
>  0x42,
>  0x58,
>  0x50,
> @@ -40,9 +40,9 @@ static unsigned char ssdp_pcihp_aml[] = {
>  0x4e,
>  0x54,
>  0x4c,
> -0x28,
> -0x5,
> -0x10,
> +0x23,
> +0x8,
> +0x13,
>  0x20,
>  0x10,
>  0x33,
> -- 
> MST

Re: [Qemu-devel] [PULL 25/43] acpi: ssdt pcihp: updat generated file

[Michael S. Tsirkin]

On Mon, Oct 14, 2013 at 03:32:43PM -0700, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > update generated file, not sure what changed
> >
> > Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
> > Tested-by: Gerd Hoffmann <kraxel@redhat.com>
> > Reviewed-by: Igor Mammedov <imammedo@redhat.com>
> > Tested-by: Igor Mammedov <imammedo@redhat.com>
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> 
> How in the world did this get reviewed by's????

When people send reviewed-by for the series this
applies to the whole series.
Probably not much to review here besides the file names.

> Regards,
> 
> Anthony Liguori
> 
> > ---
> >  hw/i386/ssdt-pcihp.hex.generated | 8 ++++----
> >  1 file changed, 4 insertions(+), 4 deletions(-)
> >
> > diff --git a/hw/i386/ssdt-pcihp.hex.generated b/hw/i386/ssdt-pcihp.hex.generated
> > index 0d32a27..b3c2cd5 100644
> > --- a/hw/i386/ssdt-pcihp.hex.generated
> > +++ b/hw/i386/ssdt-pcihp.hex.generated
> > @@ -17,7 +17,7 @@ static unsigned char ssdp_pcihp_aml[] = {
> >  0x0,
> >  0x0,
> >  0x1,
> > -0x77,
> > +0x76,
> >  0x42,
> >  0x58,
> >  0x50,
> > @@ -40,9 +40,9 @@ static unsigned char ssdp_pcihp_aml[] = {
> >  0x4e,
> >  0x54,
> >  0x4c,
> > -0x28,
> > -0x5,
> > -0x10,
> > +0x23,
> > +0x8,
> > +0x13,
> >  0x20,
> >  0x10,
> >  0x33,
> > -- 
> > MST

[Qemu-devel] [PULL 26/43] loader: use file path size from fw_cfg.h

[Michael S. Tsirkin]

Avoid a bit of code duplication, make
max file path constant reusable.

Suggested-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/nvram/fw_cfg.h | 4 +++-
 hw/core/loader.c          | 2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index 2ab0fc2..72b1549 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -46,12 +46,14 @@
 
 #define FW_CFG_INVALID          0xffff
 
+#define FW_CFG_MAX_FILE_PATH    56
+
 #ifndef NO_QEMU_PROTOS
 typedef struct FWCfgFile {
     uint32_t  size;        /* file size */
     uint16_t  select;      /* write this to 0x510 to read it */
     uint16_t  reserved;
-    char      name[56];
+    char      name[FW_CFG_MAX_FILE_PATH];
 } FWCfgFile;
 
 typedef struct FWCfgFiles {
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 449bd4c..060729f 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -663,7 +663,7 @@ int rom_add_file(const char *file, const char *fw_dir,
     rom_insert(rom);
     if (rom->fw_file && fw_cfg) {
         const char *basename;
-        char fw_file_name[56];
+        char fw_file_name[FW_CFG_MAX_FILE_PATH];
         void *data;
 
         basename = strrchr(rom->fw_file, '/');
-- 
MST

[Qemu-devel] [PULL 27/43] i386: add bios linker/loader

[Michael S. Tsirkin]

This adds a dynamic bios linker/loader.
This will be used by acpi table generation
code to:
    - load each table in the appropriate memory segment
    - link tables to each other
    - fix up checksums after said linking

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/bios-linker-loader.h |  27 ++++++++
 hw/i386/bios-linker-loader.c | 158 +++++++++++++++++++++++++++++++++++++++++++
 hw/i386/Makefile.objs        |   1 +
 3 files changed, 186 insertions(+)
 create mode 100644 hw/i386/bios-linker-loader.h
 create mode 100644 hw/i386/bios-linker-loader.c

diff --git a/hw/i386/bios-linker-loader.h b/hw/i386/bios-linker-loader.h
new file mode 100644
index 0000000..498c0af
--- /dev/null
+++ b/hw/i386/bios-linker-loader.h
@@ -0,0 +1,27 @@
+#ifndef BIOS_LINKER_LOADER_H
+#define BIOS_LINKER_LOADER_H
+
+#include <glib.h>
+#include <stdbool.h>
+#include <inttypes.h>
+
+GArray *bios_linker_loader_init(void);
+
+void bios_linker_loader_alloc(GArray *linker,
+                              const char *file,
+                              uint32_t alloc_align,
+                              bool alloc_fseg);
+
+void bios_linker_loader_add_checksum(GArray *linker, const char *file,
+                                     void *table,
+                                     void *start, unsigned size,
+                                     uint8_t *checksum);
+
+void bios_linker_loader_add_pointer(GArray *linker,
+                                    const char *dest_file,
+                                    const char *src_file,
+                                    GArray *table, void *pointer,
+                                    uint8_t pointer_size);
+
+void *bios_linker_loader_cleanup(GArray *linker);
+#endif
diff --git a/hw/i386/bios-linker-loader.c b/hw/i386/bios-linker-loader.c
new file mode 100644
index 0000000..0833853
--- /dev/null
+++ b/hw/i386/bios-linker-loader.c
@@ -0,0 +1,158 @@
+/* Dynamic linker/loader of ACPI tables
+ *
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "bios-linker-loader.h"
+#include "hw/nvram/fw_cfg.h"
+
+#include <string.h>
+#include <assert.h>
+#include "qemu/bswap.h"
+
+#define BIOS_LINKER_LOADER_FILESZ FW_CFG_MAX_FILE_PATH
+
+struct BiosLinkerLoaderEntry {
+    uint32_t command;
+    union {
+        /*
+         * COMMAND_ALLOCATE - allocate a table from @alloc.file
+         * subject to @alloc.align alignment (must be power of 2)
+         * and @alloc.zone (can be HIGH or FSEG) requirements.
+         *
+         * Must appear exactly once for each file, and before
+         * this file is referenced by any other command.
+         */
+        struct {
+            char file[BIOS_LINKER_LOADER_FILESZ];
+            uint32_t align;
+            uint8_t zone;
+        } alloc;
+
+        /*
+         * COMMAND_ADD_POINTER - patch the table (originating from
+         * @dest_file) at @pointer.offset, by adding a pointer to the table
+         * originating from @src_file. 1,2,4 or 8 byte unsigned
+         * addition is used depending on @pointer.size.
+         */
+        struct {
+            char dest_file[BIOS_LINKER_LOADER_FILESZ];
+            char src_file[BIOS_LINKER_LOADER_FILESZ];
+            uint32_t offset;
+            uint8_t size;
+        } pointer;
+
+        /*
+         * COMMAND_ADD_CHECKSUM - calculate checksum of the range specified by
+         * @cksum_start and @cksum_length fields,
+         * and then add the value at @cksum.offset.
+         * Checksum simply sums -X for each byte X in the range
+         * using 8-bit math.
+         */
+        struct {
+            char file[BIOS_LINKER_LOADER_FILESZ];
+            uint32_t offset;
+            uint32_t start;
+            uint32_t length;
+        } cksum;
+
+        /* padding */
+        char pad[124];
+    };
+} QEMU_PACKED;
+typedef struct BiosLinkerLoaderEntry BiosLinkerLoaderEntry;
+
+enum {
+    BIOS_LINKER_LOADER_COMMAND_ALLOCATE     = 0x1,
+    BIOS_LINKER_LOADER_COMMAND_ADD_POINTER  = 0x2,
+    BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM = 0x3,
+};
+
+enum {
+    BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH = 0x1,
+    BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG = 0x2,
+};
+
+GArray *bios_linker_loader_init(void)
+{
+    return g_array_new(false, true /* clear */, sizeof(BiosLinkerLoaderEntry));
+}
+
+/* Free linker wrapper and return the linker array. */
+void *bios_linker_loader_cleanup(GArray *linker)
+{
+    return g_array_free(linker, false);
+}
+
+void bios_linker_loader_alloc(GArray *linker,
+                              const char *file,
+                              uint32_t alloc_align,
+                              bool alloc_fseg)
+{
+    BiosLinkerLoaderEntry entry;
+
+    memset(&entry, 0, sizeof entry);
+    strncpy(entry.alloc.file, file, sizeof entry.alloc.file - 1);
+    entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ALLOCATE);
+    entry.alloc.align = cpu_to_le32(alloc_align);
+    entry.alloc.zone = cpu_to_le32(alloc_fseg ?
+                                    BIOS_LINKER_LOADER_ALLOC_ZONE_FSEG :
+                                    BIOS_LINKER_LOADER_ALLOC_ZONE_HIGH);
+
+    /* Alloc entries must come first, so prepend them */
+    g_array_prepend_val(linker, entry);
+}
+
+void bios_linker_loader_add_checksum(GArray *linker, const char *file,
+                                     void *table,
+                                     void *start, unsigned size,
+                                     uint8_t *checksum)
+{
+    BiosLinkerLoaderEntry entry;
+
+    memset(&entry, 0, sizeof entry);
+    strncpy(entry.cksum.file, file, sizeof entry.cksum.file - 1);
+    entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ADD_CHECKSUM);
+    entry.cksum.offset = cpu_to_le32(checksum - (uint8_t *)table);
+    entry.cksum.start = cpu_to_le32((uint8_t *)start - (uint8_t *)table);
+    entry.cksum.length = cpu_to_le32(size);
+
+    g_array_append_val(linker, entry);
+}
+
+void bios_linker_loader_add_pointer(GArray *linker,
+                                    const char *dest_file,
+                                    const char *src_file,
+                                    GArray *table, void *pointer,
+                                    uint8_t pointer_size)
+{
+    BiosLinkerLoaderEntry entry;
+
+    memset(&entry, 0, sizeof entry);
+    strncpy(entry.pointer.dest_file, dest_file,
+            sizeof entry.pointer.dest_file - 1);
+    strncpy(entry.pointer.src_file, src_file,
+            sizeof entry.pointer.src_file - 1);
+    entry.command = cpu_to_le32(BIOS_LINKER_LOADER_COMMAND_ADD_POINTER);
+    entry.pointer.offset = cpu_to_le32((gchar *)pointer - table->data);
+    entry.pointer.size = pointer_size;
+    assert(pointer_size == 1 || pointer_size == 2 ||
+           pointer_size == 4 || pointer_size == 8);
+
+    g_array_append_val(linker, entry);
+}
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index f950707..b9ca380 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -5,6 +5,7 @@ obj-y += pc_sysfw.o
 obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
 
 obj-y += kvmvapic.o
+obj-y += bios-linker-loader.o
 
 iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
     ; then echo "$(2)"; else echo "$(3)"; fi ;)
-- 
MST

[Qemu-devel] [PULL 28/43] loader: allow adding ROMs in done callbacks

[Michael S. Tsirkin]

Don't abort if machine done callbacks add ROMs.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/loader.h | 1 +
 hw/core/loader.c    | 6 +++++-
 vl.c                | 3 +++
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/include/hw/loader.h b/include/hw/loader.h
index e0c576b..58eca98 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -46,6 +46,7 @@ void *rom_add_blob(const char *name, const void *blob, size_t len,
 int rom_add_elf_program(const char *name, void *data, size_t datasize,
                         size_t romsize, hwaddr addr);
 int rom_load_all(void);
+void rom_load_done(void);
 void rom_set_fw(FWCfgState *f);
 int rom_copy(uint8_t *dest, hwaddr addr, size_t size);
 void *rom_ptr(hwaddr addr);
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 060729f..60d2ebd 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -812,10 +812,14 @@ int rom_load_all(void)
         memory_region_unref(section.mr);
     }
     qemu_register_reset(rom_reset, NULL);
-    roms_loaded = 1;
     return 0;
 }
 
+void rom_load_done(void)
+{
+    roms_loaded = 1;
+}
+
 void rom_set_fw(FWCfgState *f)
 {
     fw_cfg = f;
diff --git a/vl.c b/vl.c
index fb8006e..46c29c4 100644
--- a/vl.c
+++ b/vl.c
@@ -4339,6 +4339,9 @@ int main(int argc, char **argv, char **envp)
     qemu_register_reset(qbus_reset_all_fn, sysbus_get_default());
     qemu_run_machine_init_done_notifiers();
 
+    /* Done notifiers can load ROMs */
+    rom_load_done();
+
     qemu_system_reset(VMRESET_SILENT);
     if (loadvm) {
         if (load_vmstate(loadvm) < 0) {
-- 
MST

[Qemu-devel] [PULL 29/43] i386: define pc guest info

[Michael S. Tsirkin]

This defines a structure that will be used to fill in acpi tables
where relevant properties are not yet available using QOM.

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/i386/pc.h |  9 +++++++++
 hw/i386/pc.c         | 21 +++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 9b2ddc4..085a621 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -9,6 +9,9 @@
 #include "hw/i386/ioapic.h"
 
 #include "qemu/range.h"
+#include "qemu/bitmap.h"
+#include "sysemu/sysemu.h"
+#include "hw/pci/pci.h"
 
 /* PC-style peripherals (also used by other machines).  */
 
@@ -20,6 +23,12 @@ typedef struct PcPciInfo {
 struct PcGuestInfo {
     bool has_pci_info;
     bool isapc_ram_fw;
+    hwaddr ram_size;
+    unsigned apic_id_limit;
+    bool apic_xrupt_override;
+    uint64_t numa_nodes;
+    uint64_t *node_mem;
+    uint64_t *node_cpu;
     FWCfgState *fw_cfg;
 };
 
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 0c313fe..d17d1d9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1047,6 +1047,27 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 {
     PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
     PcGuestInfo *guest_info = &guest_info_state->info;
+    int i, j;
+
+    guest_info->ram_size = below_4g_mem_size + above_4g_mem_size;
+    guest_info->apic_id_limit = pc_apic_id_limit(max_cpus);
+    guest_info->apic_xrupt_override = kvm_allows_irq0_override();
+    guest_info->numa_nodes = nb_numa_nodes;
+    guest_info->node_mem = g_memdup(node_mem, guest_info->numa_nodes *
+                                    sizeof *guest_info->node_mem);
+    guest_info->node_cpu = g_malloc0(guest_info->apic_id_limit *
+                                     sizeof *guest_info->node_cpu);
+
+    for (i = 0; i < max_cpus; i++) {
+        unsigned int apic_id = x86_cpu_apic_id_from_index(i);
+        assert(apic_id < guest_info->apic_id_limit);
+        for (j = 0; j < nb_numa_nodes; j++) {
+            if (test_bit(i, node_cpumask[j])) {
+                guest_info->node_cpu[apic_id] = j;
+                break;
+            }
+        }
+    }
 
     guest_info_state->machine_done.notify = pc_guest_info_machine_done;
     qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
-- 
MST

[Qemu-devel] [PULL 30/43] acpi/piix: add macros for acpi property names

[Michael S. Tsirkin]

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/i386/pc.h | 10 ++++++++++
 hw/acpi/piix4.c      |  6 +++---
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 085a621..5aefc5b 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -20,6 +20,16 @@ typedef struct PcPciInfo {
     Range w64;
 } PcPciInfo;
 
+#define ACPI_PM_PROP_S3_DISABLED "disable_s3"
+#define ACPI_PM_PROP_S4_DISABLED "disable_s4"
+#define ACPI_PM_PROP_S4_VAL "s4_val"
+#define ACPI_PM_PROP_SCI_INT "sci_int"
+#define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
+#define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
+#define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
+#define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
+#define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
+
 struct PcGuestInfo {
     bool has_pci_info;
     bool isapc_ram_fw;
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index b46bd5e..4b8c1da 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -489,9 +489,9 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
 static Property piix4_pm_properties[] = {
     DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
-    DEFINE_PROP_UINT8("disable_s3", PIIX4PMState, disable_s3, 0),
-    DEFINE_PROP_UINT8("disable_s4", PIIX4PMState, disable_s4, 0),
-    DEFINE_PROP_UINT8("s4_val", PIIX4PMState, s4_val, 2),
+    DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
+    DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
+    DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
MST

[Qemu-devel] [PULL 31/43] piix: APIs for pc guest info

[Michael S. Tsirkin]

This adds APIs that will be used to fill in guest acpi tables.
Some required information is still lacking in QOM, so we
fall back on lookups by type and returning explicit types.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/acpi/piix4.h |  8 ++++++++
 include/hw/i386/pc.h    |  1 +
 hw/acpi/piix4.c         | 44 ++++++++++++++++++++++++++++++++++++++++----
 hw/pci-host/piix.c      |  8 ++++++++
 4 files changed, 57 insertions(+), 4 deletions(-)
 create mode 100644 include/hw/acpi/piix4.h

diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
new file mode 100644
index 0000000..65e6fd7
--- /dev/null
+++ b/include/hw/acpi/piix4.h
@@ -0,0 +1,8 @@
+#ifndef HW_ACPI_PIIX4_H
+#define HW_ACPI_PIIX4_H
+
+#include "qemu/typedefs.h"
+
+Object *piix4_pm_find(void);
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 5aefc5b..95857be 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -192,6 +192,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
                     MemoryRegion *pci_memory,
                     MemoryRegion *ram_memory);
 
+PCIBus *find_i440fx(void);
 /* piix4.c */
 extern PCIDevice *piix4_dev;
 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 4b8c1da..3bcd890 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -29,6 +29,7 @@
 #include "exec/ioport.h"
 #include "hw/nvram/fw_cfg.h"
 #include "exec/address-spaces.h"
+#include "hw/acpi/piix4.h"
 
 //#define DEBUG
 
@@ -69,6 +70,8 @@ typedef struct PIIX4PMState {
     /*< public >*/
 
     MemoryRegion io;
+    uint32_t io_base;
+
     MemoryRegion io_gpe;
     MemoryRegion io_pci;
     MemoryRegion io_cpu;
@@ -152,14 +155,13 @@ static void apm_ctrl_changed(uint32_t val, void *arg)
 static void pm_io_space_update(PIIX4PMState *s)
 {
     PCIDevice *d = PCI_DEVICE(s);
-    uint32_t pm_io_base;
 
-    pm_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
-    pm_io_base &= 0xffc0;
+    s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
+    s->io_base &= 0xffc0;
 
     memory_region_transaction_begin();
     memory_region_set_enabled(&s->io, d->config[0x80] & 1);
-    memory_region_set_address(&s->io, pm_io_base);
+    memory_region_set_address(&s->io, s->io_base);
     memory_region_transaction_commit();
 }
 
@@ -407,6 +409,28 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
 }
 
+static void piix4_pm_add_propeties(PIIX4PMState *s)
+{
+    static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
+    static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
+    static const uint32_t gpe0_blk = GPE_BASE;
+    static const uint32_t gpe0_blk_len = GPE_LEN;
+    static const uint16_t sci_int = 9;
+
+    object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+                                  &acpi_enable_cmd, NULL);
+    object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+                                  &acpi_disable_cmd, NULL);
+    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
+                                  &gpe0_blk, NULL);
+    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
+                                  &gpe0_blk_len, NULL);
+    object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
+                                  &sci_int, NULL);
+    object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
+                                  &s->io_base, NULL);
+}
+
 static int piix4_pm_initfn(PCIDevice *dev)
 {
     PIIX4PMState *s = PIIX4_PM(dev);
@@ -456,9 +480,21 @@ static int piix4_pm_initfn(PCIDevice *dev)
 
     piix4_acpi_system_hot_add_init(pci_address_space_io(dev), dev->bus, s);
 
+    piix4_pm_add_propeties(s);
     return 0;
 }
 
+Object *piix4_pm_find(void)
+{
+    bool ambig;
+    Object *o = object_resolve_path_type("", TYPE_PIIX4_PM, &ambig);
+
+    if (ambig || !o) {
+        return NULL;
+    }
+    return o;
+}
+
 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
                        qemu_irq sci_irq, qemu_irq smi_irq,
                        int kvm_enabled, FWCfgState *fw_cfg)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index c041149..bad3953 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -416,6 +416,14 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
     return b;
 }
 
+PCIBus *find_i440fx(void)
+{
+    PCIHostState *s = OBJECT_CHECK(PCIHostState,
+                                   object_resolve_path("/machine/i440fx", NULL),
+                                   TYPE_PCI_HOST_BRIDGE);
+    return s ? s->bus : NULL;
+}
+
 /* PIIX3 PCI to ISA bridge */
 static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
 {
-- 
MST

[Qemu-devel] [PULL 32/43] ich9: APIs for pc guest info

[Michael S. Tsirkin]

This adds APIs that will be used to fill in
acpi tables, implemented using QOM,
to various ich9 components.
Some information is still missing in QOM,
so we fall back on lookups by type instead.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/acpi/ich9.h    |  2 ++
 include/hw/i386/ich9.h    |  2 ++
 include/hw/pci-host/q35.h |  2 ++
 hw/acpi/ich9.c            | 24 ++++++++++++++++++++++++
 hw/isa/lpc_ich9.c         | 40 ++++++++++++++++++++++++++++++++++++++++
 hw/pci-host/q35.c         | 10 ++++++++++
 6 files changed, 80 insertions(+)

diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h
index b1fe71f..82fcf9f 100644
--- a/include/hw/acpi/ich9.h
+++ b/include/hw/acpi/ich9.h
@@ -49,4 +49,6 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
 void ich9_pm_iospace_update(ICH9LPCPMRegs *pm, uint32_t pm_io_base);
 extern const VMStateDescription vmstate_ich9_pm;
 
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp);
+
 #endif /* HW_ACPI_ICH9_H */
diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h
index c5f637b..4a68b35 100644
--- a/include/hw/i386/ich9.h
+++ b/include/hw/i386/ich9.h
@@ -66,6 +66,8 @@ typedef struct ICH9LPCState {
     qemu_irq *ioapic;
 } ICH9LPCState;
 
+Object *ich9_lpc_find(void);
+
 #define Q35_MASK(bit, ms_bit, ls_bit) \
 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
 
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 6eb7ab6..f9db770 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -156,4 +156,6 @@ typedef struct Q35PCIHost {
 #define MCH_PCIE_DEV                           1
 #define MCH_PCIE_FUNC                          0
 
+uint64_t mch_mcfg_base(void);
+
 #endif /* HW_Q35_H */
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 3fb443d..7e0429e 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -24,6 +24,7 @@
  * GNU GPL, version 2 or (at your option) any later version.
  */
 #include "hw/hw.h"
+#include "qapi/visitor.h"
 #include "hw/i386/pc.h"
 #include "hw/pci/pci.h"
 #include "qemu/timer.h"
@@ -228,3 +229,26 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm,
     pm->powerdown_notifier.notify = pm_powerdown_req;
     qemu_register_powerdown_notifier(&pm->powerdown_notifier);
 }
+
+static void ich9_pm_get_gpe0_blk(Object *obj, Visitor *v,
+                                 void *opaque, const char *name,
+                                 Error **errp)
+{
+    ICH9LPCPMRegs *pm = opaque;
+    uint32_t value = pm->pm_io_base + ICH9_PMIO_GPE0_STS;
+
+    visit_type_uint32(v, &value, name, errp);
+}
+
+void ich9_pm_add_properties(Object *obj, ICH9LPCPMRegs *pm, Error **errp)
+{
+    static const uint32_t gpe0_len = ICH9_PMIO_GPE0_LEN;
+
+    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_PM_IO_BASE,
+                                   &pm->pm_io_base, errp);
+    object_property_add(obj, ACPI_PM_PROP_GPE0_BLK, "uint32",
+                        ich9_pm_get_gpe0_blk,
+                        NULL, NULL, pm, NULL);
+    object_property_add_uint32_ptr(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
+                                   &gpe0_len, errp);
+}
diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c
index 5633d08..19b2198 100644
--- a/hw/isa/lpc_ich9.c
+++ b/hw/isa/lpc_ich9.c
@@ -29,6 +29,7 @@
  */
 #include "qemu-common.h"
 #include "hw/hw.h"
+#include "qapi/visitor.h"
 #include "qemu/range.h"
 #include "hw/isa/isa.h"
 #include "hw/sysbus.h"
@@ -525,6 +526,43 @@ static const MemoryRegionOps ich9_rst_cnt_ops = {
     .endianness = DEVICE_LITTLE_ENDIAN
 };
 
+Object *ich9_lpc_find(void)
+{
+    bool ambig;
+    Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig);
+
+    if (ambig) {
+        return NULL;
+    }
+    return o;
+}
+
+static void ich9_lpc_get_sci_int(Object *obj, Visitor *v,
+                                 void *opaque, const char *name,
+                                 Error **errp)
+{
+    ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
+    uint32_t value = ich9_lpc_sci_irq(lpc);
+
+    visit_type_uint32(v, &value, name, errp);
+}
+
+static void ich9_lpc_add_properties(ICH9LPCState *lpc)
+{
+    static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
+    static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
+
+    object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32",
+                        ich9_lpc_get_sci_int,
+                        NULL, NULL, NULL, NULL);
+    object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
+                                  &acpi_enable_cmd, NULL);
+    object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
+                                  &acpi_disable_cmd, NULL);
+
+    ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL);
+}
+
 static int ich9_lpc_initfn(PCIDevice *d)
 {
     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
@@ -552,6 +590,8 @@ static int ich9_lpc_initfn(PCIDevice *d)
                                         ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
                                         1);
 
+    ich9_lpc_add_properties(lpc);
+
     return 0;
 }
 
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index a051b58..50063f8 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -389,6 +389,16 @@ static int mch_init(PCIDevice *d)
     return 0;
 }
 
+uint64_t mch_mcfg_base(void)
+{
+    bool ambiguous;
+    Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous);
+    if (!o) {
+        return 0;
+    }
+    return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT;
+}
+
 static void mch_class_init(ObjectClass *klass, void *data)
 {
     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-- 
MST

[Qemu-devel] [PULL 33/43] pvpanic: add API to access io port

[Michael S. Tsirkin]

Add API to find pvpanic device and get its io port.
Will be used to fill in guest info structure.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/i386/pc.h |  1 +
 hw/misc/pvpanic.c    | 13 ++++++++++++-
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 95857be..e3ee0a8 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -235,6 +235,7 @@ void pc_system_firmware_init(MemoryRegion *rom_memory,
 
 /* pvpanic.c */
 void pvpanic_init(ISABus *bus);
+uint16_t pvpanic_port(void);
 
 /* e820 types */
 #define E820_RAM        1
diff --git a/hw/misc/pvpanic.c b/hw/misc/pvpanic.c
index b64e3bb..226e298 100644
--- a/hw/misc/pvpanic.c
+++ b/hw/misc/pvpanic.c
@@ -117,8 +117,19 @@ void pvpanic_init(ISABus *bus)
     isa_create_simple(bus, TYPE_ISA_PVPANIC_DEVICE);
 }
 
+#define PVPANIC_IOPORT_PROP "ioport"
+
+uint16_t pvpanic_port(void)
+{
+    Object *o = object_resolve_path_type("", TYPE_ISA_PVPANIC_DEVICE, NULL);
+    if (!o) {
+        return 0;
+    }
+    return object_property_get_int(o, PVPANIC_IOPORT_PROP, NULL);
+}
+
 static Property pvpanic_isa_properties[] = {
-    DEFINE_PROP_UINT16("ioport", PVPanicState, ioport, 0x505),
+    DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicState, ioport, 0x505),
     DEFINE_PROP_END_OF_LIST(),
 };
 
-- 
MST

[Qemu-devel] [PULL 34/43] hpet: add API to find it

[Michael S. Tsirkin]

Add API to find HPET using QOM.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/timer/hpet.h | 2 ++
 hw/timer/hpet.c         | 5 +++++
 2 files changed, 7 insertions(+)

diff --git a/include/hw/timer/hpet.h b/include/hw/timer/hpet.h
index 757f79f..ab44bd3 100644
--- a/include/hw/timer/hpet.h
+++ b/include/hw/timer/hpet.h
@@ -71,4 +71,6 @@ struct hpet_fw_config
 } QEMU_PACKED;
 
 extern struct hpet_fw_config hpet_cfg;
+
+bool hpet_find(void);
 #endif
diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c
index fcd22ae..2eb75ea 100644
--- a/hw/timer/hpet.c
+++ b/hw/timer/hpet.c
@@ -757,6 +757,11 @@ static void hpet_device_class_init(ObjectClass *klass, void *data)
     dc->props = hpet_device_properties;
 }
 
+bool hpet_find(void)
+{
+    return object_resolve_path_type("", TYPE_HPET, NULL);
+}
+
 static const TypeInfo hpet_device_info = {
     .name          = TYPE_HPET,
     .parent        = TYPE_SYS_BUS_DEVICE,
-- 
MST

[Qemu-devel] [PULL 35/43] acpi: add interface to access user-installed tables

[Michael S. Tsirkin]

Also add a new API to install builtin tables, so
that we can distinguish between the two.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/acpi/acpi.h |  4 ++++
 hw/acpi/core.c         | 40 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h
index 51733d3..6bbcb17 100644
--- a/include/hw/acpi/acpi.h
+++ b/include/hw/acpi/acpi.h
@@ -165,6 +165,10 @@ extern int acpi_enabled;
 extern char unsigned *acpi_tables;
 extern size_t acpi_tables_len;
 
+uint8_t *acpi_table_first(void);
+uint8_t *acpi_table_next(uint8_t *current);
+unsigned acpi_table_len(void *current);
 void acpi_table_add(const QemuOpts *opts, Error **errp);
+void acpi_table_add_builtin(const QemuOpts *opts, Error **errp);
 
 #endif /* !QEMU_HW_ACPI_H */
diff --git a/hw/acpi/core.c b/hw/acpi/core.c
index 7467b88..4d25d8e 100644
--- a/hw/acpi/core.c
+++ b/hw/acpi/core.c
@@ -309,6 +309,46 @@ out:
     error_propagate(errp, err);
 }
 
+static bool acpi_table_builtin = false;
+
+void acpi_table_add_builtin(const QemuOpts *opts, Error **errp)
+{
+    acpi_table_builtin = true;
+    acpi_table_add(opts, errp);
+}
+
+unsigned acpi_table_len(void *current)
+{
+    struct acpi_table_header *hdr = current - sizeof(hdr->_length);
+    return hdr->_length;
+}
+
+static
+void *acpi_table_hdr(void *h)
+{
+    struct acpi_table_header *hdr = h;
+    return &hdr->sig;
+}
+
+uint8_t *acpi_table_first(void)
+{
+    if (acpi_table_builtin || !acpi_tables) {
+        return NULL;
+    }
+    return acpi_table_hdr(acpi_tables + ACPI_TABLE_PFX_SIZE);
+}
+
+uint8_t *acpi_table_next(uint8_t *current)
+{
+    uint8_t *next = current + acpi_table_len(current);
+
+    if (next - acpi_tables >= acpi_tables_len) {
+        return NULL;
+    } else {
+        return acpi_table_hdr(next);
+    }
+}
+
 static void acpi_notify_wakeup(Notifier *notifier, void *data)
 {
     ACPIREGS *ar = container_of(notifier, ACPIREGS, wakeup);
-- 
MST

[Qemu-devel] [PULL 36/43] pc: use new api to add builtin tables

[Michael S. Tsirkin]

At this point the only builtin table we have is
the DSDT used for Q35.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/pc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index d17d1d9..f8a3f0b 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1114,7 +1114,7 @@ void pc_acpi_init(const char *default_dsdt)
         opts = qemu_opts_parse(qemu_find_opts("acpi"), arg, 0);
         g_assert(opts != NULL);
 
-        acpi_table_add(opts, &err);
+        acpi_table_add_builtin(opts, &err);
         if (err) {
             error_report("WARNING: failed to load %s: %s", filename,
                          error_get_pretty(err));
-- 
MST

[Qemu-devel] [PULL 37/43] i386: ACPI table generation code from seabios

[Michael S. Tsirkin]

This adds C code for generating ACPI tables at runtime,
imported from seabios git tree
    commit 51684b7ced75fb76776e8ee84833fcfb6ecf12dd

Although ACPI tables come from a system BIOS on real hw,
it makes sense that the ACPI tables are coupled with the
virtual machine, since they have to abstract the x86 machine to
the OS's.

This is widely desired as a way to avoid the churn
and proliferation of QEMU-specific interfaces
associated with ACPI tables in bios code.

Notes:
As BIOS can reprogram devices prior to loading
ACPI tables, we pre-format ACPI tables but defer loading
hardware configuration there until tables are loaded.

The code structure was intentionally kept as close
to the seabios original as possible, to simplify
comparison and making sure we didn't lose anything
in translation.

Minor code duplication results, to help ensure there are no functional
regressions, I think it's better to merge it like this and do more code
changes in follow-up patches.

Cross-version compatibility concerns have been addressed:
    ACPI tables are exposed to guest as FW_CFG entries.
    When running with -M 1.5 and older, this patch disables ACPI
    table generation, and doesn't expose ACPI
    tables to guest.

    As table content is likely to change over time,
    the following measures are taken to simplify
    cross-version migration:
    - All tables besides the RSDP are packed in a single FW CFG entry.
      This entry size is currently 23K. We round it up to 64K
      to avoid too much churn there.
    - Tables are placed in special ROM blob (not mapped into guest memory)
      which is automatically migrated together with the guest, same
      as BIOS code.
    - Offsets where hardware configuration is loaded in ACPI tables
      are also migrated, this is in case future ACPI changes make us
      rearrange the tables in memory.

This patch reuses some code from SeaBIOS, which was originally under
LGPLv2 and then relicensed to GPLv3 or LGPLv3, in QEMU under GPLv2+. This
relicensing has been acked by all contributors that had contributed to the
code since the v2->v3 relicense. ACKs approving the v2+ relicensing are
listed below. The list might include ACKs from people not holding
copyright on any parts of the reused code, but it's better to err on the
side of caution and include them.

Affected SeaBIOS files (GPLv2+ license headers added)
<http://thread.gmane.org/gmane.comp.bios.coreboot.seabios/5949>:

 src/acpi-dsdt-cpu-hotplug.dsl
 src/acpi-dsdt-dbug.dsl
 src/acpi-dsdt-hpet.dsl
 src/acpi-dsdt-isa.dsl
 src/acpi-dsdt-pci-crs.dsl
 src/acpi.c
 src/acpi.h
 src/ssdt-misc.dsl
 src/ssdt-pcihp.dsl
 src/ssdt-proc.dsl
 tools/acpi_extract.py
 tools/acpi_extract_preprocess.py

Each one of the listed people agreed to the following:

> If you allow the use of your contribution in QEMU under the
> terms of GPLv2 or later as proposed by this patch,
> please respond to this mail including the line:
>
> Acked-by: Name <email address>

  Acked-by: Gerd Hoffmann <kraxel@redhat.com>
  Acked-by: Jan Kiszka <jan.kiszka@siemens.com>
  Acked-by: Jason Baron <jbaron@akamai.com>
  Acked-by: David Woodhouse <David.Woodhouse@intel.com>
  Acked-by: Gleb Natapov <gleb@redhat.com>
  Acked-by: Marcelo Tosatti <mtosatti@redhat.com>
  Acked-by: Dave Frodin <dave.frodin@se-eng.com>
  Acked-by: Paolo Bonzini <pbonzini@redhat.com>
  Acked-by: Kevin O'Connor <kevin@koconnor.net>
  Acked-by: Laszlo Ersek <lersek@redhat.com>
  Acked-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
  Acked-by: Isaku Yamahata <yamahata@valinux.co.jp>
  Acked-by: Magnus Christensson <magnus.christensson@intel.com>
  Acked-by: Hu Tao <hutao@cn.fujitsu.com>
  Acked-by: Eduardo Habkost <ehabkost@redhat.com>

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/acpi-build.h  |    9 +
 hw/i386/acpi-defs.h   |  331 ++++++++++++++
 include/hw/i386/pc.h  |    1 +
 hw/i386/acpi-build.c  | 1214 +++++++++++++++++++++++++++++++++++++++++++++++++
 hw/i386/pc.c          |    2 +
 hw/i386/pc_piix.c     |    5 +
 hw/i386/pc_q35.c      |    3 +
 hw/i386/Makefile.objs |    4 +
 8 files changed, 1569 insertions(+)
 create mode 100644 hw/i386/acpi-build.h
 create mode 100644 hw/i386/acpi-defs.h
 create mode 100644 hw/i386/acpi-build.c

diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h
new file mode 100644
index 0000000..e57b1aa
--- /dev/null
+++ b/hw/i386/acpi-build.h
@@ -0,0 +1,9 @@
+
+#ifndef HW_I386_ACPI_BUILD_H
+#define HW_I386_ACPI_BUILD_H
+
+#include "qemu/typedefs.h"
+
+void acpi_setup(PcGuestInfo *);
+
+#endif
diff --git a/hw/i386/acpi-defs.h b/hw/i386/acpi-defs.h
new file mode 100644
index 0000000..78ca204
--- /dev/null
+++ b/hw/i386/acpi-defs.h
@@ -0,0 +1,331 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef QEMU_ACPI_DEFS_H
+#define QEMU_ACPI_DEFS_H
+
+enum {
+    ACPI_FADT_F_WBINVD,
+    ACPI_FADT_F_WBINVD_FLUSH,
+    ACPI_FADT_F_PROC_C1,
+    ACPI_FADT_F_P_LVL2_UP,
+    ACPI_FADT_F_PWR_BUTTON,
+    ACPI_FADT_F_SLP_BUTTON,
+    ACPI_FADT_F_FIX_RTC,
+    ACPI_FADT_F_RTC_S4,
+    ACPI_FADT_F_TMR_VAL_EXT,
+    ACPI_FADT_F_DCK_CAP,
+    ACPI_FADT_F_RESET_REG_SUP,
+    ACPI_FADT_F_SEALED_CASE,
+    ACPI_FADT_F_HEADLESS,
+    ACPI_FADT_F_CPU_SW_SLP,
+    ACPI_FADT_F_PCI_EXP_WAK,
+    ACPI_FADT_F_USE_PLATFORM_CLOCK,
+    ACPI_FADT_F_S4_RTC_STS_VALID,
+    ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE,
+    ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL,
+    ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE,
+    ACPI_FADT_F_HW_REDUCED_ACPI,
+    ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE,
+};
+
+/*
+ * ACPI 2.0 Generic Address Space definition.
+ */
+struct Acpi20GenericAddress {
+    uint8_t  address_space_id;
+    uint8_t  register_bit_width;
+    uint8_t  register_bit_offset;
+    uint8_t  reserved;
+    uint64_t address;
+} QEMU_PACKED;
+typedef struct Acpi20GenericAddress Acpi20GenericAddress;
+
+#define ACPI_RSDP_SIGNATURE 0x2052545020445352LL // "RSD PTR "
+
+struct AcpiRsdpDescriptor {        /* Root System Descriptor Pointer */
+    uint64_t signature;              /* ACPI signature, contains "RSD PTR " */
+    uint8_t  checksum;               /* To make sum of struct == 0 */
+    uint8_t  oem_id [6];             /* OEM identification */
+    uint8_t  revision;               /* Must be 0 for 1.0, 2 for 2.0 */
+    uint32_t rsdt_physical_address;  /* 32-bit physical address of RSDT */
+    uint32_t length;                 /* XSDT Length in bytes including hdr */
+    uint64_t xsdt_physical_address;  /* 64-bit physical address of XSDT */
+    uint8_t  extended_checksum;      /* Checksum of entire table */
+    uint8_t  reserved [3];           /* Reserved field must be 0 */
+} QEMU_PACKED;
+typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor;
+
+/* Table structure from Linux kernel (the ACPI tables are under the
+   BSD license) */
+
+
+#define ACPI_TABLE_HEADER_DEF   /* ACPI common table header */ \
+    uint32_t signature;          /* ACPI signature (4 ASCII characters) */ \
+    uint32_t length;                 /* Length of table, in bytes, including header */ \
+    uint8_t  revision;               /* ACPI Specification minor version # */ \
+    uint8_t  checksum;               /* To make sum of entire table == 0 */ \
+    uint8_t  oem_id [6];             /* OEM identification */ \
+    uint8_t  oem_table_id [8];       /* OEM table identification */ \
+    uint32_t oem_revision;           /* OEM revision number */ \
+    uint8_t  asl_compiler_id [4];    /* ASL compiler vendor ID */ \
+    uint32_t asl_compiler_revision;  /* ASL compiler revision number */
+
+
+struct AcpiTableHeader         /* ACPI common table header */
+{
+    ACPI_TABLE_HEADER_DEF
+} QEMU_PACKED;
+typedef struct AcpiTableHeader AcpiTableHeader;
+
+/*
+ * ACPI 1.0 Fixed ACPI Description Table (FADT)
+ */
+#define ACPI_FACP_SIGNATURE 0x50434146 // FACP
+struct AcpiFadtDescriptorRev1
+{
+    ACPI_TABLE_HEADER_DEF     /* ACPI common table header */
+    uint32_t firmware_ctrl;          /* Physical address of FACS */
+    uint32_t dsdt;                   /* Physical address of DSDT */
+    uint8_t  model;                  /* System Interrupt Model */
+    uint8_t  reserved1;              /* Reserved */
+    uint16_t sci_int;                /* System vector of SCI interrupt */
+    uint32_t smi_cmd;                /* Port address of SMI command port */
+    uint8_t  acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+    uint8_t  acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
+    uint8_t  S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
+    uint8_t  reserved2;              /* Reserved - must be zero */
+    uint32_t pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
+    uint32_t pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
+    uint32_t pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
+    uint32_t pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
+    uint32_t pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
+    uint32_t pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
+    uint32_t gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
+    uint32_t gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
+    uint8_t  pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
+    uint8_t  pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
+    uint8_t  pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
+    uint8_t  pm_tmr_len;             /* Byte Length of ports at pm_tm_blk */
+    uint8_t  gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
+    uint8_t  gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
+    uint8_t  gpe1_base;              /* Offset in gpe model where gpe1 events start */
+    uint8_t  reserved3;              /* Reserved */
+    uint16_t plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+    uint16_t plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
+    uint16_t flush_size;             /* Size of area read to flush caches */
+    uint16_t flush_stride;           /* Stride used in flushing caches */
+    uint8_t  duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+    uint8_t  duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+    uint8_t  day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+    uint8_t  mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+    uint8_t  century;                /* Index to century in RTC CMOS RAM */
+    uint8_t  reserved4;              /* Reserved */
+    uint8_t  reserved4a;             /* Reserved */
+    uint8_t  reserved4b;             /* Reserved */
+    uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Root System Description Table (RSDT)
+ */
+#define ACPI_RSDT_SIGNATURE 0x54445352 // RSDT
+struct AcpiRsdtDescriptorRev1
+{
+    ACPI_TABLE_HEADER_DEF       /* ACPI common table header */
+    uint32_t table_offset_entry[0];  /* Array of pointers to other */
+    /* ACPI tables */
+} QEMU_PACKED;
+typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1;
+
+/*
+ * ACPI 1.0 Firmware ACPI Control Structure (FACS)
+ */
+#define ACPI_FACS_SIGNATURE 0x53434146 // FACS
+struct AcpiFacsDescriptorRev1
+{
+    uint32_t signature;           /* ACPI Signature */
+    uint32_t length;                 /* Length of structure, in bytes */
+    uint32_t hardware_signature;     /* Hardware configuration signature */
+    uint32_t firmware_waking_vector; /* ACPI OS waking vector */
+    uint32_t global_lock;            /* Global Lock */
+    uint32_t flags;
+    uint8_t  resverved3 [40];        /* Reserved - must be zero */
+} QEMU_PACKED;
+typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1;
+
+/*
+ * Differentiated System Description Table (DSDT)
+ */
+#define ACPI_DSDT_SIGNATURE 0x54445344 // DSDT
+
+/*
+ * MADT values and structures
+ */
+
+/* Values for MADT PCATCompat */
+
+#define ACPI_DUAL_PIC                0
+#define ACPI_MULTIPLE_APIC           1
+
+/* Master MADT */
+
+#define ACPI_APIC_SIGNATURE 0x43495041 // APIC
+struct AcpiMultipleApicTable
+{
+    ACPI_TABLE_HEADER_DEF     /* ACPI common table header */
+    uint32_t local_apic_address;     /* Physical address of local APIC */
+    uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMultipleApicTable AcpiMultipleApicTable;
+
+/* Values for Type in APIC sub-headers */
+
+#define ACPI_APIC_PROCESSOR          0
+#define ACPI_APIC_IO                 1
+#define ACPI_APIC_XRUPT_OVERRIDE     2
+#define ACPI_APIC_NMI                3
+#define ACPI_APIC_LOCAL_NMI          4
+#define ACPI_APIC_ADDRESS_OVERRIDE   5
+#define ACPI_APIC_IO_SAPIC           6
+#define ACPI_APIC_LOCAL_SAPIC        7
+#define ACPI_APIC_XRUPT_SOURCE       8
+#define ACPI_APIC_RESERVED           9           /* 9 and greater are reserved */
+
+/*
+ * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
+ */
+#define ACPI_SUB_HEADER_DEF   /* Common ACPI sub-structure header */\
+    uint8_t  type;                               \
+    uint8_t  length;
+
+/* Sub-structures for MADT */
+
+struct AcpiMadtProcessorApic
+{
+    ACPI_SUB_HEADER_DEF
+    uint8_t  processor_id;           /* ACPI processor id */
+    uint8_t  local_apic_id;          /* Processor's local APIC id */
+    uint32_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic;
+
+struct AcpiMadtIoApic
+{
+    ACPI_SUB_HEADER_DEF
+    uint8_t  io_apic_id;             /* I/O APIC ID */
+    uint8_t  reserved;               /* Reserved - must be zero */
+    uint32_t address;                /* APIC physical address */
+    uint32_t interrupt;              /* Global system interrupt where INTI
+                                 * lines start */
+} QEMU_PACKED;
+typedef struct AcpiMadtIoApic AcpiMadtIoApic;
+
+struct AcpiMadtIntsrcovr {
+    ACPI_SUB_HEADER_DEF
+    uint8_t  bus;
+    uint8_t  source;
+    uint32_t gsi;
+    uint16_t flags;
+} QEMU_PACKED;
+typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr;
+
+struct AcpiMadtLocalNmi {
+    ACPI_SUB_HEADER_DEF
+    uint8_t  processor_id;           /* ACPI processor id */
+    uint16_t flags;                  /* MPS INTI flags */
+    uint8_t  lint;                   /* Local APIC LINT# */
+} QEMU_PACKED;
+typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi;
+
+/*
+ * HPET Description Table
+ */
+#define ACPI_HPET_SIGNATURE 0x54455048 // HPET
+struct Acpi20Hpet {
+    ACPI_TABLE_HEADER_DEF                    /* ACPI common table header */
+    uint32_t           timer_block_id;
+    Acpi20GenericAddress addr;
+    uint8_t            hpet_number;
+    uint16_t           min_tick;
+    uint8_t            page_protect;
+} QEMU_PACKED;
+typedef struct Acpi20Hpet Acpi20Hpet;
+
+/*
+ * SRAT (NUMA topology description) table
+ */
+
+#define ACPI_SRAT_SIGNATURE 0x54415253 // SRAT
+struct AcpiSystemResourceAffinityTable
+{
+    ACPI_TABLE_HEADER_DEF
+    uint32_t    reserved1;
+    uint32_t    reserved2[2];
+} QEMU_PACKED;
+typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable;
+
+#define ACPI_SRAT_PROCESSOR          0
+#define ACPI_SRAT_MEMORY             1
+
+struct AcpiSratProcessorAffinity
+{
+    ACPI_SUB_HEADER_DEF
+    uint8_t     proximity_lo;
+    uint8_t     local_apic_id;
+    uint32_t    flags;
+    uint8_t     local_sapic_eid;
+    uint8_t     proximity_hi[3];
+    uint32_t    reserved;
+} QEMU_PACKED;
+typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity;
+
+struct AcpiSratMemoryAffinity
+{
+    ACPI_SUB_HEADER_DEF
+    uint8_t     proximity[4];
+    uint16_t    reserved1;
+    uint64_t    base_addr;
+    uint64_t    range_length;
+    uint32_t    reserved2;
+    uint32_t    flags;
+    uint32_t    reserved3[2];
+} QEMU_PACKED;
+typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity;
+
+/* PCI fw r3.0 MCFG table. */
+/* Subtable */
+struct AcpiMcfgAllocation {
+    uint64_t address;                /* Base address, processor-relative */
+    uint16_t pci_segment;            /* PCI segment group number */
+    uint8_t start_bus_number;       /* Starting PCI Bus number */
+    uint8_t end_bus_number;         /* Final PCI Bus number */
+    uint32_t reserved;
+} QEMU_PACKED;
+typedef struct AcpiMcfgAllocation AcpiMcfgAllocation;
+
+#define ACPI_MCFG_SIGNATURE 0x4746434d       // MCFG
+
+/* Reserved signature: ignored by OSPM */
+#define ACPI_RSRV_SIGNATURE 0x554d4551       // QEMU
+
+struct AcpiTableMcfg {
+    ACPI_TABLE_HEADER_DEF;
+    uint8_t reserved[8];
+    AcpiMcfgAllocation allocation[0];
+} QEMU_PACKED;
+typedef struct AcpiTableMcfg AcpiTableMcfg;
+
+#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index e3ee0a8..39db8cb 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -40,6 +40,7 @@ struct PcGuestInfo {
     uint64_t *node_mem;
     uint64_t *node_cpu;
     FWCfgState *fw_cfg;
+    bool has_acpi_build;
 };
 
 /* parallel.c */
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
new file mode 100644
index 0000000..6cfa044
--- /dev/null
+++ b/hw/i386/acpi-build.c
@@ -0,0 +1,1214 @@
+/* Support for generating ACPI tables and passing them to Guests
+ *
+ * Copyright (C) 2008-2010  Kevin O'Connor <kevin@koconnor.net>
+ * Copyright (C) 2006 Fabrice Bellard
+ * Copyright (C) 2013 Red Hat Inc
+ *
+ * Author: Michael S. Tsirkin <mst@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "acpi-build.h"
+#include <stddef.h>
+#include <glib.h>
+#include "qemu-common.h"
+#include "qemu/bitmap.h"
+#include "qemu/range.h"
+#include "hw/pci/pci.h"
+#include "qom/cpu.h"
+#include "hw/i386/pc.h"
+#include "target-i386/cpu.h"
+#include "hw/timer/hpet.h"
+#include "hw/i386/acpi-defs.h"
+#include "hw/acpi/acpi.h"
+#include "hw/nvram/fw_cfg.h"
+#include "bios-linker-loader.h"
+#include "hw/loader.h"
+
+/* Supported chipsets: */
+#include "hw/acpi/piix4.h"
+#include "hw/i386/ich9.h"
+#include "hw/pci/pci_bus.h"
+#include "hw/pci-host/q35.h"
+
+#include "hw/i386/q35-acpi-dsdt.hex"
+#include "hw/i386/acpi-dsdt.hex"
+
+#include "qapi/qmp/qint.h"
+#include "qom/qom-qobject.h"
+
+typedef struct AcpiCpuInfo {
+    DECLARE_BITMAP(found_cpus, MAX_CPUMASK_BITS + 1);
+} AcpiCpuInfo;
+
+typedef struct AcpiMcfgInfo {
+    uint64_t mcfg_base;
+    uint32_t mcfg_size;
+} AcpiMcfgInfo;
+
+typedef struct AcpiPmInfo {
+    bool s3_disabled;
+    bool s4_disabled;
+    uint8_t s4_val;
+    uint16_t sci_int;
+    uint8_t acpi_enable_cmd;
+    uint8_t acpi_disable_cmd;
+    uint32_t gpe0_blk;
+    uint32_t gpe0_blk_len;
+    uint32_t io_base;
+} AcpiPmInfo;
+
+typedef struct AcpiMiscInfo {
+    bool has_hpet;
+    DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
+    const unsigned char *dsdt_code;
+    unsigned dsdt_size;
+    uint16_t pvpanic_port;
+} AcpiMiscInfo;
+
+static void acpi_get_dsdt(AcpiMiscInfo *info)
+{
+    Object *piix = piix4_pm_find();
+    Object *lpc = ich9_lpc_find();
+    assert(!!piix != !!lpc);
+
+    if (piix) {
+        info->dsdt_code = AcpiDsdtAmlCode;
+        info->dsdt_size = sizeof AcpiDsdtAmlCode;
+    }
+    if (lpc) {
+        info->dsdt_code = Q35AcpiDsdtAmlCode;
+        info->dsdt_size = sizeof Q35AcpiDsdtAmlCode;
+    }
+}
+
+static
+int acpi_add_cpu_info(Object *o, void *opaque)
+{
+    AcpiCpuInfo *cpu = opaque;
+    uint64_t apic_id;
+
+    if (object_dynamic_cast(o, TYPE_CPU)) {
+        apic_id = object_property_get_int(o, "apic-id", NULL);
+        assert(apic_id <= MAX_CPUMASK_BITS);
+
+        set_bit(apic_id, cpu->found_cpus);
+    }
+
+    object_child_foreach(o, acpi_add_cpu_info, opaque);
+    return 0;
+}
+
+static void acpi_get_cpu_info(AcpiCpuInfo *cpu)
+{
+    Object *root = object_get_root();
+
+    memset(cpu->found_cpus, 0, sizeof cpu->found_cpus);
+    object_child_foreach(root, acpi_add_cpu_info, cpu);
+}
+
+static void acpi_get_pm_info(AcpiPmInfo *pm)
+{
+    Object *piix = piix4_pm_find();
+    Object *lpc = ich9_lpc_find();
+    Object *obj = NULL;
+    QObject *o;
+
+    if (piix) {
+        obj = piix;
+    }
+    if (lpc) {
+        obj = lpc;
+    }
+    assert(obj);
+
+    /* Fill in optional s3/s4 related properties */
+    o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
+    if (o) {
+        pm->s3_disabled = qint_get_int(qobject_to_qint(o));
+    } else {
+        pm->s3_disabled = false;
+    }
+    o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_DISABLED, NULL);
+    if (o) {
+        pm->s4_disabled = qint_get_int(qobject_to_qint(o));
+    } else {
+        pm->s4_disabled = false;
+    }
+    o = object_property_get_qobject(obj, ACPI_PM_PROP_S4_VAL, NULL);
+    if (o) {
+        pm->s4_val = qint_get_int(qobject_to_qint(o));
+    } else {
+        pm->s4_val = false;
+    }
+
+    /* Fill in mandatory properties */
+    pm->sci_int = object_property_get_int(obj, ACPI_PM_PROP_SCI_INT, NULL);
+
+    pm->acpi_enable_cmd = object_property_get_int(obj,
+                                                  ACPI_PM_PROP_ACPI_ENABLE_CMD,
+                                                  NULL);
+    pm->acpi_disable_cmd = object_property_get_int(obj,
+                                                  ACPI_PM_PROP_ACPI_DISABLE_CMD,
+                                                  NULL);
+    pm->io_base = object_property_get_int(obj, ACPI_PM_PROP_PM_IO_BASE,
+                                          NULL);
+    pm->gpe0_blk = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK,
+                                           NULL);
+    pm->gpe0_blk_len = object_property_get_int(obj, ACPI_PM_PROP_GPE0_BLK_LEN,
+                                               NULL);
+}
+
+static void acpi_get_hotplug_info(AcpiMiscInfo *misc)
+{
+    int i;
+    PCIBus *bus = find_i440fx();
+
+    if (!bus) {
+        /* Only PIIX supports ACPI hotplug */
+        memset(misc->slot_hotplug_enable, 0, sizeof misc->slot_hotplug_enable);
+        return;
+    }
+
+    memset(misc->slot_hotplug_enable, 0xff,
+           DIV_ROUND_UP(PCI_SLOT_MAX, BITS_PER_BYTE));
+
+    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
+        PCIDeviceClass *pc;
+        PCIDevice *pdev = bus->devices[i];
+
+        if (!pdev) {
+            continue;
+        }
+
+        pc = PCI_DEVICE_GET_CLASS(pdev);
+
+        if (pc->no_hotplug) {
+            int slot = PCI_SLOT(i);
+
+            clear_bit(slot, misc->slot_hotplug_enable);
+        }
+    }
+}
+
+static void acpi_get_misc_info(AcpiMiscInfo *info)
+{
+    info->has_hpet = hpet_find();
+    info->pvpanic_port = pvpanic_port();
+}
+
+static void acpi_get_pci_info(PcPciInfo *info)
+{
+    Object *pci_host;
+    bool ambiguous;
+
+    pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
+    g_assert(!ambiguous);
+    g_assert(pci_host);
+
+    info->w32.begin = object_property_get_int(pci_host,
+                                              PCI_HOST_PROP_PCI_HOLE_START,
+                                              NULL);
+    info->w32.end = object_property_get_int(pci_host,
+                                            PCI_HOST_PROP_PCI_HOLE_END,
+                                            NULL);
+    info->w64.begin = object_property_get_int(pci_host,
+                                              PCI_HOST_PROP_PCI_HOLE64_START,
+                                              NULL);
+    info->w64.end = object_property_get_int(pci_host,
+                                            PCI_HOST_PROP_PCI_HOLE64_END,
+                                            NULL);
+}
+
+#define ACPI_BUILD_APPNAME  "Bochs"
+#define ACPI_BUILD_APPNAME6 "BOCHS "
+#define ACPI_BUILD_APPNAME4 "BXPC"
+
+#define ACPI_BUILD_DPRINTF(level, fmt, ...) do {} while (0)
+
+#define ACPI_BUILD_TABLE_FILE "etc/acpi/tables"
+#define ACPI_BUILD_RSDP_FILE "etc/acpi/rsdp"
+
+static void
+build_header(GArray *linker, GArray *table_data,
+             AcpiTableHeader *h, uint32_t sig, int len, uint8_t rev)
+{
+    h->signature = cpu_to_le32(sig);
+    h->length = cpu_to_le32(len);
+    h->revision = rev;
+    memcpy(h->oem_id, ACPI_BUILD_APPNAME6, 6);
+    memcpy(h->oem_table_id, ACPI_BUILD_APPNAME4, 4);
+    memcpy(h->oem_table_id + 4, (void *)&sig, 4);
+    h->oem_revision = cpu_to_le32(1);
+    memcpy(h->asl_compiler_id, ACPI_BUILD_APPNAME4, 4);
+    h->asl_compiler_revision = cpu_to_le32(1);
+    h->checksum = 0;
+    /* Checksum to be filled in by Guest linker */
+    bios_linker_loader_add_checksum(linker, ACPI_BUILD_TABLE_FILE,
+                                    table_data->data, h, len, &h->checksum);
+}
+
+static inline GArray *build_alloc_array(void)
+{
+        return g_array_new(false, true /* clear */, 1);
+}
+
+static inline void build_free_array(GArray *array)
+{
+        g_array_free(array, true);
+}
+
+static inline void build_prepend_byte(GArray *array, uint8_t val)
+{
+    g_array_prepend_val(array, val);
+}
+
+static inline void build_append_byte(GArray *array, uint8_t val)
+{
+    g_array_append_val(array, val);
+}
+
+static inline void build_append_array(GArray *array, GArray *val)
+{
+    g_array_append_vals(array, val->data, val->len);
+}
+
+static void build_append_nameseg(GArray *array, const char *format, ...)
+{
+    GString *s = g_string_new("");
+    va_list args;
+
+    va_start(args, format);
+    g_string_vprintf(s, format, args);
+    va_end(args);
+
+    assert(s->len == 4);
+    g_array_append_vals(array, s->str, s->len);
+    g_string_free(s, true);
+}
+
+/* 5.4 Definition Block Encoding */
+enum {
+    PACKAGE_LENGTH_1BYTE_SHIFT = 6, /* Up to 63 - use extra 2 bits. */
+    PACKAGE_LENGTH_2BYTE_SHIFT = 4,
+    PACKAGE_LENGTH_3BYTE_SHIFT = 12,
+    PACKAGE_LENGTH_4BYTE_SHIFT = 20,
+};
+
+static void build_prepend_package_length(GArray *package, unsigned min_bytes)
+{
+    uint8_t byte;
+    unsigned length = package->len;
+    unsigned length_bytes;
+
+    if (length + 1 < (1 << PACKAGE_LENGTH_1BYTE_SHIFT)) {
+        length_bytes = 1;
+    } else if (length + 2 < (1 << PACKAGE_LENGTH_3BYTE_SHIFT)) {
+        length_bytes = 2;
+    } else if (length + 3 < (1 << PACKAGE_LENGTH_4BYTE_SHIFT)) {
+        length_bytes = 3;
+    } else {
+        length_bytes = 4;
+    }
+
+    /* Force length to at least min_bytes.
+     * This wastes memory but that's how bios did it.
+     */
+    length_bytes = MAX(length_bytes, min_bytes);
+
+    /* PkgLength is the length of the inclusive length of the data. */
+    length += length_bytes;
+
+    switch (length_bytes) {
+    case 1:
+        byte = length;
+        build_prepend_byte(package, byte);
+        return;
+    case 4:
+        byte = length >> PACKAGE_LENGTH_4BYTE_SHIFT;
+        build_prepend_byte(package, byte);
+        length &= (1 << PACKAGE_LENGTH_4BYTE_SHIFT) - 1;
+        /* fall through */
+    case 3:
+        byte = length >> PACKAGE_LENGTH_3BYTE_SHIFT;
+        build_prepend_byte(package, byte);
+        length &= (1 << PACKAGE_LENGTH_3BYTE_SHIFT) - 1;
+        /* fall through */
+    case 2:
+        byte = length >> PACKAGE_LENGTH_2BYTE_SHIFT;
+        build_prepend_byte(package, byte);
+        length &= (1 << PACKAGE_LENGTH_2BYTE_SHIFT) - 1;
+        /* fall through */
+    }
+    /*
+     * Most significant two bits of byte zero indicate how many following bytes
+     * are in PkgLength encoding.
+     */
+    byte = ((length_bytes - 1) << PACKAGE_LENGTH_1BYTE_SHIFT) | length;
+    build_prepend_byte(package, byte);
+}
+
+static void build_package(GArray *package, uint8_t op, unsigned min_bytes)
+{
+    build_prepend_package_length(package, min_bytes);
+    build_prepend_byte(package, op);
+}
+
+static void build_append_value(GArray *table, uint32_t value, int size)
+{
+    uint8_t prefix;
+    int i;
+
+    switch (size) {
+    case 1:
+        prefix = 0x0A; /* BytePrefix */
+        break;
+    case 2:
+        prefix = 0x0B; /* WordPrefix */
+        break;
+    case 4:
+        prefix = 0x0C; /* DWordPrefix */
+        break;
+    default:
+        assert(0);
+        return;
+    }
+    build_append_byte(table, prefix);
+    for (i = 0; i < size; ++i) {
+        build_append_byte(table, value & 0xFF);
+        value = value >> 8;
+    }
+}
+
+static void build_append_notify_target(GArray *method, GArray *target_name,
+                                       uint32_t value, int size)
+{
+    GArray *notify = build_alloc_array();
+    uint8_t op = 0xA0; /* IfOp */
+
+    build_append_byte(notify, 0x93); /* LEqualOp */
+    build_append_byte(notify, 0x68); /* Arg0Op */
+    build_append_value(notify, value, size);
+    build_append_byte(notify, 0x86); /* NotifyOp */
+    build_append_array(notify, target_name);
+    build_append_byte(notify, 0x69); /* Arg1Op */
+
+    /* Pack it up */
+    build_package(notify, op, 1);
+
+    build_append_array(method, notify);
+
+    build_free_array(notify);
+}
+
+#define ACPI_PORT_SMI_CMD           0x00b2 /* TODO: this is APM_CNT_IOPORT */
+
+static inline void *acpi_data_push(GArray *table_data, unsigned size)
+{
+    unsigned off = table_data->len;
+    g_array_set_size(table_data, off + size);
+    return table_data->data + off;
+}
+
+static unsigned acpi_data_len(GArray *table)
+{
+    return table->len * g_array_get_element_size(table);
+}
+
+static void acpi_align_size(GArray *blob, unsigned align)
+{
+    /* Align size to multiple of given size. This reduces the chance
+     * we need to change size in the future (breaking cross version migration).
+     */
+    g_array_set_size(blob, (ROUND_UP(acpi_data_len(blob), align) +
+                            g_array_get_element_size(blob) - 1) /
+                             g_array_get_element_size(blob));
+}
+
+/* Get pointer within table in a safe manner */
+#define ACPI_BUILD_PTR(table, size, off, type) \
+    ((type *)(acpi_data_get_ptr(table, size, off, sizeof(type))))
+
+static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
+                                      unsigned off, unsigned size)
+{
+    assert(off + size > off);
+    assert(off + size <= table_size);
+    return table_data + off;
+}
+
+static inline void acpi_add_table(GArray *table_offsets, GArray *table_data)
+{
+    uint32_t offset = cpu_to_le32(table_data->len);
+    g_array_append_val(table_offsets, offset);
+}
+
+/* FACS */
+static void
+build_facs(GArray *table_data, GArray *linker, PcGuestInfo *guest_info)
+{
+    AcpiFacsDescriptorRev1 *facs = acpi_data_push(table_data, sizeof *facs);
+    facs->signature = cpu_to_le32(ACPI_FACS_SIGNATURE);
+    facs->length = cpu_to_le32(sizeof(*facs));
+}
+
+/* Load chipset information in FADT */
+static void fadt_setup(AcpiFadtDescriptorRev1 *fadt, AcpiPmInfo *pm)
+{
+    fadt->model = 1;
+    fadt->reserved1 = 0;
+    fadt->sci_int = cpu_to_le16(pm->sci_int);
+    fadt->smi_cmd = cpu_to_le32(ACPI_PORT_SMI_CMD);
+    fadt->acpi_enable = pm->acpi_enable_cmd;
+    fadt->acpi_disable = pm->acpi_disable_cmd;
+    /* EVT, CNT, TMR offset matches hw/acpi/core.c */
+    fadt->pm1a_evt_blk = cpu_to_le32(pm->io_base);
+    fadt->pm1a_cnt_blk = cpu_to_le32(pm->io_base + 0x04);
+    fadt->pm_tmr_blk = cpu_to_le32(pm->io_base + 0x08);
+    fadt->gpe0_blk = cpu_to_le32(pm->gpe0_blk);
+    /* EVT, CNT, TMR length matches hw/acpi/core.c */
+    fadt->pm1_evt_len = 4;
+    fadt->pm1_cnt_len = 2;
+    fadt->pm_tmr_len = 4;
+    fadt->gpe0_blk_len = pm->gpe0_blk_len;
+    fadt->plvl2_lat = cpu_to_le16(0xfff); /* C2 state not supported */
+    fadt->plvl3_lat = cpu_to_le16(0xfff); /* C3 state not supported */
+    fadt->flags = cpu_to_le32((1 << ACPI_FADT_F_WBINVD) |
+                              (1 << ACPI_FADT_F_PROC_C1) |
+                              (1 << ACPI_FADT_F_SLP_BUTTON) |
+                              (1 << ACPI_FADT_F_RTC_S4));
+    fadt->flags |= cpu_to_le32(1 << ACPI_FADT_F_USE_PLATFORM_CLOCK);
+}
+
+
+/* FADT */
+static void
+build_fadt(GArray *table_data, GArray *linker, AcpiPmInfo *pm,
+           unsigned facs, unsigned dsdt)
+{
+    AcpiFadtDescriptorRev1 *fadt = acpi_data_push(table_data, sizeof(*fadt));
+
+    fadt->firmware_ctrl = cpu_to_le32(facs);
+    /* FACS address to be filled by Guest linker */
+    bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+                                   ACPI_BUILD_TABLE_FILE,
+                                   table_data, &fadt->firmware_ctrl,
+                                   sizeof fadt->firmware_ctrl);
+
+    fadt->dsdt = cpu_to_le32(dsdt);
+    /* DSDT address to be filled by Guest linker */
+    bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE,
+                                   ACPI_BUILD_TABLE_FILE,
+                                   table_data, &fadt->dsdt,
+                                   sizeof fadt->dsdt);
+
+    fadt_setup(fadt, pm);
+
+    build_header(linker, table_data,
+                 (void *)fadt, ACPI_FACP_SIGNATURE, sizeof(*fadt), 1);
+}
+
+static void
+build_madt(GArray *table_data, GArray *linker, AcpiCpuInfo *cpu,
+           PcGuestInfo *guest_info)
+{
+    int madt_start = table_data->len;
+
+    AcpiMultipleApicTable *madt;
+    AcpiMadtIoApic *io_apic;
+    AcpiMadtIntsrcovr *intsrcovr;
+    AcpiMadtLocalNmi *local_nmi;
+    int i;
+
+    madt = acpi_data_push(table_data, sizeof *madt);
+    madt->local_apic_address = cpu_to_le32(APIC_DEFAULT_ADDRESS);
+    madt->flags = cpu_to_le32(1);
+
+    for (i = 0; i < guest_info->apic_id_limit; i++) {
+        AcpiMadtProcessorApic *apic = acpi_data_push(table_data, sizeof *apic);
+        apic->type = ACPI_APIC_PROCESSOR;
+        apic->length = sizeof(*apic);
+        apic->processor_id = i;
+        apic->local_apic_id = i;
+        if (test_bit(i, cpu->found_cpus)) {
+            apic->flags = cpu_to_le32(1);
+        } else {
+            apic->flags = cpu_to_le32(0);
+        }
+    }
+    io_apic = acpi_data_push(table_data, sizeof *io_apic);
+    io_apic->type = ACPI_APIC_IO;
+    io_apic->length = sizeof(*io_apic);
+#define ACPI_BUILD_IOAPIC_ID 0x0
+    io_apic->io_apic_id = ACPI_BUILD_IOAPIC_ID;
+    io_apic->address = cpu_to_le32(IO_APIC_DEFAULT_ADDRESS);
+    io_apic->interrupt = cpu_to_le32(0);
+
+    if (guest_info->apic_xrupt_override) {
+        intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+        intsrcovr->type   = ACPI_APIC_XRUPT_OVERRIDE;
+        intsrcovr->length = sizeof(*intsrcovr);
+        intsrcovr->source = 0;
+        intsrcovr->gsi    = cpu_to_le32(2);
+        intsrcovr->flags  = cpu_to_le16(0); /* conforms to bus specifications */
+    }
+    for (i = 1; i < 16; i++) {
+#define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
+        if (!(ACPI_BUILD_PCI_IRQS & (1 << i))) {
+            /* No need for a INT source override structure. */
+            continue;
+        }
+        intsrcovr = acpi_data_push(table_data, sizeof *intsrcovr);
+        intsrcovr->type   = ACPI_APIC_XRUPT_OVERRIDE;
+        intsrcovr->length = sizeof(*intsrcovr);
+        intsrcovr->source = i;
+        intsrcovr->gsi    = cpu_to_le32(i);
+        intsrcovr->flags  = cpu_to_le16(0xd); /* active high, level triggered */
+    }
+
+    local_nmi = acpi_data_push(table_data, sizeof *local_nmi);
+    local_nmi->type         = ACPI_APIC_LOCAL_NMI;
+    local_nmi->length       = sizeof(*local_nmi);
+    local_nmi->processor_id = 0xff; /* all processors */
+    local_nmi->flags        = cpu_to_le16(0);
+    local_nmi->lint         = 1; /* ACPI_LINT1 */
+
+    build_header(linker, table_data,
+                 (void *)(table_data->data + madt_start), ACPI_APIC_SIGNATURE,
+                 table_data->len - madt_start, 1);
+}
+
+/* Encode a hex value */
+static inline char acpi_get_hex(uint32_t val)
+{
+    val &= 0x0f;
+    return (val <= 9) ? ('0' + val) : ('A' + val - 10);
+}
+
+#include "hw/i386/ssdt-proc.hex"
+
+/* 0x5B 0x83 ProcessorOp PkgLength NameString ProcID */
+#define ACPI_PROC_OFFSET_CPUHEX (*ssdt_proc_name - *ssdt_proc_start + 2)
+#define ACPI_PROC_OFFSET_CPUID1 (*ssdt_proc_name - *ssdt_proc_start + 4)
+#define ACPI_PROC_OFFSET_CPUID2 (*ssdt_proc_id - *ssdt_proc_start)
+#define ACPI_PROC_SIZEOF (*ssdt_proc_end - *ssdt_proc_start)
+#define ACPI_PROC_AML (ssdp_proc_aml + *ssdt_proc_start)
+
+/* 0x5B 0x82 DeviceOp PkgLength NameString */
+#define ACPI_PCIHP_OFFSET_HEX (*ssdt_pcihp_name - *ssdt_pcihp_start + 1)
+#define ACPI_PCIHP_OFFSET_ID (*ssdt_pcihp_id - *ssdt_pcihp_start)
+#define ACPI_PCIHP_OFFSET_ADR (*ssdt_pcihp_adr - *ssdt_pcihp_start)
+#define ACPI_PCIHP_OFFSET_EJ0 (*ssdt_pcihp_ej0 - *ssdt_pcihp_start)
+#define ACPI_PCIHP_SIZEOF (*ssdt_pcihp_end - *ssdt_pcihp_start)
+#define ACPI_PCIHP_AML (ssdp_pcihp_aml + *ssdt_pcihp_start)
+
+#define ACPI_SSDT_SIGNATURE 0x54445353 /* SSDT */
+#define ACPI_SSDT_HEADER_LENGTH 36
+
+#include "hw/i386/ssdt-misc.hex"
+#include "hw/i386/ssdt-pcihp.hex"
+
+static void
+build_append_notify(GArray *device, const char *name,
+                    const char *format, int skip, int count)
+{
+    int i;
+    GArray *method = build_alloc_array();
+    uint8_t op = 0x14; /* MethodOp */
+
+    build_append_nameseg(method, name);
+    build_append_byte(method, 0x02); /* MethodFlags: ArgCount */
+    for (i = skip; i < count; i++) {
+        GArray *target = build_alloc_array();
+        build_append_nameseg(target, format, i);
+        assert(i < 256); /* Fits in 1 byte */
+        build_append_notify_target(method, target, i, 1);
+        build_free_array(target);
+    }
+    build_package(method, op, 2);
+
+    build_append_array(device, method);
+    build_free_array(method);
+}
+
+static void patch_pcihp(int slot, uint8_t *ssdt_ptr, uint32_t eject)
+{
+    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(slot >> 4);
+    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(slot);
+    ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
+    ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
+
+    /* Runtime patching of ACPI_EJ0: to disable hotplug for a slot,
+     * replace the method name: _EJ0 by ACPI_EJ0_.
+     */
+    /* Sanity check */
+    assert(!memcmp(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "_EJ0", 4));
+
+    if (!eject) {
+        memcpy(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "EJ0_", 4);
+    }
+}
+
+static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
+{
+    *ACPI_BUILD_PTR(start, size, acpi_pci32_start[0], uint32_t) =
+        cpu_to_le32(pci->w32.begin);
+
+    *ACPI_BUILD_PTR(start, size, acpi_pci32_end[0], uint32_t) =
+        cpu_to_le32(pci->w32.end - 1);
+
+    if (pci->w64.end || pci->w64.begin) {
+        *ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 1;
+        *ACPI_BUILD_PTR(start, size, acpi_pci64_start[0], uint64_t) =
+            cpu_to_le64(pci->w64.begin);
+        *ACPI_BUILD_PTR(start, size, acpi_pci64_end[0], uint64_t) =
+            cpu_to_le64(pci->w64.end - 1);
+        *ACPI_BUILD_PTR(start, size, acpi_pci64_length[0], uint64_t) =
+            cpu_to_le64(pci->w64.end - pci->w64.begin);
+    } else {
+        *ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 0;
+    }
+}
+
+static void
+build_ssdt(GArray *table_data, GArray *linker,
+           AcpiCpuInfo *cpu, AcpiPmInfo *pm, AcpiMiscInfo *misc,
+           PcPciInfo *pci, PcGuestInfo *guest_info)
+{
+    int acpi_cpus = MIN(0xff, guest_info->apic_id_limit);
+    int ssdt_start = table_data->len;
+    uint8_t *ssdt_ptr;
+    int i;
+
+    /* Copy header and patch values in the S3_ / S4_ / S5_ packages */
+    ssdt_ptr = acpi_data_push(table_data, sizeof(ssdp_misc_aml));
+    memcpy(ssdt_ptr, ssdp_misc_aml, sizeof(ssdp_misc_aml));
+    if (pm->s3_disabled) {
+        ssdt_ptr[acpi_s3_name[0]] = 'X';
+    }
+    if (pm->s4_disabled) {
+        ssdt_ptr[acpi_s4_name[0]] = 'X';
+    } else {
+        ssdt_ptr[acpi_s4_pkg[0] + 1] = ssdt_ptr[acpi_s4_pkg[0] + 3] =
+            pm->s4_val;
+    }
+
+    patch_pci_windows(pci, ssdt_ptr, sizeof(ssdp_misc_aml));
+
+    *(uint16_t *)(ssdt_ptr + *ssdt_isa_pest) =
+        cpu_to_le16(misc->pvpanic_port);
+
+    {
+        GArray *sb_scope = build_alloc_array();
+        uint8_t op = 0x10; /* ScopeOp */
+
+        build_append_nameseg(sb_scope, "_SB_");
+
+        /* build Processor object for each processor */
+        for (i = 0; i < acpi_cpus; i++) {
+            uint8_t *proc = acpi_data_push(sb_scope, ACPI_PROC_SIZEOF);
+            memcpy(proc, ACPI_PROC_AML, ACPI_PROC_SIZEOF);
+            proc[ACPI_PROC_OFFSET_CPUHEX] = acpi_get_hex(i >> 4);
+            proc[ACPI_PROC_OFFSET_CPUHEX+1] = acpi_get_hex(i);
+            proc[ACPI_PROC_OFFSET_CPUID1] = i;
+            proc[ACPI_PROC_OFFSET_CPUID2] = i;
+        }
+
+        /* build this code:
+         *   Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
+         */
+        /* Arg0 = Processor ID = APIC ID */
+        build_append_notify(sb_scope, "NTFY", "CP%0.02X", 0, acpi_cpus);
+
+        /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" */
+        build_append_byte(sb_scope, 0x08); /* NameOp */
+        build_append_nameseg(sb_scope, "CPON");
+
+        {
+            GArray *package = build_alloc_array();
+            uint8_t op = 0x12; /* PackageOp */
+
+            build_append_byte(package, acpi_cpus); /* NumElements */
+            for (i = 0; i < acpi_cpus; i++) {
+                uint8_t b = test_bit(i, cpu->found_cpus) ? 0x01 : 0x00;
+                build_append_byte(package, b);
+            }
+
+            build_package(package, op, 2);
+            build_append_array(sb_scope, package);
+            build_free_array(package);
+        }
+
+        {
+            GArray *pci0 = build_alloc_array();
+            uint8_t op = 0x10; /* ScopeOp */;
+
+            build_append_nameseg(pci0, "PCI0");
+
+            /* build Device object for each slot */
+            for (i = 1; i < PCI_SLOT_MAX; i++) {
+                bool eject = test_bit(i, misc->slot_hotplug_enable);
+                void *pcihp = acpi_data_push(pci0, ACPI_PCIHP_SIZEOF);
+
+                memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
+                patch_pcihp(i, pcihp, eject);
+            }
+
+            build_append_notify(pci0, "PCNT", "S%0.02X_", 1, PCI_SLOT_MAX);
+            build_package(pci0, op, 3);
+            build_append_array(sb_scope, pci0);
+            build_free_array(pci0);
+        }
+
+        build_package(sb_scope, op, 3);
+        build_append_array(table_data, sb_scope);
+        build_free_array(sb_scope);
+    }
+
+    build_header(linker, table_data,
+                 (void *)(table_data->data + ssdt_start),
+                 ACPI_SSDT_SIGNATURE, table_data->len - ssdt_start, 1);
+}
+
+static void
+build_hpet(GArray *table_data, GArray *linker)
+{
+    Acpi20Hpet *hpet;
+
+    hpet = acpi_data_push(table_data, sizeof(*hpet));
+    /* Note timer_block_id value must be kept in sync with value advertised by
+     * emulated hpet
+     */
+    hpet->timer_block_id = cpu_to_le32(0x8086a201);
+    hpet->addr.address = cpu_to_le64(HPET_BASE);
+    build_header(linker, table_data,
+                 (void *)hpet, ACPI_HPET_SIGNATURE, sizeof(*hpet), 1);
+}
+
+static void
+acpi_build_srat_memory(AcpiSratMemoryAffinity *numamem,
+                       uint64_t base, uint64_t len, int node, int enabled)
+{
+    numamem->type = ACPI_SRAT_MEMORY;
+    numamem->length = sizeof(*numamem);
+    memset(numamem->proximity, 0, 4);
+    numamem->proximity[0] = node;
+    numamem->flags = cpu_to_le32(!!enabled);
+    numamem->base_addr = cpu_to_le64(base);
+    numamem->range_length = cpu_to_le64(len);
+}
+
+static void
+build_srat(GArray *table_data, GArray *linker,
+           AcpiCpuInfo *cpu, PcGuestInfo *guest_info)
+{
+    AcpiSystemResourceAffinityTable *srat;
+    AcpiSratProcessorAffinity *core;
+    AcpiSratMemoryAffinity *numamem;
+
+    int i;
+    uint64_t curnode;
+    int srat_start, numa_start, slots;
+    uint64_t mem_len, mem_base, next_base;
+
+    srat_start = table_data->len;
+
+    srat = acpi_data_push(table_data, sizeof *srat);
+    srat->reserved1 = cpu_to_le32(1);
+    core = (void *)(srat + 1);
+
+    for (i = 0; i < guest_info->apic_id_limit; ++i) {
+        core = acpi_data_push(table_data, sizeof *core);
+        core->type = ACPI_SRAT_PROCESSOR;
+        core->length = sizeof(*core);
+        core->local_apic_id = i;
+        curnode = guest_info->node_cpu[i];
+        core->proximity_lo = curnode;
+        memset(core->proximity_hi, 0, 3);
+        core->local_sapic_eid = 0;
+        if (test_bit(i, cpu->found_cpus)) {
+            core->flags = cpu_to_le32(1);
+        } else {
+            core->flags = cpu_to_le32(0);
+        }
+    }
+
+
+    /* the memory map is a bit tricky, it contains at least one hole
+     * from 640k-1M and possibly another one from 3.5G-4G.
+     */
+    next_base = 0;
+    numa_start = table_data->len;
+
+    numamem = acpi_data_push(table_data, sizeof *numamem);
+    acpi_build_srat_memory(numamem, 0, 640*1024, 0, 1);
+    next_base = 1024 * 1024;
+    for (i = 1; i < guest_info->numa_nodes + 1; ++i) {
+        mem_base = next_base;
+        mem_len = guest_info->node_mem[i - 1];
+        if (i == 1) {
+            mem_len -= 1024 * 1024;
+        }
+        next_base = mem_base + mem_len;
+
+        /* Cut out the ACPI_PCI hole */
+        if (mem_base <= guest_info->ram_size &&
+            next_base > guest_info->ram_size) {
+            mem_len -= next_base - guest_info->ram_size;
+            if (mem_len > 0) {
+                numamem = acpi_data_push(table_data, sizeof *numamem);
+                acpi_build_srat_memory(numamem, mem_base, mem_len, i-1, 1);
+            }
+            mem_base = 1ULL << 32;
+            mem_len = next_base - guest_info->ram_size;
+            next_base += (1ULL << 32) - guest_info->ram_size;
+        }
+        numamem = acpi_data_push(table_data, sizeof *numamem);
+        acpi_build_srat_memory(numamem, mem_base, mem_len, i - 1, 1);
+    }
+    slots = (table_data->len - numa_start) / sizeof *numamem;
+    for (; slots < guest_info->numa_nodes + 2; slots++) {
+        numamem = acpi_data_push(table_data, sizeof *numamem);
+        acpi_build_srat_memory(numamem, 0, 0, 0, 0);
+    }
+
+    build_header(linker, table_data,
+                 (void *)(table_data->data + srat_start),
+                 ACPI_SRAT_SIGNATURE,
+                 table_data->len - srat_start, 1);
+}
+
+static void
+build_mcfg_q35(GArray *table_data, GArray *linker, AcpiMcfgInfo *info)
+{
+    AcpiTableMcfg *mcfg;
+    uint32_t sig;
+    int len = sizeof(*mcfg) + 1 * sizeof(mcfg->allocation[0]);
+
+    mcfg = acpi_data_push(table_data, len);
+    mcfg->allocation[0].address = cpu_to_le64(info->mcfg_base);
+    /* Only a single allocation so no need to play with segments */
+    mcfg->allocation[0].pci_segment = cpu_to_le16(0);
+    mcfg->allocation[0].start_bus_number = 0;
+    mcfg->allocation[0].end_bus_number = PCIE_MMCFG_BUS(info->mcfg_size - 1);
+
+    /* MCFG is used for ECAM which can be enabled or disabled by guest.
+     * To avoid table size changes (which create migration issues),
+     * always create the table even if there are no allocations,
+     * but set the signature to a reserved value in this case.
+     * ACPI spec requires OSPMs to ignore such tables.
+     */
+    if (info->mcfg_base == PCIE_BASE_ADDR_UNMAPPED) {
+        sig = ACPI_RSRV_SIGNATURE;
+    } else {
+        sig = ACPI_MCFG_SIGNATURE;
+    }
+    build_header(linker, table_data, (void *)mcfg, sig, len, 1);
+}
+
+static void
+build_dsdt(GArray *table_data, GArray *linker, AcpiMiscInfo *misc)
+{
+    void *dsdt;
+    assert(misc->dsdt_code && misc->dsdt_size);
+    dsdt = acpi_data_push(table_data, misc->dsdt_size);
+    memcpy(dsdt, misc->dsdt_code, misc->dsdt_size);
+}
+
+/* Build final rsdt table */
+static void
+build_rsdt(GArray *table_data, GArray *linker, GArray *table_offsets)
+{
+    AcpiRsdtDescriptorRev1 *rsdt;
+    size_t rsdt_len;
+    int i;
+
+    rsdt_len = sizeof(*rsdt) + sizeof(uint32_t) * table_offsets->len;
+    rsdt = acpi_data_push(table_data, rsdt_len);
+    memcpy(rsdt->table_offset_entry, table_offsets->data,
+           sizeof(uint32_t) * table_offsets->len);
+    for (i = 0; i < table_offsets->len; ++i) {
+        /* rsdt->table_offset_entry to be filled by Guest linker */
+        bios_linker_loader_add_pointer(linker,
+                                       ACPI_BUILD_TABLE_FILE,
+                                       ACPI_BUILD_TABLE_FILE,
+                                       table_data, &rsdt->table_offset_entry[i],
+                                       sizeof(uint32_t));
+    }
+    build_header(linker, table_data,
+                 (void *)rsdt, ACPI_RSDT_SIGNATURE, rsdt_len, 1);
+}
+
+static GArray *
+build_rsdp(GArray *rsdp_table, GArray *linker, unsigned rsdt)
+{
+    AcpiRsdpDescriptor *rsdp = acpi_data_push(rsdp_table, sizeof *rsdp);
+
+    bios_linker_loader_alloc(linker, ACPI_BUILD_RSDP_FILE, 1,
+                             true /* fseg memory */);
+
+    rsdp->signature = cpu_to_le64(ACPI_RSDP_SIGNATURE);
+    memcpy(rsdp->oem_id, ACPI_BUILD_APPNAME6, 6);
+    rsdp->rsdt_physical_address = cpu_to_le32(rsdt);
+    /* Address to be filled by Guest linker */
+    bios_linker_loader_add_pointer(linker, ACPI_BUILD_RSDP_FILE,
+                                   ACPI_BUILD_TABLE_FILE,
+                                   rsdp_table, &rsdp->rsdt_physical_address,
+                                   sizeof rsdp->rsdt_physical_address);
+    rsdp->checksum = 0;
+    /* Checksum to be filled by Guest linker */
+    bios_linker_loader_add_checksum(linker, ACPI_BUILD_RSDP_FILE,
+                                    rsdp, rsdp, sizeof *rsdp, &rsdp->checksum);
+
+    return rsdp_table;
+}
+
+typedef
+struct AcpiBuildTables {
+    GArray *table_data;
+    GArray *rsdp;
+    GArray *linker;
+} AcpiBuildTables;
+
+static inline void acpi_build_tables_init(AcpiBuildTables *tables)
+{
+    tables->rsdp = g_array_new(false, true /* clear */, 1);
+    tables->table_data = g_array_new(false, true /* clear */, 1);
+    tables->linker = bios_linker_loader_init();
+}
+
+static inline void acpi_build_tables_cleanup(AcpiBuildTables *tables, bool mfre)
+{
+    void *linker_data = bios_linker_loader_cleanup(tables->linker);
+    if (mfre) {
+        g_free(linker_data);
+    }
+    g_array_free(tables->rsdp, mfre);
+    g_array_free(tables->table_data, mfre);
+}
+
+typedef
+struct AcpiBuildState {
+    /* Copy of table in RAM (for patching). */
+    uint8_t *table_ram;
+    uint32_t table_size;
+    /* Is table patched? */
+    uint8_t patched;
+    PcGuestInfo *guest_info;
+} AcpiBuildState;
+
+static bool acpi_get_mcfg(AcpiMcfgInfo *mcfg)
+{
+    Object *pci_host;
+    QObject *o;
+    bool ambiguous;
+
+    pci_host = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
+    g_assert(!ambiguous);
+    g_assert(pci_host);
+
+    o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_BASE, NULL);
+    if (!o) {
+        return false;
+    }
+    mcfg->mcfg_base = qint_get_int(qobject_to_qint(o));
+
+    o = object_property_get_qobject(pci_host, PCIE_HOST_MCFG_SIZE, NULL);
+    assert(o);
+    mcfg->mcfg_size = qint_get_int(qobject_to_qint(o));
+    return true;
+}
+
+static
+void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
+{
+    GArray *table_offsets;
+    unsigned facs, dsdt, rsdt;
+    AcpiCpuInfo cpu;
+    AcpiPmInfo pm;
+    AcpiMiscInfo misc;
+    AcpiMcfgInfo mcfg;
+    PcPciInfo pci;
+    uint8_t *u;
+
+    acpi_get_cpu_info(&cpu);
+    acpi_get_pm_info(&pm);
+    acpi_get_dsdt(&misc);
+    acpi_get_hotplug_info(&misc);
+    acpi_get_misc_info(&misc);
+    acpi_get_pci_info(&pci);
+
+    table_offsets = g_array_new(false, true /* clear */,
+                                        sizeof(uint32_t));
+    ACPI_BUILD_DPRINTF(3, "init ACPI tables\n");
+
+    bios_linker_loader_alloc(tables->linker, ACPI_BUILD_TABLE_FILE,
+                             64 /* Ensure FACS is aligned */,
+                             false /* high memory */);
+
+    /*
+     * FACS is pointed to by FADT.
+     * We place it first since it's the only table that has alignment
+     * requirements.
+     */
+    facs = tables->table_data->len;
+    build_facs(tables->table_data, tables->linker, guest_info);
+
+    /* DSDT is pointed to by FADT */
+    dsdt = tables->table_data->len;
+    build_dsdt(tables->table_data, tables->linker, &misc);
+
+    /* ACPI tables pointed to by RSDT */
+    acpi_add_table(table_offsets, tables->table_data);
+    build_fadt(tables->table_data, tables->linker, &pm, facs, dsdt);
+    acpi_add_table(table_offsets, tables->table_data);
+
+    build_ssdt(tables->table_data, tables->linker, &cpu, &pm, &misc, &pci,
+               guest_info);
+    acpi_add_table(table_offsets, tables->table_data);
+
+    build_madt(tables->table_data, tables->linker, &cpu, guest_info);
+    acpi_add_table(table_offsets, tables->table_data);
+    if (misc.has_hpet) {
+        build_hpet(tables->table_data, tables->linker);
+    }
+    if (guest_info->numa_nodes) {
+        acpi_add_table(table_offsets, tables->table_data);
+        build_srat(tables->table_data, tables->linker, &cpu, guest_info);
+    }
+    if (acpi_get_mcfg(&mcfg)) {
+        acpi_add_table(table_offsets, tables->table_data);
+        build_mcfg_q35(tables->table_data, tables->linker, &mcfg);
+    }
+
+    /* Add tables supplied by user (if any) */
+    for (u = acpi_table_first(); u; u = acpi_table_next(u)) {
+        unsigned len = acpi_table_len(u);
+
+        acpi_add_table(table_offsets, tables->table_data);
+        g_array_append_vals(tables->table_data, u, len);
+    }
+
+    /* RSDT is pointed to by RSDP */
+    rsdt = tables->table_data->len;
+    build_rsdt(tables->table_data, tables->linker, table_offsets);
+
+    /* RSDP is in FSEG memory, so allocate it separately */
+    build_rsdp(tables->rsdp, tables->linker, rsdt);
+
+    /* We'll expose it all to Guest so align size to reduce
+     * chance of size changes.
+     * RSDP is small so it's easy to keep it immutable, no need to
+     * bother with alignment.
+     */
+    acpi_align_size(tables->table_data, 0x1000);
+
+    acpi_align_size(tables->linker, 0x1000);
+
+    /* Cleanup memory that's no longer used. */
+    g_array_free(table_offsets, true);
+}
+
+static void acpi_build_update(void *build_opaque, uint32_t offset)
+{
+    AcpiBuildState *build_state = build_opaque;
+    AcpiBuildTables tables;
+
+    /* No state to update or already patched? Nothing to do. */
+    if (!build_state || build_state->patched) {
+        return;
+    }
+    build_state->patched = 1;
+
+    acpi_build_tables_init(&tables);
+
+    acpi_build(build_state->guest_info, &tables);
+
+    assert(acpi_data_len(tables.table_data) == build_state->table_size);
+    memcpy(build_state->table_ram, tables.table_data->data,
+           build_state->table_size);
+
+    acpi_build_tables_cleanup(&tables, true);
+}
+
+static void acpi_build_reset(void *build_opaque)
+{
+    AcpiBuildState *build_state = build_opaque;
+    build_state->patched = 0;
+}
+
+static void *acpi_add_rom_blob(AcpiBuildState *build_state, GArray *blob,
+                               const char *name)
+{
+    return rom_add_blob(name, blob->data, acpi_data_len(blob), -1, name,
+                        acpi_build_update, build_state);
+}
+
+static const VMStateDescription vmstate_acpi_build = {
+    .name = "acpi_build",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT8(patched, AcpiBuildState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+void acpi_setup(PcGuestInfo *guest_info)
+{
+    AcpiBuildTables tables;
+    AcpiBuildState *build_state;
+
+    if (!guest_info->fw_cfg) {
+        ACPI_BUILD_DPRINTF(3, "No fw cfg. Bailing out.\n");
+        return;
+    }
+
+    if (!guest_info->has_acpi_build) {
+        ACPI_BUILD_DPRINTF(3, "ACPI build disabled. Bailing out.\n");
+        return;
+    }
+
+    build_state = g_malloc0(sizeof *build_state);
+
+    build_state->guest_info = guest_info;
+
+    acpi_build_tables_init(&tables);
+    acpi_build(build_state->guest_info, &tables);
+
+    /* Now expose it all to Guest */
+    build_state->table_ram = acpi_add_rom_blob(build_state, tables.table_data,
+                                               ACPI_BUILD_TABLE_FILE);
+    build_state->table_size = acpi_data_len(tables.table_data);
+
+    acpi_add_rom_blob(NULL, tables.linker, "etc/table-loader");
+
+    /*
+     * RSDP is small so it's easy to keep it immutable, no need to
+     * bother with ROM blobs.
+     */
+    fw_cfg_add_file(guest_info->fw_cfg, ACPI_BUILD_RSDP_FILE,
+                    tables.rsdp->data, acpi_data_len(tables.rsdp));
+
+    qemu_register_reset(acpi_build_reset, build_state);
+    acpi_build_reset(build_state);
+    vmstate_register(NULL, 0, &vmstate_acpi_build, build_state);
+
+    /* Cleanup tables but don't free the memory: we track it
+     * in build_state.
+     */
+    acpi_build_tables_cleanup(&tables, false);
+}
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index f8a3f0b..a51f916 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -56,6 +56,7 @@
 #include "hw/cpu/icc_bus.h"
 #include "hw/boards.h"
 #include "hw/pci/pci_host.h"
+#include "acpi-build.h"
 
 /* debug PC/ISA interrupts */
 //#define DEBUG_IRQ
@@ -1040,6 +1041,7 @@ void pc_guest_info_machine_done(Notifier *notifier, void *data)
                                                       PcGuestInfoState,
                                                       machine_done);
     pc_fw_cfg_guest_info(&guest_info_state->info);
+    acpi_setup(&guest_info_state->info);
 }
 
 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 907792b..63ae2ae 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -59,6 +59,7 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
 
 static bool has_pvpanic;
 static bool has_pci_info = true;
+static bool has_acpi_build = true;
 
 /* PC hardware initialisation */
 static void pc_init1(QEMUMachineInitArgs *args,
@@ -122,6 +123,9 @@ static void pc_init1(QEMUMachineInitArgs *args,
     }
 
     guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
+
+    guest_info->has_acpi_build = has_acpi_build;
+
     guest_info->has_pci_info = has_pci_info;
     guest_info->isapc_ram_fw = !pci_enabled;
 
@@ -240,6 +244,7 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
 {
     has_pci_info = false;
     rom_file_in_ram = false;
+    has_acpi_build = false;
 }
 
 static void pc_compat_1_5(QEMUMachineInitArgs *args)
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index ca84e1c..4c191d3 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -49,6 +49,7 @@
 
 static bool has_pvpanic;
 static bool has_pci_info = true;
+static bool has_acpi_build = true;
 
 /* PC hardware initialisation */
 static void pc_q35_init(QEMUMachineInitArgs *args)
@@ -111,6 +112,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
     guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
     guest_info->has_pci_info = has_pci_info;
     guest_info->isapc_ram_fw = false;
+    guest_info->has_acpi_build = has_acpi_build;
 
     /* allocate ram and load rom/bios */
     if (!xen_enabled()) {
@@ -224,6 +226,7 @@ static void pc_compat_1_6(QEMUMachineInitArgs *args)
 {
     has_pci_info = false;
     rom_file_in_ram = false;
+    has_acpi_build = false;
 }
 
 static void pc_compat_1_5(QEMUMachineInitArgs *args)
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index b9ca380..185aacb 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -5,7 +5,11 @@ obj-y += pc_sysfw.o
 obj-$(CONFIG_XEN) += xen_domainbuild.o xen_machine_pv.o
 
 obj-y += kvmvapic.o
+obj-y += acpi-build.o
 obj-y += bios-linker-loader.o
+hw/i386/acpi-build.o: hw/i386/acpi-build.c hw/i386/acpi-dsdt.hex \
+	hw/i386/ssdt-proc.hex hw/i386/ssdt-pcihp.hex hw/i386/ssdt-misc.hex \
+	hw/i386/acpi-dsdt.hex hw/i386/q35-acpi-dsdt.hex
 
 iasl-option=$(shell if test -z "`$(1) $(2) 2>&1 > /dev/null`" \
     ; then echo "$(2)"; else echo "$(3)"; fi ;)
-- 
MST

[Qemu-devel] [PULL 38/43] ssdt: fix PBLK length

[Michael S. Tsirkin]

We don't really support CPU throttling, so supply 0 PBLK length.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/ssdt-proc.dsl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/i386/ssdt-proc.dsl b/hw/i386/ssdt-proc.dsl
index 58333c7..8229bfd 100644
--- a/hw/i386/ssdt-proc.dsl
+++ b/hw/i386/ssdt-proc.dsl
@@ -37,7 +37,7 @@ DefinitionBlock ("ssdt-proc.aml", "SSDT", 0x01, "BXPC", "BXSSDT", 0x1)
     ACPI_EXTRACT_PROCESSOR_START ssdt_proc_start
     ACPI_EXTRACT_PROCESSOR_END ssdt_proc_end
     ACPI_EXTRACT_PROCESSOR_STRING ssdt_proc_name
-    Processor(CPAA, 0xAA, 0x0000b010, 0x06) {
+    Processor(CPAA, 0xAA, 0x00000000, 0x0) {
         ACPI_EXTRACT_NAME_BYTE_CONST ssdt_proc_id
         Name(ID, 0xAA)
 /*
-- 
MST

[Qemu-devel] [PULL 39/43] ssdt-proc: update generated file

[Michael S. Tsirkin]

Update generated ssdt proc hex file (used for systems
lacking IASL) after P_BLK length change.

Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/ssdt-proc.hex.generated | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/hw/i386/ssdt-proc.hex.generated b/hw/i386/ssdt-proc.hex.generated
index a28172e..bb9920d 100644
--- a/hw/i386/ssdt-proc.hex.generated
+++ b/hw/i386/ssdt-proc.hex.generated
@@ -11,7 +11,7 @@ static unsigned char ssdp_proc_aml[] = {
 0x0,
 0x0,
 0x1,
-0xb3,
+0xb8,
 0x42,
 0x58,
 0x50,
@@ -34,9 +34,9 @@ static unsigned char ssdp_proc_aml[] = {
 0x4e,
 0x54,
 0x4c,
-0x28,
-0x5,
-0x10,
+0x23,
+0x8,
+0x13,
 0x20,
 0x5b,
 0x83,
@@ -51,7 +51,7 @@ static unsigned char ssdp_proc_aml[] = {
 0xb0,
 0x0,
 0x0,
-0x6,
+0x0,
 0x8,
 0x49,
 0x44,
-- 
MST

[Qemu-devel] [PULL 40/43] pci: add pci_for_each_bus_depth_first

[Michael S. Tsirkin]

Useful for ACPI hotplug.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/pci/pci.h | 14 ++++++++++++++
 hw/pci/pci.c         | 28 ++++++++++++++++++++++++++++
 2 files changed, 42 insertions(+)

diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 37ffa53..3755b02 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -388,6 +388,20 @@ int pci_bus_num(PCIBus *s);
 void pci_for_each_device(PCIBus *bus, int bus_num,
                          void (*fn)(PCIBus *bus, PCIDevice *d, void *opaque),
                          void *opaque);
+void pci_for_each_bus_depth_first(PCIBus *bus,
+                                  void *(*begin)(PCIBus *bus, void *parent_state),
+                                  void (*end)(PCIBus *bus, void *state),
+                                  void *parent_state);
+
+/* Use this wrapper when specific scan order is not required. */
+static inline
+void pci_for_each_bus(PCIBus *bus,
+                      void (*fn)(PCIBus *bus, void *opaque),
+                      void *opaque)
+{
+    pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
+}
+
 PCIBus *pci_find_primary_bus(void);
 PCIBus *pci_device_root_bus(const PCIDevice *d);
 const char *pci_root_bus_path(PCIDevice *dev);
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index a98c8a0..d5c3a91 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -1724,6 +1724,34 @@ static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
     return NULL;
 }
 
+void pci_for_each_bus_depth_first(PCIBus *bus,
+                                  void *(*begin)(PCIBus *bus, void *parent_state),
+                                  void (*end)(PCIBus *bus, void *state),
+                                  void *parent_state)
+{
+    PCIBus *sec;
+    void *state;
+
+    if (!bus) {
+        return;
+    }
+
+    if (begin) {
+        state = begin(bus, parent_state);
+    } else {
+        state = parent_state;
+    }
+
+    QLIST_FOREACH(sec, &bus->child, sibling) {
+        pci_for_each_bus_depth_first(sec, begin, end, state);
+    }
+
+    if (end) {
+        end(bus, state);
+    }
+}
+
+
 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
 {
     bus = pci_find_bus_nr(bus, bus_num);
-- 
MST

[Qemu-devel] [PULL 41/43] pcihp: generalization of piix4 acpi

[Michael S. Tsirkin]

Add ACPI based PCI hotplug library with bridge hotplug
support.
Design
   - each bus gets assigned "bsel" property.
   - ACPI code writes this number
     to a new BNUM register, then uses existing
     UP/DOWN registers to probe slot status;
     to eject, write number to BNUM register,
     then slot into existing EJ.

The interface is actually backwards-compatible with
existing PIIX4 ACPI (though not migration compatible).

This is split out from PIIX4 codebase so we can
reuse it for Q35 as well.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/acpi/pcihp.h |  72 +++++++++++
 hw/acpi/pcihp.c         | 312 ++++++++++++++++++++++++++++++++++++++++++++++++
 hw/acpi/Makefile.objs   |   2 +-
 3 files changed, 385 insertions(+), 1 deletion(-)
 create mode 100644 include/hw/acpi/pcihp.h
 create mode 100644 hw/acpi/pcihp.c

diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
new file mode 100644
index 0000000..6230e60
--- /dev/null
+++ b/include/hw/acpi/pcihp.h
@@ -0,0 +1,72 @@
+/*
+ * QEMU<->ACPI BIOS PCI hotplug interface
+ *
+ * QEMU supports PCI hotplug via ACPI. This module
+ * implements the interface between QEMU and the ACPI BIOS.
+ * Interface specification - see docs/specs/acpi_pci_hotplug.txt
+ *
+ * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#ifndef HW_ACPI_PCIHP_H
+#define HW_ACPI_PCIHP_H
+
+#include <inttypes.h>
+#include <qemu/typedefs.h>
+#include "hw/pci/pci.h" /* for PCIHotplugState */
+
+typedef struct AcpiPciHpPciStatus {
+    uint32_t up; /* deprecated, maintained for migration compatibility */
+    uint32_t down;
+    uint32_t hotplug_enable;
+    uint32_t device_present;
+} AcpiPciHpPciStatus;
+
+#define ACPI_PCIHP_PROP_BSEL "acpi-pcihp-bsel"
+#define ACPI_PCIHP_MAX_HOTPLUG_BUS 256
+
+typedef struct AcpiPciHpState {
+    AcpiPciHpPciStatus acpi_pcihp_pci_status[ACPI_PCIHP_MAX_HOTPLUG_BUS];
+    uint32_t hotplug_select;
+    PCIBus *root;
+    MemoryRegion io;
+} AcpiPciHpState;
+
+void acpi_pcihp_init(AcpiPciHpState *, PCIBus *root,
+                     MemoryRegion *address_space_io);
+
+/* Invoke on device hotplug */
+int acpi_pcihp_device_hotplug(AcpiPciHpState *, PCIDevice *,
+                              PCIHotplugState state);
+
+/* Called on reset */
+void acpi_pcihp_reset(AcpiPciHpState *s);
+
+extern const VMStateDescription vmstate_acpi_pcihp_pci_status;
+
+#define VMSTATE_PCI_HOTPLUG(pcihp, state, test_pcihp) \
+        VMSTATE_UINT32_TEST(pcihp.hotplug_select, state, \
+                            test_pcihp), \
+        VMSTATE_STRUCT_ARRAY_TEST(pcihp.acpi_pcihp_pci_status, state, \
+                                  ACPI_PCIHP_MAX_HOTPLUG_BUS, \
+                                  test_pcihp, 1, \
+                                  vmstate_acpi_pcihp_pci_status, \
+                                  AcpiPciHpPciStatus)
+
+#endif
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
new file mode 100644
index 0000000..13938e6
--- /dev/null
+++ b/hw/acpi/pcihp.c
@@ -0,0 +1,312 @@
+/*
+ * QEMU<->ACPI BIOS PCI hotplug interface
+ *
+ * QEMU supports PCI hotplug via ACPI. This module
+ * implements the interface between QEMU and the ACPI BIOS.
+ * Interface specification - see docs/specs/acpi_pci_hotplug.txt
+ *
+ * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
+ */
+
+#include "hw/acpi/pcihp.h"
+
+#include "hw/hw.h"
+#include "hw/i386/pc.h"
+#include "hw/pci/pci.h"
+#include "hw/acpi/acpi.h"
+#include "sysemu/sysemu.h"
+#include "qemu/range.h"
+#include "exec/ioport.h"
+#include "exec/address-spaces.h"
+#include "hw/pci/pci_bus.h"
+#include "qom/qom-qobject.h"
+#include "qapi/qmp/qint.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+# define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
+#else
+# define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
+#endif
+
+#define PCI_HOTPLUG_ADDR 0xae00
+#define PCI_HOTPLUG_SIZE 0x0014
+#define PCI_UP_BASE 0xae00
+#define PCI_DOWN_BASE 0xae04
+#define PCI_EJ_BASE 0xae08
+#define PCI_RMV_BASE 0xae0c
+#define PCI_SEL_BASE 0xae10
+
+typedef struct AcpiPciHpFind {
+    int bsel;
+    PCIBus *bus;
+} AcpiPciHpFind;
+
+static int acpi_pcihp_get_bsel(PCIBus *bus)
+{
+    QObject *o = object_property_get_qobject(OBJECT(bus),
+                                             ACPI_PCIHP_PROP_BSEL, NULL);
+    int64_t bsel = -1;
+    if (o) {
+        bsel = qint_get_int(qobject_to_qint(o));
+    }
+    if (bsel < 0) {
+        return -1;
+    }
+    return bsel;
+}
+
+static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
+{
+    AcpiPciHpFind *find = opaque;
+    if (find->bsel == acpi_pcihp_get_bsel(bus)) {
+        find->bus = bus;
+    }
+}
+
+static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
+{
+    AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
+
+    if (bsel < 0) {
+        return NULL;
+    }
+
+    pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
+
+    if (!bsel && !find.bus) {
+        find.bus = s->root;
+    }
+    return find.bus;
+}
+
+static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
+{
+    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
+    /*
+     * ACPI doesn't allow hotplug of bridge devices.  Don't allow
+     * hot-unplug of bridge devices unless they were added by hotplug
+     * (and so, not described by acpi).
+     */
+    return (pc->is_bridge && !dev->qdev.hotplugged) || pc->no_hotplug;
+}
+
+static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
+{
+    BusChild *kid, *next;
+    int slot = ffs(slots) - 1;
+    bool slot_free = true;
+    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
+
+    if (!bus) {
+        return;
+    }
+
+    /* Mark request as complete */
+    s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
+
+    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
+        DeviceState *qdev = kid->child;
+        PCIDevice *dev = PCI_DEVICE(qdev);
+        if (PCI_SLOT(dev->devfn) == slot) {
+            if (acpi_pcihp_pc_no_hotplug(s, dev)) {
+                slot_free = false;
+            } else {
+                qdev_free(qdev);
+            }
+        }
+    }
+    if (slot_free) {
+        s->acpi_pcihp_pci_status[bsel].device_present &= ~(1U << slot);
+    }
+}
+
+static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
+{
+    BusChild *kid, *next;
+    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
+
+    /* Execute any pending removes during reset */
+    while (s->acpi_pcihp_pci_status[bsel].down) {
+        acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
+    }
+
+    s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
+    s->acpi_pcihp_pci_status[bsel].device_present = 0;
+
+    if (!bus) {
+        return;
+    }
+    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
+        DeviceState *qdev = kid->child;
+        PCIDevice *pdev = PCI_DEVICE(qdev);
+        int slot = PCI_SLOT(pdev->devfn);
+
+        if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
+            s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
+        }
+
+        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
+    }
+}
+
+static void acpi_pcihp_update(AcpiPciHpState *s)
+{
+    int i;
+
+    for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
+        acpi_pcihp_update_hotplug_bus(s, i);
+    }
+}
+
+void acpi_pcihp_reset(AcpiPciHpState *s)
+{
+    acpi_pcihp_update(s);
+}
+
+static void enable_device(AcpiPciHpState *s, unsigned bsel, int slot)
+{
+    s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
+}
+
+static void disable_device(AcpiPciHpState *s, unsigned bsel, int slot)
+{
+    s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
+}
+
+int acpi_pcihp_device_hotplug(AcpiPciHpState *s, PCIDevice *dev,
+                              PCIHotplugState state)
+{
+    int slot = PCI_SLOT(dev->devfn);
+    int bsel = acpi_pcihp_get_bsel(dev->bus);
+    if (bsel < 0) {
+        return -1;
+    }
+
+    /* Don't send event when device is enabled during qemu machine creation:
+     * it is present on boot, no hotplug event is necessary. We do send an
+     * event when the device is disabled later. */
+    if (state == PCI_COLDPLUG_ENABLED) {
+        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
+        return 0;
+    }
+
+    if (state == PCI_HOTPLUG_ENABLED) {
+        enable_device(s, bsel, slot);
+    } else {
+        disable_device(s, bsel, slot);
+    }
+
+    return 0;
+}
+
+static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
+{
+    AcpiPciHpState *s = opaque;
+    uint32_t val = 0;
+    int bsel = s->hotplug_select;
+
+    if (bsel < 0 || bsel > ACPI_PCIHP_MAX_HOTPLUG_BUS) {
+        return 0;
+    }
+
+    switch (addr) {
+    case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
+        /* Manufacture an "up" value to cause a device check on any hotplug
+         * slot with a device.  Extra device checks are harmless. */
+        val = s->acpi_pcihp_pci_status[bsel].device_present &
+            s->acpi_pcihp_pci_status[bsel].hotplug_enable;
+        ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
+        break;
+    case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
+        val = s->acpi_pcihp_pci_status[bsel].down;
+        ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
+        break;
+    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
+        /* No feature defined yet */
+        ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
+        break;
+    case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
+        val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
+        ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
+        break;
+    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
+        val = s->hotplug_select;
+        ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
+    default:
+        break;
+    }
+
+    return val;
+}
+
+static void pci_write(void *opaque, hwaddr addr, uint64_t data,
+                      unsigned int size)
+{
+    AcpiPciHpState *s = opaque;
+    switch (addr) {
+    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
+        if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
+            break;
+        }
+        acpi_pcihp_eject_slot(s, s->hotplug_select, data);
+        ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
+                      addr, data);
+        break;
+    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
+        s->hotplug_select = data;
+        ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
+                      addr, data);
+    default:
+        break;
+    }
+}
+
+static const MemoryRegionOps acpi_pcihp_io_ops = {
+    .read = pci_read,
+    .write = pci_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+};
+
+void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
+                     MemoryRegion *address_space_io)
+{
+    s->root= root_bus;
+    memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
+                          "acpi-pci-hotplug",
+                          PCI_HOTPLUG_SIZE);
+    memory_region_add_subregion(address_space_io, PCI_HOTPLUG_ADDR, &s->io);
+}
+
+const VMStateDescription vmstate_acpi_pcihp_pci_status = {
+    .name = "acpi_pcihp_pci_status",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32(up, AcpiPciHpPciStatus),
+        VMSTATE_UINT32(down, AcpiPciHpPciStatus),
+        VMSTATE_END_OF_LIST()
+    }
+};
diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
index a0b63b5..0a47a53 100644
--- a/hw/acpi/Makefile.objs
+++ b/hw/acpi/Makefile.objs
@@ -1,2 +1,2 @@
-common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o
+common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o
 
-- 
MST

Re: [Qemu-devel] [PULL 41/43] pcihp: generalization of piix4 acpi

[Anthony Liguori]

"Michael S. Tsirkin" <mst@redhat.com> writes:

> Add ACPI based PCI hotplug library with bridge hotplug
> support.
> Design
>    - each bus gets assigned "bsel" property.
>    - ACPI code writes this number
>      to a new BNUM register, then uses existing
>      UP/DOWN registers to probe slot status;
>      to eject, write number to BNUM register,
>      then slot into existing EJ.
>
> The interface is actually backwards-compatible with
> existing PIIX4 ACPI (though not migration compatible).
>
> This is split out from PIIX4 codebase so we can
> reuse it for Q35 as well.

So we break migration for PIIX4 so the code can be reused for Q35?

That doesn't seem acceptable to me.

Regards,

Anthony Liguori

>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
>  include/hw/acpi/pcihp.h |  72 +++++++++++
>  hw/acpi/pcihp.c         | 312 ++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/acpi/Makefile.objs   |   2 +-
>  3 files changed, 385 insertions(+), 1 deletion(-)
>  create mode 100644 include/hw/acpi/pcihp.h
>  create mode 100644 hw/acpi/pcihp.c
>
> diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
> new file mode 100644
> index 0000000..6230e60
> --- /dev/null
> +++ b/include/hw/acpi/pcihp.h
> @@ -0,0 +1,72 @@
> +/*
> + * QEMU<->ACPI BIOS PCI hotplug interface
> + *
> + * QEMU supports PCI hotplug via ACPI. This module
> + * implements the interface between QEMU and the ACPI BIOS.
> + * Interface specification - see docs/specs/acpi_pci_hotplug.txt
> + *
> + * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + *
> + * Contributions after 2012-01-13 are licensed under the terms of the
> + * GNU GPL, version 2 or (at your option) any later version.
> + */
> +
> +#ifndef HW_ACPI_PCIHP_H
> +#define HW_ACPI_PCIHP_H
> +
> +#include <inttypes.h>
> +#include <qemu/typedefs.h>
> +#include "hw/pci/pci.h" /* for PCIHotplugState */
> +
> +typedef struct AcpiPciHpPciStatus {
> +    uint32_t up; /* deprecated, maintained for migration compatibility */
> +    uint32_t down;
> +    uint32_t hotplug_enable;
> +    uint32_t device_present;
> +} AcpiPciHpPciStatus;
> +
> +#define ACPI_PCIHP_PROP_BSEL "acpi-pcihp-bsel"
> +#define ACPI_PCIHP_MAX_HOTPLUG_BUS 256
> +
> +typedef struct AcpiPciHpState {
> +    AcpiPciHpPciStatus acpi_pcihp_pci_status[ACPI_PCIHP_MAX_HOTPLUG_BUS];
> +    uint32_t hotplug_select;
> +    PCIBus *root;
> +    MemoryRegion io;
> +} AcpiPciHpState;
> +
> +void acpi_pcihp_init(AcpiPciHpState *, PCIBus *root,
> +                     MemoryRegion *address_space_io);
> +
> +/* Invoke on device hotplug */
> +int acpi_pcihp_device_hotplug(AcpiPciHpState *, PCIDevice *,
> +                              PCIHotplugState state);
> +
> +/* Called on reset */
> +void acpi_pcihp_reset(AcpiPciHpState *s);
> +
> +extern const VMStateDescription vmstate_acpi_pcihp_pci_status;
> +
> +#define VMSTATE_PCI_HOTPLUG(pcihp, state, test_pcihp) \
> +        VMSTATE_UINT32_TEST(pcihp.hotplug_select, state, \
> +                            test_pcihp), \
> +        VMSTATE_STRUCT_ARRAY_TEST(pcihp.acpi_pcihp_pci_status, state, \
> +                                  ACPI_PCIHP_MAX_HOTPLUG_BUS, \
> +                                  test_pcihp, 1, \
> +                                  vmstate_acpi_pcihp_pci_status, \
> +                                  AcpiPciHpPciStatus)
> +
> +#endif
> diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
> new file mode 100644
> index 0000000..13938e6
> --- /dev/null
> +++ b/hw/acpi/pcihp.c
> @@ -0,0 +1,312 @@
> +/*
> + * QEMU<->ACPI BIOS PCI hotplug interface
> + *
> + * QEMU supports PCI hotplug via ACPI. This module
> + * implements the interface between QEMU and the ACPI BIOS.
> + * Interface specification - see docs/specs/acpi_pci_hotplug.txt
> + *
> + * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + *
> + * Contributions after 2012-01-13 are licensed under the terms of the
> + * GNU GPL, version 2 or (at your option) any later version.
> + */
> +
> +#include "hw/acpi/pcihp.h"
> +
> +#include "hw/hw.h"
> +#include "hw/i386/pc.h"
> +#include "hw/pci/pci.h"
> +#include "hw/acpi/acpi.h"
> +#include "sysemu/sysemu.h"
> +#include "qemu/range.h"
> +#include "exec/ioport.h"
> +#include "exec/address-spaces.h"
> +#include "hw/pci/pci_bus.h"
> +#include "qom/qom-qobject.h"
> +#include "qapi/qmp/qint.h"
> +
> +//#define DEBUG
> +
> +#ifdef DEBUG
> +# define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
> +#else
> +# define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
> +#endif
> +
> +#define PCI_HOTPLUG_ADDR 0xae00
> +#define PCI_HOTPLUG_SIZE 0x0014
> +#define PCI_UP_BASE 0xae00
> +#define PCI_DOWN_BASE 0xae04
> +#define PCI_EJ_BASE 0xae08
> +#define PCI_RMV_BASE 0xae0c
> +#define PCI_SEL_BASE 0xae10
> +
> +typedef struct AcpiPciHpFind {
> +    int bsel;
> +    PCIBus *bus;
> +} AcpiPciHpFind;
> +
> +static int acpi_pcihp_get_bsel(PCIBus *bus)
> +{
> +    QObject *o = object_property_get_qobject(OBJECT(bus),
> +                                             ACPI_PCIHP_PROP_BSEL, NULL);
> +    int64_t bsel = -1;
> +    if (o) {
> +        bsel = qint_get_int(qobject_to_qint(o));
> +    }
> +    if (bsel < 0) {
> +        return -1;
> +    }
> +    return bsel;
> +}
> +
> +static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
> +{
> +    AcpiPciHpFind *find = opaque;
> +    if (find->bsel == acpi_pcihp_get_bsel(bus)) {
> +        find->bus = bus;
> +    }
> +}
> +
> +static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
> +{
> +    AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
> +
> +    if (bsel < 0) {
> +        return NULL;
> +    }
> +
> +    pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
> +
> +    if (!bsel && !find.bus) {
> +        find.bus = s->root;
> +    }
> +    return find.bus;
> +}
> +
> +static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
> +{
> +    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
> +    /*
> +     * ACPI doesn't allow hotplug of bridge devices.  Don't allow
> +     * hot-unplug of bridge devices unless they were added by hotplug
> +     * (and so, not described by acpi).
> +     */
> +    return (pc->is_bridge && !dev->qdev.hotplugged) || pc->no_hotplug;
> +}
> +
> +static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
> +{
> +    BusChild *kid, *next;
> +    int slot = ffs(slots) - 1;
> +    bool slot_free = true;
> +    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
> +
> +    if (!bus) {
> +        return;
> +    }
> +
> +    /* Mark request as complete */
> +    s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
> +
> +    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
> +        DeviceState *qdev = kid->child;
> +        PCIDevice *dev = PCI_DEVICE(qdev);
> +        if (PCI_SLOT(dev->devfn) == slot) {
> +            if (acpi_pcihp_pc_no_hotplug(s, dev)) {
> +                slot_free = false;
> +            } else {
> +                qdev_free(qdev);
> +            }
> +        }
> +    }
> +    if (slot_free) {
> +        s->acpi_pcihp_pci_status[bsel].device_present &= ~(1U << slot);
> +    }
> +}
> +
> +static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
> +{
> +    BusChild *kid, *next;
> +    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
> +
> +    /* Execute any pending removes during reset */
> +    while (s->acpi_pcihp_pci_status[bsel].down) {
> +        acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
> +    }
> +
> +    s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
> +    s->acpi_pcihp_pci_status[bsel].device_present = 0;
> +
> +    if (!bus) {
> +        return;
> +    }
> +    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
> +        DeviceState *qdev = kid->child;
> +        PCIDevice *pdev = PCI_DEVICE(qdev);
> +        int slot = PCI_SLOT(pdev->devfn);
> +
> +        if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
> +            s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
> +        }
> +
> +        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> +    }
> +}
> +
> +static void acpi_pcihp_update(AcpiPciHpState *s)
> +{
> +    int i;
> +
> +    for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
> +        acpi_pcihp_update_hotplug_bus(s, i);
> +    }
> +}
> +
> +void acpi_pcihp_reset(AcpiPciHpState *s)
> +{
> +    acpi_pcihp_update(s);
> +}
> +
> +static void enable_device(AcpiPciHpState *s, unsigned bsel, int slot)
> +{
> +    s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> +}
> +
> +static void disable_device(AcpiPciHpState *s, unsigned bsel, int slot)
> +{
> +    s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
> +}
> +
> +int acpi_pcihp_device_hotplug(AcpiPciHpState *s, PCIDevice *dev,
> +                              PCIHotplugState state)
> +{
> +    int slot = PCI_SLOT(dev->devfn);
> +    int bsel = acpi_pcihp_get_bsel(dev->bus);
> +    if (bsel < 0) {
> +        return -1;
> +    }
> +
> +    /* Don't send event when device is enabled during qemu machine creation:
> +     * it is present on boot, no hotplug event is necessary. We do send an
> +     * event when the device is disabled later. */
> +    if (state == PCI_COLDPLUG_ENABLED) {
> +        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> +        return 0;
> +    }
> +
> +    if (state == PCI_HOTPLUG_ENABLED) {
> +        enable_device(s, bsel, slot);
> +    } else {
> +        disable_device(s, bsel, slot);
> +    }
> +
> +    return 0;
> +}
> +
> +static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
> +{
> +    AcpiPciHpState *s = opaque;
> +    uint32_t val = 0;
> +    int bsel = s->hotplug_select;
> +
> +    if (bsel < 0 || bsel > ACPI_PCIHP_MAX_HOTPLUG_BUS) {
> +        return 0;
> +    }
> +
> +    switch (addr) {
> +    case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
> +        /* Manufacture an "up" value to cause a device check on any hotplug
> +         * slot with a device.  Extra device checks are harmless. */
> +        val = s->acpi_pcihp_pci_status[bsel].device_present &
> +            s->acpi_pcihp_pci_status[bsel].hotplug_enable;
> +        ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
> +        break;
> +    case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
> +        val = s->acpi_pcihp_pci_status[bsel].down;
> +        ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
> +        break;
> +    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
> +        /* No feature defined yet */
> +        ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
> +        break;
> +    case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
> +        val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
> +        ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
> +        break;
> +    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
> +        val = s->hotplug_select;
> +        ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
> +    default:
> +        break;
> +    }
> +
> +    return val;
> +}
> +
> +static void pci_write(void *opaque, hwaddr addr, uint64_t data,
> +                      unsigned int size)
> +{
> +    AcpiPciHpState *s = opaque;
> +    switch (addr) {
> +    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
> +        if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
> +            break;
> +        }
> +        acpi_pcihp_eject_slot(s, s->hotplug_select, data);
> +        ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
> +                      addr, data);
> +        break;
> +    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
> +        s->hotplug_select = data;
> +        ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
> +                      addr, data);
> +    default:
> +        break;
> +    }
> +}
> +
> +static const MemoryRegionOps acpi_pcihp_io_ops = {
> +    .read = pci_read,
> +    .write = pci_write,
> +    .endianness = DEVICE_LITTLE_ENDIAN,
> +    .valid = {
> +        .min_access_size = 4,
> +        .max_access_size = 4,
> +    },
> +};
> +
> +void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
> +                     MemoryRegion *address_space_io)
> +{
> +    s->root= root_bus;
> +    memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
> +                          "acpi-pci-hotplug",
> +                          PCI_HOTPLUG_SIZE);
> +    memory_region_add_subregion(address_space_io, PCI_HOTPLUG_ADDR, &s->io);
> +}
> +
> +const VMStateDescription vmstate_acpi_pcihp_pci_status = {
> +    .name = "acpi_pcihp_pci_status",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .minimum_version_id_old = 1,
> +    .fields      = (VMStateField []) {
> +        VMSTATE_UINT32(up, AcpiPciHpPciStatus),
> +        VMSTATE_UINT32(down, AcpiPciHpPciStatus),
> +        VMSTATE_END_OF_LIST()
> +    }
> +};
> diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
> index a0b63b5..0a47a53 100644
> --- a/hw/acpi/Makefile.objs
> +++ b/hw/acpi/Makefile.objs
> @@ -1,2 +1,2 @@
> -common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o
> +common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o
>  
> -- 
> MST

Re: [Qemu-devel] [PULL 41/43] pcihp: generalization of piix4 acpi

[Michael S. Tsirkin]

On Mon, Oct 14, 2013 at 03:36:13PM -0700, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > Add ACPI based PCI hotplug library with bridge hotplug
> > support.
> > Design
> >    - each bus gets assigned "bsel" property.
> >    - ACPI code writes this number
> >      to a new BNUM register, then uses existing
> >      UP/DOWN registers to probe slot status;
> >      to eject, write number to BNUM register,
> >      then slot into existing EJ.
> >
> > The interface is actually backwards-compatible with
> > existing PIIX4 ACPI (though not migration compatible).
> >
> > This is split out from PIIX4 codebase so we can
> > reuse it for Q35 as well.
> 
> So we break migration for PIIX4 so the code can be reused for Q35?

No we don't: for -M 1.6 machine type this is disabled
and we use the old code.

> That doesn't seem acceptable to me.
> 
> Regards,
> 
> Anthony Liguori
> 
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> >  include/hw/acpi/pcihp.h |  72 +++++++++++
> >  hw/acpi/pcihp.c         | 312 ++++++++++++++++++++++++++++++++++++++++++++++++
> >  hw/acpi/Makefile.objs   |   2 +-
> >  3 files changed, 385 insertions(+), 1 deletion(-)
> >  create mode 100644 include/hw/acpi/pcihp.h
> >  create mode 100644 hw/acpi/pcihp.c
> >
> > diff --git a/include/hw/acpi/pcihp.h b/include/hw/acpi/pcihp.h
> > new file mode 100644
> > index 0000000..6230e60
> > --- /dev/null
> > +++ b/include/hw/acpi/pcihp.h
> > @@ -0,0 +1,72 @@
> > +/*
> > + * QEMU<->ACPI BIOS PCI hotplug interface
> > + *
> > + * QEMU supports PCI hotplug via ACPI. This module
> > + * implements the interface between QEMU and the ACPI BIOS.
> > + * Interface specification - see docs/specs/acpi_pci_hotplug.txt
> > + *
> > + * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
> > + * Copyright (c) 2006 Fabrice Bellard
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License version 2 as published by the Free Software Foundation.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > + *
> > + * Contributions after 2012-01-13 are licensed under the terms of the
> > + * GNU GPL, version 2 or (at your option) any later version.
> > + */
> > +
> > +#ifndef HW_ACPI_PCIHP_H
> > +#define HW_ACPI_PCIHP_H
> > +
> > +#include <inttypes.h>
> > +#include <qemu/typedefs.h>
> > +#include "hw/pci/pci.h" /* for PCIHotplugState */
> > +
> > +typedef struct AcpiPciHpPciStatus {
> > +    uint32_t up; /* deprecated, maintained for migration compatibility */
> > +    uint32_t down;
> > +    uint32_t hotplug_enable;
> > +    uint32_t device_present;
> > +} AcpiPciHpPciStatus;
> > +
> > +#define ACPI_PCIHP_PROP_BSEL "acpi-pcihp-bsel"
> > +#define ACPI_PCIHP_MAX_HOTPLUG_BUS 256
> > +
> > +typedef struct AcpiPciHpState {
> > +    AcpiPciHpPciStatus acpi_pcihp_pci_status[ACPI_PCIHP_MAX_HOTPLUG_BUS];
> > +    uint32_t hotplug_select;
> > +    PCIBus *root;
> > +    MemoryRegion io;
> > +} AcpiPciHpState;
> > +
> > +void acpi_pcihp_init(AcpiPciHpState *, PCIBus *root,
> > +                     MemoryRegion *address_space_io);
> > +
> > +/* Invoke on device hotplug */
> > +int acpi_pcihp_device_hotplug(AcpiPciHpState *, PCIDevice *,
> > +                              PCIHotplugState state);
> > +
> > +/* Called on reset */
> > +void acpi_pcihp_reset(AcpiPciHpState *s);
> > +
> > +extern const VMStateDescription vmstate_acpi_pcihp_pci_status;
> > +
> > +#define VMSTATE_PCI_HOTPLUG(pcihp, state, test_pcihp) \
> > +        VMSTATE_UINT32_TEST(pcihp.hotplug_select, state, \
> > +                            test_pcihp), \
> > +        VMSTATE_STRUCT_ARRAY_TEST(pcihp.acpi_pcihp_pci_status, state, \
> > +                                  ACPI_PCIHP_MAX_HOTPLUG_BUS, \
> > +                                  test_pcihp, 1, \
> > +                                  vmstate_acpi_pcihp_pci_status, \
> > +                                  AcpiPciHpPciStatus)
> > +
> > +#endif
> > diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
> > new file mode 100644
> > index 0000000..13938e6
> > --- /dev/null
> > +++ b/hw/acpi/pcihp.c
> > @@ -0,0 +1,312 @@
> > +/*
> > + * QEMU<->ACPI BIOS PCI hotplug interface
> > + *
> > + * QEMU supports PCI hotplug via ACPI. This module
> > + * implements the interface between QEMU and the ACPI BIOS.
> > + * Interface specification - see docs/specs/acpi_pci_hotplug.txt
> > + *
> > + * Copyright (c) 2013, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
> > + * Copyright (c) 2006 Fabrice Bellard
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License version 2 as published by the Free Software Foundation.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > + *
> > + * Contributions after 2012-01-13 are licensed under the terms of the
> > + * GNU GPL, version 2 or (at your option) any later version.
> > + */
> > +
> > +#include "hw/acpi/pcihp.h"
> > +
> > +#include "hw/hw.h"
> > +#include "hw/i386/pc.h"
> > +#include "hw/pci/pci.h"
> > +#include "hw/acpi/acpi.h"
> > +#include "sysemu/sysemu.h"
> > +#include "qemu/range.h"
> > +#include "exec/ioport.h"
> > +#include "exec/address-spaces.h"
> > +#include "hw/pci/pci_bus.h"
> > +#include "qom/qom-qobject.h"
> > +#include "qapi/qmp/qint.h"
> > +
> > +//#define DEBUG
> > +
> > +#ifdef DEBUG
> > +# define ACPI_PCIHP_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
> > +#else
> > +# define ACPI_PCIHP_DPRINTF(format, ...)     do { } while (0)
> > +#endif
> > +
> > +#define PCI_HOTPLUG_ADDR 0xae00
> > +#define PCI_HOTPLUG_SIZE 0x0014
> > +#define PCI_UP_BASE 0xae00
> > +#define PCI_DOWN_BASE 0xae04
> > +#define PCI_EJ_BASE 0xae08
> > +#define PCI_RMV_BASE 0xae0c
> > +#define PCI_SEL_BASE 0xae10
> > +
> > +typedef struct AcpiPciHpFind {
> > +    int bsel;
> > +    PCIBus *bus;
> > +} AcpiPciHpFind;
> > +
> > +static int acpi_pcihp_get_bsel(PCIBus *bus)
> > +{
> > +    QObject *o = object_property_get_qobject(OBJECT(bus),
> > +                                             ACPI_PCIHP_PROP_BSEL, NULL);
> > +    int64_t bsel = -1;
> > +    if (o) {
> > +        bsel = qint_get_int(qobject_to_qint(o));
> > +    }
> > +    if (bsel < 0) {
> > +        return -1;
> > +    }
> > +    return bsel;
> > +}
> > +
> > +static void acpi_pcihp_test_hotplug_bus(PCIBus *bus, void *opaque)
> > +{
> > +    AcpiPciHpFind *find = opaque;
> > +    if (find->bsel == acpi_pcihp_get_bsel(bus)) {
> > +        find->bus = bus;
> > +    }
> > +}
> > +
> > +static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel)
> > +{
> > +    AcpiPciHpFind find = { .bsel = bsel, .bus = NULL };
> > +
> > +    if (bsel < 0) {
> > +        return NULL;
> > +    }
> > +
> > +    pci_for_each_bus(s->root, acpi_pcihp_test_hotplug_bus, &find);
> > +
> > +    if (!bsel && !find.bus) {
> > +        find.bus = s->root;
> > +    }
> > +    return find.bus;
> > +}
> > +
> > +static bool acpi_pcihp_pc_no_hotplug(AcpiPciHpState *s, PCIDevice *dev)
> > +{
> > +    PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
> > +    /*
> > +     * ACPI doesn't allow hotplug of bridge devices.  Don't allow
> > +     * hot-unplug of bridge devices unless they were added by hotplug
> > +     * (and so, not described by acpi).
> > +     */
> > +    return (pc->is_bridge && !dev->qdev.hotplugged) || pc->no_hotplug;
> > +}
> > +
> > +static void acpi_pcihp_eject_slot(AcpiPciHpState *s, unsigned bsel, unsigned slots)
> > +{
> > +    BusChild *kid, *next;
> > +    int slot = ffs(slots) - 1;
> > +    bool slot_free = true;
> > +    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
> > +
> > +    if (!bus) {
> > +        return;
> > +    }
> > +
> > +    /* Mark request as complete */
> > +    s->acpi_pcihp_pci_status[bsel].down &= ~(1U << slot);
> > +
> > +    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
> > +        DeviceState *qdev = kid->child;
> > +        PCIDevice *dev = PCI_DEVICE(qdev);
> > +        if (PCI_SLOT(dev->devfn) == slot) {
> > +            if (acpi_pcihp_pc_no_hotplug(s, dev)) {
> > +                slot_free = false;
> > +            } else {
> > +                qdev_free(qdev);
> > +            }
> > +        }
> > +    }
> > +    if (slot_free) {
> > +        s->acpi_pcihp_pci_status[bsel].device_present &= ~(1U << slot);
> > +    }
> > +}
> > +
> > +static void acpi_pcihp_update_hotplug_bus(AcpiPciHpState *s, int bsel)
> > +{
> > +    BusChild *kid, *next;
> > +    PCIBus *bus = acpi_pcihp_find_hotplug_bus(s, bsel);
> > +
> > +    /* Execute any pending removes during reset */
> > +    while (s->acpi_pcihp_pci_status[bsel].down) {
> > +        acpi_pcihp_eject_slot(s, bsel, s->acpi_pcihp_pci_status[bsel].down);
> > +    }
> > +
> > +    s->acpi_pcihp_pci_status[bsel].hotplug_enable = ~0;
> > +    s->acpi_pcihp_pci_status[bsel].device_present = 0;
> > +
> > +    if (!bus) {
> > +        return;
> > +    }
> > +    QTAILQ_FOREACH_SAFE(kid, &bus->qbus.children, sibling, next) {
> > +        DeviceState *qdev = kid->child;
> > +        PCIDevice *pdev = PCI_DEVICE(qdev);
> > +        int slot = PCI_SLOT(pdev->devfn);
> > +
> > +        if (acpi_pcihp_pc_no_hotplug(s, pdev)) {
> > +            s->acpi_pcihp_pci_status[bsel].hotplug_enable &= ~(1U << slot);
> > +        }
> > +
> > +        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> > +    }
> > +}
> > +
> > +static void acpi_pcihp_update(AcpiPciHpState *s)
> > +{
> > +    int i;
> > +
> > +    for (i = 0; i < ACPI_PCIHP_MAX_HOTPLUG_BUS; ++i) {
> > +        acpi_pcihp_update_hotplug_bus(s, i);
> > +    }
> > +}
> > +
> > +void acpi_pcihp_reset(AcpiPciHpState *s)
> > +{
> > +    acpi_pcihp_update(s);
> > +}
> > +
> > +static void enable_device(AcpiPciHpState *s, unsigned bsel, int slot)
> > +{
> > +    s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> > +}
> > +
> > +static void disable_device(AcpiPciHpState *s, unsigned bsel, int slot)
> > +{
> > +    s->acpi_pcihp_pci_status[bsel].down |= (1U << slot);
> > +}
> > +
> > +int acpi_pcihp_device_hotplug(AcpiPciHpState *s, PCIDevice *dev,
> > +                              PCIHotplugState state)
> > +{
> > +    int slot = PCI_SLOT(dev->devfn);
> > +    int bsel = acpi_pcihp_get_bsel(dev->bus);
> > +    if (bsel < 0) {
> > +        return -1;
> > +    }
> > +
> > +    /* Don't send event when device is enabled during qemu machine creation:
> > +     * it is present on boot, no hotplug event is necessary. We do send an
> > +     * event when the device is disabled later. */
> > +    if (state == PCI_COLDPLUG_ENABLED) {
> > +        s->acpi_pcihp_pci_status[bsel].device_present |= (1U << slot);
> > +        return 0;
> > +    }
> > +
> > +    if (state == PCI_HOTPLUG_ENABLED) {
> > +        enable_device(s, bsel, slot);
> > +    } else {
> > +        disable_device(s, bsel, slot);
> > +    }
> > +
> > +    return 0;
> > +}
> > +
> > +static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
> > +{
> > +    AcpiPciHpState *s = opaque;
> > +    uint32_t val = 0;
> > +    int bsel = s->hotplug_select;
> > +
> > +    if (bsel < 0 || bsel > ACPI_PCIHP_MAX_HOTPLUG_BUS) {
> > +        return 0;
> > +    }
> > +
> > +    switch (addr) {
> > +    case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
> > +        /* Manufacture an "up" value to cause a device check on any hotplug
> > +         * slot with a device.  Extra device checks are harmless. */
> > +        val = s->acpi_pcihp_pci_status[bsel].device_present &
> > +            s->acpi_pcihp_pci_status[bsel].hotplug_enable;
> > +        ACPI_PCIHP_DPRINTF("pci_up_read %" PRIu32 "\n", val);
> > +        break;
> > +    case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
> > +        val = s->acpi_pcihp_pci_status[bsel].down;
> > +        ACPI_PCIHP_DPRINTF("pci_down_read %" PRIu32 "\n", val);
> > +        break;
> > +    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
> > +        /* No feature defined yet */
> > +        ACPI_PCIHP_DPRINTF("pci_features_read %" PRIu32 "\n", val);
> > +        break;
> > +    case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
> > +        val = s->acpi_pcihp_pci_status[bsel].hotplug_enable;
> > +        ACPI_PCIHP_DPRINTF("pci_rmv_read %" PRIu32 "\n", val);
> > +        break;
> > +    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
> > +        val = s->hotplug_select;
> > +        ACPI_PCIHP_DPRINTF("pci_sel_read %" PRIu32 "\n", val);
> > +    default:
> > +        break;
> > +    }
> > +
> > +    return val;
> > +}
> > +
> > +static void pci_write(void *opaque, hwaddr addr, uint64_t data,
> > +                      unsigned int size)
> > +{
> > +    AcpiPciHpState *s = opaque;
> > +    switch (addr) {
> > +    case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
> > +        if (s->hotplug_select >= ACPI_PCIHP_MAX_HOTPLUG_BUS) {
> > +            break;
> > +        }
> > +        acpi_pcihp_eject_slot(s, s->hotplug_select, data);
> > +        ACPI_PCIHP_DPRINTF("pciej write %" HWADDR_PRIx " <== %" PRIu64 "\n",
> > +                      addr, data);
> > +        break;
> > +    case PCI_SEL_BASE - PCI_HOTPLUG_ADDR:
> > +        s->hotplug_select = data;
> > +        ACPI_PCIHP_DPRINTF("pcisel write %" HWADDR_PRIx " <== %" PRIu64 "\n",
> > +                      addr, data);
> > +    default:
> > +        break;
> > +    }
> > +}
> > +
> > +static const MemoryRegionOps acpi_pcihp_io_ops = {
> > +    .read = pci_read,
> > +    .write = pci_write,
> > +    .endianness = DEVICE_LITTLE_ENDIAN,
> > +    .valid = {
> > +        .min_access_size = 4,
> > +        .max_access_size = 4,
> > +    },
> > +};
> > +
> > +void acpi_pcihp_init(AcpiPciHpState *s, PCIBus *root_bus,
> > +                     MemoryRegion *address_space_io)
> > +{
> > +    s->root= root_bus;
> > +    memory_region_init_io(&s->io, NULL, &acpi_pcihp_io_ops, s,
> > +                          "acpi-pci-hotplug",
> > +                          PCI_HOTPLUG_SIZE);
> > +    memory_region_add_subregion(address_space_io, PCI_HOTPLUG_ADDR, &s->io);
> > +}
> > +
> > +const VMStateDescription vmstate_acpi_pcihp_pci_status = {
> > +    .name = "acpi_pcihp_pci_status",
> > +    .version_id = 1,
> > +    .minimum_version_id = 1,
> > +    .minimum_version_id_old = 1,
> > +    .fields      = (VMStateField []) {
> > +        VMSTATE_UINT32(up, AcpiPciHpPciStatus),
> > +        VMSTATE_UINT32(down, AcpiPciHpPciStatus),
> > +        VMSTATE_END_OF_LIST()
> > +    }
> > +};
> > diff --git a/hw/acpi/Makefile.objs b/hw/acpi/Makefile.objs
> > index a0b63b5..0a47a53 100644
> > --- a/hw/acpi/Makefile.objs
> > +++ b/hw/acpi/Makefile.objs
> > @@ -1,2 +1,2 @@
> > -common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o
> > +common-obj-$(CONFIG_ACPI) += core.o piix4.o ich9.o pcihp.o
> >  
> > -- 
> > MST

[Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

Add support for acpi pci hotplug using the
new infrastructure.
PIIX4 legacy interface is maintained as is for
machine types 1.6 and older.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 include/hw/i386/pc.h |  5 ++++
 hw/acpi/piix4.c      | 75 +++++++++++++++++++++++++++++++++++++++++++++-------
 2 files changed, 70 insertions(+), 10 deletions(-)

diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 39db8cb..6865972 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -249,6 +249,11 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
 
 #define PC_COMPAT_1_6 \
         {\
+            .driver   = "PIIX4_PM",\
+            .property = "acpi-pci-hotplug-with-bridge-support",\
+            .value    = "off",\
+        }, \
+        {\
             .driver   = "e1000",\
             .property = "mitigation",\
             .value    = "off",\
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 3bcd890..d516033 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -30,6 +30,7 @@
 #include "hw/nvram/fw_cfg.h"
 #include "exec/address-spaces.h"
 #include "hw/acpi/piix4.h"
+#include "hw/acpi/pcihp.h"
 
 //#define DEBUG
 
@@ -73,7 +74,6 @@ typedef struct PIIX4PMState {
     uint32_t io_base;
 
     MemoryRegion io_gpe;
-    MemoryRegion io_pci;
     MemoryRegion io_cpu;
     ACPIREGS ar;
 
@@ -88,11 +88,16 @@ typedef struct PIIX4PMState {
     Notifier machine_ready;
     Notifier powerdown_notifier;
 
-    /* for pci hotplug */
+    /* for legacy pci hotplug (compatible with qemu 1.6 and older) */
+    MemoryRegion io_pci;
     struct pci_status pci0_status;
     uint32_t pci0_hotplug_enable;
     uint32_t pci0_slot_device_present;
 
+    /* for new pci hotplug (with PCI2PCI bridge support) */
+    AcpiPciHpState acpi_pci_hotplug;
+    bool use_acpi_pci_hotplug;
+
     uint8_t disable_s3;
     uint8_t disable_s4;
     uint8_t s4_val;
@@ -282,6 +287,18 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
     return ret;
 }
 
+static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
+{
+    PIIX4PMState *s = opaque;
+    return s->use_acpi_pci_hotplug;
+}
+
+static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
+{
+    PIIX4PMState *s = opaque;
+    return !s->use_acpi_pci_hotplug;
+}
+
 /* qemu-kvm 1.2 uses version 3 but advertised as 2
  * To support incoming qemu-kvm 1.2 migration, change version_id
  * and minimum_version_id to 2 below (which breaks migration from
@@ -304,8 +321,12 @@ static const VMStateDescription vmstate_acpi = {
         VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
         VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
         VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
-        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
-                       struct pci_status),
+        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
+                            vmstate_test_no_use_acpi_pci_hotplug,
+                            2, vmstate_pci_status,
+                            struct pci_status),
+        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
+                            vmstate_test_use_acpi_pci_hotplug),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -383,7 +404,11 @@ static void piix4_reset(void *opaque)
         pci_conf[0x5B] = 0x02;
     }
     pm_io_space_update(s);
-    piix4_update_hotplug(s);
+    if (s->use_acpi_pci_hotplug) {
+        acpi_pcihp_reset(&s->acpi_pci_hotplug);
+    } else {
+        piix4_update_hotplug(s);
+    }
 }
 
 static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
@@ -394,6 +419,26 @@ static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
     acpi_pm1_evt_power_down(&s->ar);
 }
 
+static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev,
+                                  PCIHotplugState state)
+{
+    PIIX4PMState *s = PIIX4_PM(qdev);
+    int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state);
+    if (ret < 0) {
+        return ret;
+    }
+    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
+
+    pm_update_sci(s);
+    return 0;
+}
+
+static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque)
+{
+    PIIX4PMState *s = opaque;
+    pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s));
+}
+
 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 {
     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
@@ -407,6 +452,10 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
     pci_conf[0x63] = 0x60;
     pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
         (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
+
+    if (s->use_acpi_pci_hotplug) {
+        pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
+    }
 }
 
 static void piix4_pm_add_propeties(PIIX4PMState *s)
@@ -528,6 +577,8 @@ static Property piix4_pm_properties[] = {
     DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
     DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
+    DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
+                     use_acpi_pci_hotplug, true),
     DEFINE_PROP_END_OF_LIST(),
 };
 
@@ -716,11 +767,15 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
                           "acpi-gpe0", GPE_LEN);
     memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
 
-    memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
-                          "acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
-    memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
-                                &s->io_pci);
-    pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
+    if (s->use_acpi_pci_hotplug) {
+        acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent);
+    } else {
+        memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
+                              "acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
+        memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
+                                    &s->io_pci);
+        pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
+    }
 
     CPU_FOREACH(cpu) {
         CPUClass *cc = CPU_GET_CLASS(cpu);
-- 
MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> -                       struct pci_status),
> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> +                            vmstate_test_no_use_acpi_pci_hotplug,
> +                            2, vmstate_pci_status,
> +                            struct pci_status),

There's no reason to remove this from the stream when a new machine type
is in use.  You'll just send out zeroes.

> +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
> +                            vmstate_test_use_acpi_pci_hotplug),

This works, but it is a bit different from other cases that are already
present, which use a subsection.  It is a bit ugly because it looks like
a version-1 field, but in fact it is not version 1.

I'll let other people decide whether it's acceptable or not, but I'm
leaning towards asking you to use a subsection.

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> > -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> > -                       struct pci_status),
> > +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> > +                            vmstate_test_no_use_acpi_pci_hotplug,
> > +                            2, vmstate_pci_status,
> > +                            struct pci_status),
> 
> There's no reason to remove this from the stream when a new machine type
> is in use.  You'll just send out zeroes.

Seemed cleaner not to.

> > +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
> > +                            vmstate_test_use_acpi_pci_hotplug),
> 
> This works, but it is a bit different from other cases that are already
> present, which use a subsection.  It is a bit ugly because it looks like
> a version-1 field, but in fact it is not version 1.
> 
> I'll let other people decide whether it's acceptable or not, but I'm
> leaning towards asking you to use a subsection.
> 
> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
>>> -                       struct pci_status),
>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
>>> +                            2, vmstate_pci_status,
>>> +                            struct pci_status),
>>
>> There's no reason to remove this from the stream when a new machine type
>> is in use.  You'll just send out zeroes.
> 
> Seemed cleaner not to.

It certainly would be if we had a self-descriptive migration stream format.

However, what we have is "send bytes, parse them on the destination,
hope the format matches".  Hence, anything that makes the format less
declarative adds to the complication and complicates debugging.  This is
the same reason why I prefer a subsection for the new hotplug stuff---it
makes the format more declarative and self-descriptive.

Paolo

>>> +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
>>> +                            vmstate_test_use_acpi_pci_hotplug),
>>
>> This works, but it is a bit different from other cases that are already
>> present, which use a subsection.  It is a bit ugly because it looks like
>> a version-1 field, but in fact it is not version 1.
>>
>> I'll let other people decide whether it's acceptable or not, but I'm
>> leaning towards asking you to use a subsection.
>>
>> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 04:50:24PM +0200, Paolo Bonzini wrote:
> Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
> > On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
> >> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> >>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> >>> -                       struct pci_status),
> >>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> >>> +                            vmstate_test_no_use_acpi_pci_hotplug,
> >>> +                            2, vmstate_pci_status,
> >>> +                            struct pci_status),
> >>
> >> There's no reason to remove this from the stream when a new machine type
> >> is in use.  You'll just send out zeroes.
> > 
> > Seemed cleaner not to.
> 
> It certainly would be if we had a self-descriptive migration stream format.
> 
> However, what we have is "send bytes, parse them on the destination,
> hope the format matches".  Hence, anything that makes the format less
> declarative adds to the complication and complicates debugging.  This is
> the same reason why I prefer a subsection for the new hotplug stuff---it
> makes the format more declarative and self-descriptive.
> 
> Paolo

I understand for the subsection but why is removing
useless bytes from there making it less descriptive?

> >>> +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
> >>> +                            vmstate_test_use_acpi_pci_hotplug),
> >>
> >> This works, but it is a bit different from other cases that are already
> >> present, which use a subsection.  It is a bit ugly because it looks like
> >> a version-1 field, but in fact it is not version 1.
> >>
> >> I'll let other people decide whether it's acceptable or not, but I'm
> >> leaning towards asking you to use a subsection.
> >>
> >> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 15/10/2013 16:54, Michael S. Tsirkin ha scritto:
> > > Seemed cleaner not to.
> > 
> > It certainly would be if we had a self-descriptive migration stream format.
> > 
> > However, what we have is "send bytes, parse them on the destination,
> > hope the format matches".  Hence, anything that makes the format less
> > declarative adds to the complication and complicates debugging.  This is
> > the same reason why I prefer a subsection for the new hotplug stuff---it
> > makes the format more declarative and self-descriptive.
> 
> I understand for the subsection but why is removing
> useless bytes from there making it less descriptive?

Because the same version can have multiple formats depending on a datum
that is not part of the migration stream.

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 04:54:24PM +0200, Paolo Bonzini wrote:
> Il 15/10/2013 16:54, Michael S. Tsirkin ha scritto:
> > > > Seemed cleaner not to.
> > > 
> > > It certainly would be if we had a self-descriptive migration stream format.
> > > 
> > > However, what we have is "send bytes, parse them on the destination,
> > > hope the format matches".  Hence, anything that makes the format less
> > > declarative adds to the complication and complicates debugging.  This is
> > > the same reason why I prefer a subsection for the new hotplug stuff---it
> > > makes the format more declarative and self-descriptive.
> > 
> > I understand for the subsection but why is removing
> > useless bytes from there making it less descriptive?
> 
> Because the same version can have multiple formats depending on a datum
> that is not part of the migration stream.
> 
> Paolo

I see. Will it be OK if I'll update the version?

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 15/10/2013 17:07, Michael S. Tsirkin ha scritto:
> > Because the same version can have multiple formats depending on a datum
> > that is not part of the migration stream.
> 
> I see. Will it be OK if I'll update the version?

The version is constant, you cannot change it depending on which PCI
flavor you have.  If you use subsection (present if and only if
new-style hotplug is active) and leave pci0_hotplug always there it's okay.

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 05:09:36PM +0200, Paolo Bonzini wrote:
> Il 15/10/2013 17:07, Michael S. Tsirkin ha scritto:
> > > Because the same version can have multiple formats depending on a datum
> > > that is not part of the migration stream.
> > 
> > I see. Will it be OK if I'll update the version?
> 
> The version is constant, you cannot change it depending on which PCI
> flavor you have.  If you use subsection (present if and only if
> new-style hotplug is active) and leave pci0_hotplug always there it's okay.
> 
> Paolo

OK I can do that, thanks.

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Anthony Liguori]

Paolo Bonzini <pbonzini@redhat.com> writes:

> Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
>> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
>>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
>>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
>>>> -                       struct pci_status),
>>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
>>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
>>>> +                            2, vmstate_pci_status,
>>>> +                            struct pci_status),
>>>
>>> There's no reason to remove this from the stream when a new machine type
>>> is in use.  You'll just send out zeroes.
>> 
>> Seemed cleaner not to.
>
> It certainly would be if we had a self-descriptive migration stream
> format.

Yes, removing tests is always a good thing.

But I think subsections should always be used when they can.  We should
not break compatibility (even if we technical don't guarantee it) unless
we absolutely have to.

Regards,

Anthony Liguori

>
> However, what we have is "send bytes, parse them on the destination,
> hope the format matches".  Hence, anything that makes the format less
> declarative adds to the complication and complicates debugging.  This is
> the same reason why I prefer a subsection for the new hotplug stuff---it
> makes the format more declarative and self-descriptive.
>
> Paolo
>
>>>> +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
>>>> +                            vmstate_test_use_acpi_pci_hotplug),
>>>
>>> This works, but it is a bit different from other cases that are already
>>> present, which use a subsection.  It is a bit ugly because it looks like
>>> a version-1 field, but in fact it is not version 1.
>>>
>>> I'll let other people decide whether it's acceptable or not, but I'm
>>> leaning towards asking you to use a subsection.
>>>
>>> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 09:27:33AM -0700, Anthony Liguori wrote:
> Paolo Bonzini <pbonzini@redhat.com> writes:
> 
> > Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
> >> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
> >>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> >>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> >>>> -                       struct pci_status),
> >>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> >>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
> >>>> +                            2, vmstate_pci_status,
> >>>> +                            struct pci_status),
> >>>
> >>> There's no reason to remove this from the stream when a new machine type
> >>> is in use.  You'll just send out zeroes.
> >> 
> >> Seemed cleaner not to.
> >
> > It certainly would be if we had a self-descriptive migration stream
> > format.
> 
> Yes, removing tests is always a good thing.
> 
> But I think subsections should always be used when they can.  We should
> not break compatibility (even if we technical don't guarantee it) unless
> we absolutely have to.
> 
> Regards,
> 
> Anthony Liguori

OK so I can interpret this in 2 ways wrt bridge hotplug:
- it's in shape for 1.7 except the migration which should use
  subsections (and needs cross-version testing)
- it's not in shape for 1.7

Can you tell me which it is please?

If it's 1 I'll repost a version with tweaked
migration format and cross-version testing report, tomorrow.

If it's 2 I'd rather work on this after the forum, I still
need to make some travel arrangements.

Paolo? Anthony?

-- 
MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 15/10/2013 22:17, Michael S. Tsirkin ha scritto:
> OK so I can interpret this in 2 ways wrt bridge hotplug:
> - it's in shape for 1.7 except the migration which should use
>   subsections (and needs cross-version testing)
> - it's not in shape for 1.7
> 
> Can you tell me which it is please?
> 
> If it's 1 I'll repost a version with tweaked
> migration format and cross-version testing report, tomorrow.
> 
> If it's 2 I'd rather work on this after the forum, I still
> need to make some travel arrangements.
> 
> Paolo? Anthony?

I honestly didn't look at the patches too much except now that Anthony
and you were discussing migration, and won't claim I understand them
well.  But if you want my opinion, I'll trust you that the spec makes
sense and I'll say that for me it's (1).

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Anthony Liguori]

On Tue, Oct 15, 2013 at 1:17 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Tue, Oct 15, 2013 at 09:27:33AM -0700, Anthony Liguori wrote:
>> Paolo Bonzini <pbonzini@redhat.com> writes:
>>
>> > Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
>> >> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
>> >>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
>> >>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
>> >>>> -                       struct pci_status),
>> >>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
>> >>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
>> >>>> +                            2, vmstate_pci_status,
>> >>>> +                            struct pci_status),
>> >>>
>> >>> There's no reason to remove this from the stream when a new machine type
>> >>> is in use.  You'll just send out zeroes.
>> >>
>> >> Seemed cleaner not to.
>> >
>> > It certainly would be if we had a self-descriptive migration stream
>> > format.
>>
>> Yes, removing tests is always a good thing.
>>
>> But I think subsections should always be used when they can.  We should
>> not break compatibility (even if we technical don't guarantee it) unless
>> we absolutely have to.
>>
>> Regards,
>>
>> Anthony Liguori
>
> OK so I can interpret this in 2 ways wrt bridge hotplug:
> - it's in shape for 1.7 except the migration which should use
>   subsections (and needs cross-version testing)
> - it's not in shape for 1.7
>
> Can you tell me which it is please?

The code is not in shape.  Forget about the existence of 1.7.  Focus
on getting the code right and it will make whatever release it is
ready for.  If that's 1.7, great, but the fact that 1.7 is around the
corner does not mean we're going to merge something that isn't ready
just so it makes the release.

Migration is one issue.  As I said before, testing is another.  There
really should be some test automation for this.

Regards,

Anthony Liguori

> If it's 1 I'll repost a version with tweaked
> migration format and cross-version testing report, tomorrow.
>
> If it's 2 I'd rather work on this after the forum, I still
> need to make some travel arrangements.
>
> Paolo? Anthony?
>
> --
> MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Wed, Oct 16, 2013 at 09:38:29AM -0700, Anthony Liguori wrote:
> On Tue, Oct 15, 2013 at 1:17 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Tue, Oct 15, 2013 at 09:27:33AM -0700, Anthony Liguori wrote:
> >> Paolo Bonzini <pbonzini@redhat.com> writes:
> >>
> >> > Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
> >> >> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
> >> >>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> >> >>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> >> >>>> -                       struct pci_status),
> >> >>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> >> >>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
> >> >>>> +                            2, vmstate_pci_status,
> >> >>>> +                            struct pci_status),
> >> >>>
> >> >>> There's no reason to remove this from the stream when a new machine type
> >> >>> is in use.  You'll just send out zeroes.
> >> >>
> >> >> Seemed cleaner not to.
> >> >
> >> > It certainly would be if we had a self-descriptive migration stream
> >> > format.
> >>
> >> Yes, removing tests is always a good thing.
> >>
> >> But I think subsections should always be used when they can.  We should
> >> not break compatibility (even if we technical don't guarantee it) unless
> >> we absolutely have to.
> >>
> >> Regards,
> >>
> >> Anthony Liguori
> >
> > OK so I can interpret this in 2 ways wrt bridge hotplug:
> > - it's in shape for 1.7 except the migration which should use
> >   subsections (and needs cross-version testing)
> > - it's not in shape for 1.7
> >
> > Can you tell me which it is please?
> 
> The code is not in shape.  Forget about the existence of 1.7.  Focus
> on getting the code right and it will make whatever release it is
> ready for.  If that's 1.7, great, but the fact that 1.7 is around the
> corner does not mean we're going to merge something that isn't ready
> just so it makes the release.

OK. Apropos 1.7, how about moving soft freeze and the release out
by a couple of weeks?
What with you moving over and the kvm forum, people
didn't have time to focus on it properly IMO.
In particular it's harder than usual to get reviews.

> Migration is one issue.

Right but what's special about this feature?
Almost anything we do affects migration in some way.

> As I said before, testing is another.  There
> really should be some test automation for this.
> 
> Regards,
> 
> Anthony Liguori

I'm not sure I understand what you are saying here.

If you just want testing hotplug, automation is there.

Automated testing for cross-version migration? that's not easy since you
need two versions around. I'll talk to autotest guys but don't hold your
breath.  But a bigger issue is that migration and hotplug don't work
well together in qemu ATM.

-- 
MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Anthony Liguori]

On Wed, Oct 16, 2013 at 11:18 AM, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Wed, Oct 16, 2013 at 09:38:29AM -0700, Anthony Liguori wrote:
>> On Tue, Oct 15, 2013 at 1:17 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
>> > On Tue, Oct 15, 2013 at 09:27:33AM -0700, Anthony Liguori wrote:
>> >> Paolo Bonzini <pbonzini@redhat.com> writes:
>> >>
>> >> > Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
>> >> >> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
>> >> >>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
>> >> >>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
>> >> >>>> -                       struct pci_status),
>> >> >>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
>> >> >>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
>> >> >>>> +                            2, vmstate_pci_status,
>> >> >>>> +                            struct pci_status),
>> >> >>>
>> >> >>> There's no reason to remove this from the stream when a new machine type
>> >> >>> is in use.  You'll just send out zeroes.
>> >> >>
>> >> >> Seemed cleaner not to.
>> >> >
>> >> > It certainly would be if we had a self-descriptive migration stream
>> >> > format.
>> >>
>> >> Yes, removing tests is always a good thing.
>> >>
>> >> But I think subsections should always be used when they can.  We should
>> >> not break compatibility (even if we technical don't guarantee it) unless
>> >> we absolutely have to.
>> >>
>> >> Regards,
>> >>
>> >> Anthony Liguori
>> >
>> > OK so I can interpret this in 2 ways wrt bridge hotplug:
>> > - it's in shape for 1.7 except the migration which should use
>> >   subsections (and needs cross-version testing)
>> > - it's not in shape for 1.7
>> >
>> > Can you tell me which it is please?
>>
>> The code is not in shape.  Forget about the existence of 1.7.  Focus
>> on getting the code right and it will make whatever release it is
>> ready for.  If that's 1.7, great, but the fact that 1.7 is around the
>> corner does not mean we're going to merge something that isn't ready
>> just so it makes the release.
>
> OK. Apropos 1.7, how about moving soft freeze and the release out
> by a couple of weeks?

No.

There is always some reason to delay releases.  We have a release
every quarter.  It's not a big deal to just wait for a feature for the
next release.  That's the whole point of doing frequent releases.

> What with you moving over and the kvm forum, people
> didn't have time to focus on it properly IMO.
> In particular it's harder than usual to get reviews.
>
>> Migration is one issue.
>
> Right but what's special about this feature?
> Almost anything we do affects migration in some way.

There is nothing special and the feedback you are getting is no
different than any other series.

>
>> As I said before, testing is another.  There
>> really should be some test automation for this.
>>
>> Regards,
>>
>> Anthony Liguori
>
> I'm not sure I understand what you are saying here.
>
> If you just want testing hotplug, automation is there.

Unit level testing.  IOW, something that gets run during 'make check'
to verify that we're generating proper ACPI tables.

Regards,

Anthony Liguori

> Automated testing for cross-version migration? that's not easy since you
> need two versions around. I'll talk to autotest guys but don't hold your
> breath.  But a bigger issue is that migration and hotplug don't work
> well together in qemu ATM.
>
> --
> MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Wed, Oct 16, 2013 at 11:18:42AM -0700, Anthony Liguori wrote:
> On Wed, Oct 16, 2013 at 11:18 AM, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Wed, Oct 16, 2013 at 09:38:29AM -0700, Anthony Liguori wrote:
> >> On Tue, Oct 15, 2013 at 1:17 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> >> > On Tue, Oct 15, 2013 at 09:27:33AM -0700, Anthony Liguori wrote:
> >> >> Paolo Bonzini <pbonzini@redhat.com> writes:
> >> >>
> >> >> > Il 15/10/2013 16:35, Michael S. Tsirkin ha scritto:
> >> >> >> On Tue, Oct 15, 2013 at 04:31:31PM +0200, Paolo Bonzini wrote:
> >> >> >>> Il 14/10/2013 17:01, Michael S. Tsirkin ha scritto:
> >> >> >>>> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> >> >> >>>> -                       struct pci_status),
> >> >> >>>> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> >> >> >>>> +                            vmstate_test_no_use_acpi_pci_hotplug,
> >> >> >>>> +                            2, vmstate_pci_status,
> >> >> >>>> +                            struct pci_status),
> >> >> >>>
> >> >> >>> There's no reason to remove this from the stream when a new machine type
> >> >> >>> is in use.  You'll just send out zeroes.
> >> >> >>
> >> >> >> Seemed cleaner not to.
> >> >> >
> >> >> > It certainly would be if we had a self-descriptive migration stream
> >> >> > format.
> >> >>
> >> >> Yes, removing tests is always a good thing.
> >> >>
> >> >> But I think subsections should always be used when they can.  We should
> >> >> not break compatibility (even if we technical don't guarantee it) unless
> >> >> we absolutely have to.
> >> >>
> >> >> Regards,
> >> >>
> >> >> Anthony Liguori
> >> >
> >> > OK so I can interpret this in 2 ways wrt bridge hotplug:
> >> > - it's in shape for 1.7 except the migration which should use
> >> >   subsections (and needs cross-version testing)
> >> > - it's not in shape for 1.7
> >> >
> >> > Can you tell me which it is please?
> >>
> >> The code is not in shape.  Forget about the existence of 1.7.  Focus
> >> on getting the code right and it will make whatever release it is
> >> ready for.  If that's 1.7, great, but the fact that 1.7 is around the
> >> corner does not mean we're going to merge something that isn't ready
> >> just so it makes the release.
> >
> > OK. Apropos 1.7, how about moving soft freeze and the release out
> > by a couple of weeks?
> 
> No.
> 
> There is always some reason to delay releases.  We have a release
> every quarter.  It's not a big deal to just wait for a feature for the
> next release.  That's the whole point of doing frequent releases.
> 
> > What with you moving over and the kvm forum, people
> > didn't have time to focus on it properly IMO.
> > In particular it's harder than usual to get reviews.
> >
> >> Migration is one issue.
> >
> > Right but what's special about this feature?
> > Almost anything we do affects migration in some way.
> 
> There is nothing special and the feedback you are getting is no
> different than any other series.
> 
> >
> >> As I said before, testing is another.  There
> >> really should be some test automation for this.
> >>
> >> Regards,
> >>
> >> Anthony Liguori
> >
> > I'm not sure I understand what you are saying here.
> >
> > If you just want testing hotplug, automation is there.
> 
> Unit level testing.  IOW, something that gets run during 'make check'
> to verify that we're generating proper ACPI tables.
> 
> Regards,
> 
> Anthony Liguori

In particular I do *not* want to write a consumer for
the guest interfaces in qemu. bios has one,
duplicating it in qemu is not a good idea.

By far the best way to test this is to boot some guest,
download tables, then run iasl -d on them.

I used linux guest but that's not necessary,
we could do this by integrating kvm unit test code.
But if we do integrate it, I think it's better to merge
than fork.

Gleb, Paolo, what do you think? OK to merge kvm unit test
into qemu? It depends on qemu anyway, in-tree will make it easier.
Maybe someone's looking at this already?

If people agree I'll try to make sure this happens but I hope it's not a
precondition, it's a lot of work (and it won't help if I'm distracted
rebasing patches :) )


> > Automated testing for cross-version migration? that's not easy since you
> > need two versions around. I'll talk to autotest guys but don't hold your
> > breath.  But a bigger issue is that migration and hotplug don't work
> > well together in qemu ATM.
> >
> > --
> > MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
> Gleb, Paolo, what do you think? OK to merge kvm unit test
> into qemu? It depends on qemu anyway, in-tree will make it easier.
> Maybe someone's looking at this already?

I think merging KVM unit tests doesn't make much sense because, with
some small exceptions, it is mostly a test or a benchmark for KVM.  What
may make sense is to have a quick way to run autotest on a QEMU tree,
with a subset of testcases that doesn't take too much time (let's say <4
hours) and is more or less guaranteed to pass.  KVM unit tests are run
by autotest, that should be enough.

I agree with Anthony that device model code should be tested by qtest.
I'm not sure this extends to firmware interfaces, though, for two reasons:

(1) any testcase you could have written would have likely not shown the
kind of problem that Igor and Gerd found in your previous versions.
Black box unit testing can only do so much for something as complex as a
DSDT, while black box integration testing works well.

(2) IMO qtest's main advantage is that, at least in principle, the same
testcases could run on all the rarely-used almost-unmaintained targets
(the endianness-test already does that for example).  This does not
apply to most firmware interfaces, though.


By the way, this advantage of qtest is also being mostly negated by the
immaturity (or sheer absence) of infrastructure.

Looking at bugs that were reported, at least these two from Igor are
probably best handled with integration tests (like autotest or Anthony's
qemu-test):

* WS2008R2x64 BSODs with ACPI error on boot when 64bit PCI hole is
present, but it boots fine with upstream QEMU

* hotadd CPU to guest, reboot guest, only initial CPUs are visible to guest


qtest could at best host some sanity checks on the ACPI tables, which
would catch the MCFG problems that Gerd reported on v5.

Gerd also reported some segfaults, not sure how they escaped mst's
testing so I cannot judge what kind of testing could have exposed them
preemptively.

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
> > Gleb, Paolo, what do you think? OK to merge kvm unit test
> > into qemu? It depends on qemu anyway, in-tree will make it easier.
> > Maybe someone's looking at this already?
> 
> I think merging KVM unit tests doesn't make much sense because, with
> some small exceptions, it is mostly a test or a benchmark for KVM.

But why keep them separate? They need qemu to work, don't they?

What I wanted to use from kvm unit test is the infrastructure
to generating the kernel binary for qemu.

> What
> may make sense is to have a quick way to run autotest on a QEMU tree,
> with a subset of testcases that doesn't take too much time (let's say <4
> hours)

That's not really reasonable for make check though.

> and is more or less guaranteed to pass.

That's still the main challenge.

> KVM unit tests are run
> by autotest, that should be enough.
> 
> I agree with Anthony that device model code should be tested by qtest.
> I'm not sure this extends to firmware interfaces, though, for two reasons:
> 
> (1) any testcase you could have written would have likely not shown the
> kind of problem that Igor and Gerd found in your previous versions.
> Black box unit testing can only do so much for something as complex as a
> DSDT, while black box integration testing works well.
> 
> (2) IMO qtest's main advantage is that, at least in principle, the same
> testcases could run on all the rarely-used almost-unmaintained targets
> (the endianness-test already does that for example).  This does not
> apply to most firmware interfaces, though.
> 
> 
> By the way, this advantage of qtest is also being mostly negated by the
> immaturity (or sheer absence) of infrastructure.
> Looking at bugs that were reported, at least these two from Igor are
> probably best handled with integration tests (like autotest or Anthony's
> qemu-test):
> 
> * WS2008R2x64 BSODs with ACPI error on boot when 64bit PCI hole is
> present, but it boots fine with upstream QEMU
> 
> * hotadd CPU to guest, reboot guest, only initial CPUs are visible to guest
> 
> 
> qtest could at best host some sanity checks on the ACPI tables, which
> would catch the MCFG problems that Gerd reported on v5.

Depends on how deep the test understands ACPI - the signature
was wrong I think.
Note I was testing this too - comparing tables between
revisions. I just didn't notice that list of tables
to test included was generated by me on piix, so
MCFG wasn't tested.

> Gerd also reported some segfaults, not sure how they escaped mst's
> testing so I cannot judge what kind of testing could have exposed them
> preemptively.
> 
> Paolo

Mostly forgot to commit mistakes. I since added a script
that checks my tree is clean before build.

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 17/10/2013 00:03, Michael S. Tsirkin ha scritto:
> On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
>> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
>>> Gleb, Paolo, what do you think? OK to merge kvm unit test
>>> into qemu? It depends on qemu anyway, in-tree will make it easier.
>>> Maybe someone's looking at this already?
>>
>> I think merging KVM unit tests doesn't make much sense because, with
>> some small exceptions, it is mostly a test or a benchmark for KVM.
> 
> But why keep them separate? They need qemu to work, don't they?

Not necessarily.  They need a userspace component of course, but most of
them do not need something as big as QEMU.  Most tests, perhaps all,
only write to a handful of ports and use no BIOS services.

>> What
>> may make sense is to have a quick way to run autotest on a QEMU tree,
>> with a subset of testcases that doesn't take too much time (let's say <4
>> hours)
> 
> That's not really reasonable for make check though.

Why not?  When I was working on GCC I usually ran a subset of the
testsuite manually and then did a full run overnight.  I said <4 hours
because it lets you do 2 runs (baseline and patched) while you sleep.

However I agree it's more than we're used to, so I'd not put it under
"make check".  Still, having it available from make would be nice.

>> and is more or less guaranteed to pass.
> 
> That's still the main challenge.

Yep. :(

>> qtest could at best host some sanity checks on the ACPI tables, which
>> would catch the MCFG problems that Gerd reported on v5.
> 
> Depends on how deep the test understands ACPI - the signature
> was wrong I think.
> 
> Note I was testing this too - comparing tables between
> revisions. I just didn't notice that list of tables
> to test included was generated by me on piix, so
> MCFG wasn't tested.

So we could have a qtest for sanity checking ACPI tables.  At least
fw_cfg is one of the few components that has qtest infrastructure...  I
don't think we need to do more than that though.  The set of sanity
checks can start with a simple list of tables that "have to be there"
for a given machine type.

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Anthony Liguori]

On Wed, Oct 16, 2013 at 3:25 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> Il 17/10/2013 00:03, Michael S. Tsirkin ha scritto:
>> On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
>>> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
>>>> Gleb, Paolo, what do you think? OK to merge kvm unit test
>>>> into qemu? It depends on qemu anyway, in-tree will make it easier.
>>>> Maybe someone's looking at this already?
>>>
>>> I think merging KVM unit tests doesn't make much sense because, with
>>> some small exceptions, it is mostly a test or a benchmark for KVM.
>>
>> But why keep them separate? They need qemu to work, don't they?
>
> Not necessarily.  They need a userspace component of course, but most of
> them do not need something as big as QEMU.  Most tests, perhaps all,
> only write to a handful of ports and use no BIOS services.
>
>>> What
>>> may make sense is to have a quick way to run autotest on a QEMU tree,
>>> with a subset of testcases that doesn't take too much time (let's say <4
>>> hours)
>>
>> That's not really reasonable for make check though.
>
> Why not?  When I was working on GCC I usually ran a subset of the
> testsuite manually and then did a full run overnight.  I said <4 hours
> because it lets you do 2 runs (baseline and patched) while you sleep.
>
> However I agree it's more than we're used to, so I'd not put it under
> "make check".  Still, having it available from make would be nice.
>
>>> and is more or less guaranteed to pass.
>>
>> That's still the main challenge.
>
> Yep. :(
>
>>> qtest could at best host some sanity checks on the ACPI tables, which
>>> would catch the MCFG problems that Gerd reported on v5.
>>
>> Depends on how deep the test understands ACPI - the signature
>> was wrong I think.
>>
>> Note I was testing this too - comparing tables between
>> revisions. I just didn't notice that list of tables
>> to test included was generated by me on piix, so
>> MCFG wasn't tested.
>
> So we could have a qtest for sanity checking ACPI tables.  At least
> fw_cfg is one of the few components that has qtest infrastructure...  I
> don't think we need to do more than that though.  The set of sanity
> checks can start with a simple list of tables that "have to be there"
> for a given machine type.

I think we could reasonably attempt to validate ACPI tables across
machine versions.

Since this is qtest, we can even do things like use iasl to
disassemble the blobs on the host.  This could be pretty handy for
detecting compatibility issues across machine versions.

Regards,

Anthony Liguori

>
> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Wed, Oct 16, 2013 at 04:52:35PM -0700, Anthony Liguori wrote:
> On Wed, Oct 16, 2013 at 3:25 PM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> > Il 17/10/2013 00:03, Michael S. Tsirkin ha scritto:
> >> On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
> >>> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
> >>>> Gleb, Paolo, what do you think? OK to merge kvm unit test
> >>>> into qemu? It depends on qemu anyway, in-tree will make it easier.
> >>>> Maybe someone's looking at this already?
> >>>
> >>> I think merging KVM unit tests doesn't make much sense because, with
> >>> some small exceptions, it is mostly a test or a benchmark for KVM.
> >>
> >> But why keep them separate? They need qemu to work, don't they?
> >
> > Not necessarily.  They need a userspace component of course, but most of
> > them do not need something as big as QEMU.  Most tests, perhaps all,
> > only write to a handful of ports and use no BIOS services.
> >
> >>> What
> >>> may make sense is to have a quick way to run autotest on a QEMU tree,
> >>> with a subset of testcases that doesn't take too much time (let's say <4
> >>> hours)
> >>
> >> That's not really reasonable for make check though.
> >
> > Why not?  When I was working on GCC I usually ran a subset of the
> > testsuite manually and then did a full run overnight.  I said <4 hours
> > because it lets you do 2 runs (baseline and patched) while you sleep.
> >
> > However I agree it's more than we're used to, so I'd not put it under
> > "make check".  Still, having it available from make would be nice.
> >
> >>> and is more or less guaranteed to pass.
> >>
> >> That's still the main challenge.
> >
> > Yep. :(
> >
> >>> qtest could at best host some sanity checks on the ACPI tables, which
> >>> would catch the MCFG problems that Gerd reported on v5.
> >>
> >> Depends on how deep the test understands ACPI - the signature
> >> was wrong I think.
> >>
> >> Note I was testing this too - comparing tables between
> >> revisions. I just didn't notice that list of tables
> >> to test included was generated by me on piix, so
> >> MCFG wasn't tested.
> >
> > So we could have a qtest for sanity checking ACPI tables.  At least
> > fw_cfg is one of the few components that has qtest infrastructure...  I
> > don't think we need to do more than that though.  The set of sanity
> > checks can start with a simple list of tables that "have to be there"
> > for a given machine type.
> 
> I think we could reasonably attempt to validate ACPI tables across
> machine versions.
> 
> Since this is qtest, we can even do things like use iasl to
> disassemble the blobs on the host.  This could be pretty handy for
> detecting compatibility issues across machine versions.
> 
> Regards,
> 
> Anthony Liguori

Sounds nifty - comparing dis-assembled output is exactly
how I tested this manually.
This solves the problem that ACPI allows many ways to
encode identical tables.



> >
> > Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Thu, Oct 17, 2013 at 12:25:32AM +0200, Paolo Bonzini wrote:
> Il 17/10/2013 00:03, Michael S. Tsirkin ha scritto:
> > On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
> >> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
> >>> Gleb, Paolo, what do you think? OK to merge kvm unit test
> >>> into qemu? It depends on qemu anyway, in-tree will make it easier.
> >>> Maybe someone's looking at this already?
> >>
> >> I think merging KVM unit tests doesn't make much sense because, with
> >> some small exceptions, it is mostly a test or a benchmark for KVM.
> > 
> > But why keep them separate? They need qemu to work, don't they?
> 
> Not necessarily.  They need a userspace component of course, but most of
> them do not need something as big as QEMU.  Most tests, perhaps all,
> only write to a handful of ports and use no BIOS services.

Well all of them use the test device to report status, right?
Do they work on e.g. kvmtool?
If anyone uses these tests outside QEMU then maybe it's
worth it to be nice and keep it separate.
If not it's just extra pain and compatibility worries without
any real gain - and if someone starts using it
this way down the line we'll be able to use something
like git subtree to extract it again.

For example I think it might be nice to switch everyone
to use pci device instead of fixed ports - less magic
numbers this way. But if I need to keep it working on
old qemu and keep two versions of code around, I'd
probably not bother.

> >> What
> >> may make sense is to have a quick way to run autotest on a QEMU tree,
> >> with a subset of testcases that doesn't take too much time (let's say <4
> >> hours)
> > 
> > That's not really reasonable for make check though.
> 
> Why not?  When I was working on GCC I usually ran a subset of the
> testsuite manually and then did a full run overnight.  I said <4 hours
> because it lets you do 2 runs (baseline and patched) while you sleep.
> 
> However I agree it's more than we're used to, so I'd not put it under
> "make check".  Still, having it available from make would be nice.
> 
> >> and is more or less guaranteed to pass.
> > 
> > That's still the main challenge.
> 
> Yep. :(
> 
> >> qtest could at best host some sanity checks on the ACPI tables, which
> >> would catch the MCFG problems that Gerd reported on v5.
> > 
> > Depends on how deep the test understands ACPI - the signature
> > was wrong I think.
> > 
> > Note I was testing this too - comparing tables between
> > revisions. I just didn't notice that list of tables
> > to test included was generated by me on piix, so
> > MCFG wasn't tested.
> 
> So we could have a qtest for sanity checking ACPI tables.  At least
> fw_cfg is one of the few components that has qtest infrastructure...  I
> don't think we need to do more than that though.  The set of sanity
> checks can start with a simple list of tables that "have to be there"
> for a given machine type.
> 
> Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Gleb Natapov]

On Thu, Oct 17, 2013 at 08:32:14AM +0300, Michael S. Tsirkin wrote:
> On Thu, Oct 17, 2013 at 12:25:32AM +0200, Paolo Bonzini wrote:
> > Il 17/10/2013 00:03, Michael S. Tsirkin ha scritto:
> > > On Wed, Oct 16, 2013 at 11:26:11PM +0200, Paolo Bonzini wrote:
> > >> Il 16/10/2013 20:37, Michael S. Tsirkin ha scritto:
> > >>> Gleb, Paolo, what do you think? OK to merge kvm unit test
> > >>> into qemu? It depends on qemu anyway, in-tree will make it easier.
> > >>> Maybe someone's looking at this already?
> > >>
> > >> I think merging KVM unit tests doesn't make much sense because, with
> > >> some small exceptions, it is mostly a test or a benchmark for KVM.
> > > 
> > > But why keep them separate? They need qemu to work, don't they?
> > 
> > Not necessarily.  They need a userspace component of course, but most of
> > them do not need something as big as QEMU.  Most tests, perhaps all,
> > only write to a handful of ports and use no BIOS services.
> 
> Well all of them use the test device to report status, right?
> Do they work on e.g. kvmtool?
> If anyone uses these tests outside QEMU then maybe it's
> worth it to be nice and keep it separate.
> If not it's just extra pain and compatibility worries without
> any real gain - and if someone starts using it
> this way down the line we'll be able to use something
> like git subtree to extract it again.
> 
Same logic can be used to argue that unittest should be part of Linux
tree. Unittest was part of qemu-kvm and it was decided that having
separate repository for it is much better. Time showed that this is
true. Look at unittests commits and see how much of them have something
to do with QEMU changes and how much do not, and now look at the same
commit and see how much of them has something to do with kernel. See? The
argument for putting unittest into kernel repo is much stronger.

> For example I think it might be nice to switch everyone
> to use pci device instead of fixed ports - less magic
> numbers this way. But if I need to keep it working on
> old qemu and keep two versions of code around, I'd
> probably not bother.
> 
Nothing nice about it. Test device is all about simplicity. If separate
repository stops one from even attempting it the separation was already
a win :)

--
			Gleb.

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Michael S. Tsirkin]

On Thu, Oct 17, 2013 at 12:25:32AM +0200, Paolo Bonzini wrote:
> >> qtest could at best host some sanity checks on the ACPI tables, which
> >> would catch the MCFG problems that Gerd reported on v5.
> > 
> > Depends on how deep the test understands ACPI - the signature
> > was wrong I think.
> > 
> > Note I was testing this too - comparing tables between
> > revisions. I just didn't notice that list of tables
> > to test included was generated by me on piix, so
> > MCFG wasn't tested.
> 
> So we could have a qtest for sanity checking ACPI tables.  At least
> fw_cfg is one of the few components that has qtest infrastructure...  I
> don't think we need to do more than that though.  The set of sanity
> checks can start with a simple list of tables that "have to be there"
> for a given machine type.
> 
> Paolo

Well this means these tests won't pass on old qemu so
they would be useless for comparing old to new.

And in this case, while it's a good idea to have them
I don't see why it's a blocker for merging.

-- 
MST

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Paolo Bonzini]

Il 17/10/2013 07:34, Michael S. Tsirkin ha scritto:
> > So we could have a qtest for sanity checking ACPI tables.  At least
> > fw_cfg is one of the few components that has qtest infrastructure...  I
> > don't think we need to do more than that though.  The set of sanity
> > checks can start with a simple list of tables that "have to be there"
> > for a given machine type.
> 
> Well this means these tests won't pass on old qemu so
> they would be useless for comparing old to new.

Yes, they would be correctness tests not compatibility tests.

> And in this case, while it's a good idea to have them
> I don't see why it's a blocker for merging.

In principle, correctness tests should be a prerequisite for merging
something.  Would you merge RCU without an equivalent of rcutorture?

We rarely if ever obey that principle, but we sometimes do (e.g. QAPI
has pretty good test cases, and new additions to util/ almost always get
new testcases these days).

Paolo

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Gerd Hoffmann]

  Hi,

> By far the best way to test this is to boot some guest,
> download tables, then run iasl -d on them.

Fully agree.  /me did the same when testing with coreboot.  Boot linux,
with old seabios, with new seabios, with (patched) coreboot, then diffed
the iasl decompiled tables.

cheers,
  Gerd

Re: [Qemu-devel] [PULL 42/43] piix4: add acpi pci hotplug support

[Igor Mammedov]

On Mon, 14 Oct 2013 18:01:20 +0300
"Michael S. Tsirkin" <mst@redhat.com> wrote:

> Add support for acpi pci hotplug using the
> new infrastructure.
> PIIX4 legacy interface is maintained as is for
> machine types 1.6 and older.
> 
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> ---
>  include/hw/i386/pc.h |  5 ++++
>  hw/acpi/piix4.c      | 75 +++++++++++++++++++++++++++++++++++++++++++++-------
>  2 files changed, 70 insertions(+), 10 deletions(-)
> 
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 39db8cb..6865972 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -249,6 +249,11 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
>  
>  #define PC_COMPAT_1_6 \
>          {\
> +            .driver   = "PIIX4_PM",\
> +            .property = "acpi-pci-hotplug-with-bridge-support",\
> +            .value    = "off",\
> +        }, \
> +        {\
>              .driver   = "e1000",\
>              .property = "mitigation",\
>              .value    = "off",\
> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
> index 3bcd890..d516033 100644
> --- a/hw/acpi/piix4.c
> +++ b/hw/acpi/piix4.c
> @@ -30,6 +30,7 @@
>  #include "hw/nvram/fw_cfg.h"
>  #include "exec/address-spaces.h"
>  #include "hw/acpi/piix4.h"
> +#include "hw/acpi/pcihp.h"
>  
>  //#define DEBUG
>  
> @@ -73,7 +74,6 @@ typedef struct PIIX4PMState {
>      uint32_t io_base;
>  
>      MemoryRegion io_gpe;
> -    MemoryRegion io_pci;
>      MemoryRegion io_cpu;
>      ACPIREGS ar;
>  
> @@ -88,11 +88,16 @@ typedef struct PIIX4PMState {
>      Notifier machine_ready;
>      Notifier powerdown_notifier;
>  
> -    /* for pci hotplug */
> +    /* for legacy pci hotplug (compatible with qemu 1.6 and older) */
> +    MemoryRegion io_pci;
>      struct pci_status pci0_status;
>      uint32_t pci0_hotplug_enable;
>      uint32_t pci0_slot_device_present;
>  
> +    /* for new pci hotplug (with PCI2PCI bridge support) */
> +    AcpiPciHpState acpi_pci_hotplug;
pcihp therm collides with linux's pcihp driver that is used with native PCIE
hotplug, which makes code a bit confusing at first.

perhaps replacing "pcihp" through out with more verbose "pci_hotplug" would be
better?

> +    bool use_acpi_pci_hotplug;
> +
>      uint8_t disable_s3;
>      uint8_t disable_s4;
>      uint8_t s4_val;
> @@ -282,6 +287,18 @@ static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
>      return ret;
>  }
>  
> +static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
> +{
> +    PIIX4PMState *s = opaque;
> +    return s->use_acpi_pci_hotplug;
> +}
> +
> +static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
> +{
> +    PIIX4PMState *s = opaque;
> +    return !s->use_acpi_pci_hotplug;
> +}
> +
>  /* qemu-kvm 1.2 uses version 3 but advertised as 2
>   * To support incoming qemu-kvm 1.2 migration, change version_id
>   * and minimum_version_id to 2 below (which breaks migration from
> @@ -304,8 +321,12 @@ static const VMStateDescription vmstate_acpi = {
>          VMSTATE_TIMER(ar.tmr.timer, PIIX4PMState),
>          VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
>          VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
> -        VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
> -                       struct pci_status),
> +        VMSTATE_STRUCT_TEST(pci0_status, PIIX4PMState,
> +                            vmstate_test_no_use_acpi_pci_hotplug,
> +                            2, vmstate_pci_status,
> +                            struct pci_status),
> +        VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
> +                            vmstate_test_use_acpi_pci_hotplug),
>          VMSTATE_END_OF_LIST()
>      }
>  };
> @@ -383,7 +404,11 @@ static void piix4_reset(void *opaque)
>          pci_conf[0x5B] = 0x02;
>      }
>      pm_io_space_update(s);
> -    piix4_update_hotplug(s);
> +    if (s->use_acpi_pci_hotplug) {
> +        acpi_pcihp_reset(&s->acpi_pci_hotplug);
> +    } else {
> +        piix4_update_hotplug(s);
> +    }
>  }
>  
>  static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
> @@ -394,6 +419,26 @@ static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
>      acpi_pm1_evt_power_down(&s->ar);
>  }
>  
> +static int piix4_acpi_pci_hotplug(DeviceState *qdev, PCIDevice *dev,
> +                                  PCIHotplugState state)
> +{
> +    PIIX4PMState *s = PIIX4_PM(qdev);
> +    int ret = acpi_pcihp_device_hotplug(&s->acpi_pci_hotplug, dev, state);
> +    if (ret < 0) {
> +        return ret;
> +    }
> +    s->ar.gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
> +
> +    pm_update_sci(s);
> +    return 0;
> +}
> +
> +static void piix4_update_bus_hotplug(PCIBus *bus, void *opaque)
> +{
> +    PIIX4PMState *s = opaque;
> +    pci_bus_hotplug(bus, piix4_acpi_pci_hotplug, DEVICE(s));
> +}
> +
>  static void piix4_pm_machine_ready(Notifier *n, void *opaque)
>  {
>      PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
> @@ -407,6 +452,10 @@ static void piix4_pm_machine_ready(Notifier *n, void *opaque)
>      pci_conf[0x63] = 0x60;
>      pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
>          (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
> +
> +    if (s->use_acpi_pci_hotplug) {
> +        pci_for_each_bus(d->bus, piix4_update_bus_hotplug, s);
why do you need to do it dinamically?

> +    }
>  }
>  
>  static void piix4_pm_add_propeties(PIIX4PMState *s)
> @@ -528,6 +577,8 @@ static Property piix4_pm_properties[] = {
>      DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
>      DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
>      DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
> +    DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
> +                     use_acpi_pci_hotplug, true),
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> @@ -716,11 +767,15 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
>                            "acpi-gpe0", GPE_LEN);
>      memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
>  
> -    memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
> -                          "acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
> -    memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
> -                                &s->io_pci);
> -    pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
> +    if (s->use_acpi_pci_hotplug) {
> +        acpi_pcihp_init(&s->acpi_pci_hotplug, bus, parent);
> +    } else {
> +        memory_region_init_io(&s->io_pci, OBJECT(s), &piix4_pci_ops, s,
> +                              "acpi-pci-hotplug", PCI_HOTPLUG_SIZE);
> +        memory_region_add_subregion(parent, PCI_HOTPLUG_ADDR,
> +                                    &s->io_pci);
> +        pci_bus_hotplug(bus, piix4_device_hotplug, DEVICE(s));
> +    }
>  
>      CPU_FOREACH(cpu) {
>          CPUClass *cc = CPU_GET_CLASS(cpu);
> -- 
> MST
> 
> 


-- 
Regards,
  Igor

[Qemu-devel] [PULL 43/43] acpi-build: enable hotplug for PCI bridges

[Michael S. Tsirkin]

This enables support for device hotplug behind
pci bridges. Bridge devices themselves need
to be pre-configured on qemu command line.

Design:
    - at machine init time, assign "bsel" property to bridges with
      hotplug support
    - dynamically (At ACPI table read) generate ACPI code to handle
      hotplug events for each bridge with "bsel" property

Note: ACPI doesn't support adding or removing bridges by hotplug.
We detect and prevent removal of bridges by hotplug,
unless they were added by hotplug previously
(and so, are not described by ACPI).

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/i386/acpi-build.c   | 346 +++++++++++++++++++++++++++++++++++++++----------
 hw/i386/acpi-dsdt.dsl  |  34 +++--
 hw/i386/ssdt-pcihp.dsl |  11 +-
 3 files changed, 297 insertions(+), 94 deletions(-)

diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 6cfa044..4311814 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -39,6 +39,7 @@
 
 /* Supported chipsets: */
 #include "hw/acpi/piix4.h"
+#include "hw/acpi/pcihp.h"
 #include "hw/i386/ich9.h"
 #include "hw/pci/pci_bus.h"
 #include "hw/pci-host/q35.h"
@@ -78,6 +79,12 @@ typedef struct AcpiMiscInfo {
     uint16_t pvpanic_port;
 } AcpiMiscInfo;
 
+typedef struct AcpiBuildPciBusHotplugState {
+    GArray *device_table;
+    GArray *notify_table;
+    struct AcpiBuildPciBusHotplugState *parent;
+} AcpiBuildPciBusHotplugState;
+
 static void acpi_get_dsdt(AcpiMiscInfo *info)
 {
     Object *piix = piix4_pm_find();
@@ -171,38 +178,6 @@ static void acpi_get_pm_info(AcpiPmInfo *pm)
                                                NULL);
 }
 
-static void acpi_get_hotplug_info(AcpiMiscInfo *misc)
-{
-    int i;
-    PCIBus *bus = find_i440fx();
-
-    if (!bus) {
-        /* Only PIIX supports ACPI hotplug */
-        memset(misc->slot_hotplug_enable, 0, sizeof misc->slot_hotplug_enable);
-        return;
-    }
-
-    memset(misc->slot_hotplug_enable, 0xff,
-           DIV_ROUND_UP(PCI_SLOT_MAX, BITS_PER_BYTE));
-
-    for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
-        PCIDeviceClass *pc;
-        PCIDevice *pdev = bus->devices[i];
-
-        if (!pdev) {
-            continue;
-        }
-
-        pc = PCI_DEVICE_GET_CLASS(pdev);
-
-        if (pc->no_hotplug) {
-            int slot = PCI_SLOT(i);
-
-            clear_bit(slot, misc->slot_hotplug_enable);
-        }
-    }
-}
-
 static void acpi_get_misc_info(AcpiMiscInfo *info)
 {
     info->has_hpet = hpet_find();
@@ -366,6 +341,12 @@ static void build_package(GArray *package, uint8_t op, unsigned min_bytes)
     build_prepend_byte(package, op);
 }
 
+static void build_extop_package(GArray *package, uint8_t op)
+{
+    build_package(package, op, 1);
+    build_prepend_byte(package, 0x5B); /* ExtOpPrefix */
+}
+
 static void build_append_value(GArray *table, uint32_t value, int size)
 {
     uint8_t prefix;
@@ -392,8 +373,44 @@ static void build_append_value(GArray *table, uint32_t value, int size)
     }
 }
 
-static void build_append_notify_target(GArray *method, GArray *target_name,
-                                       uint32_t value, int size)
+static void build_append_int(GArray *table, uint32_t value)
+{
+    if (value == 0x00) {
+        build_append_byte(table, 0x00); /* ZeroOp */
+    } else if (value == 0x01) {
+        build_append_byte(table, 0x01); /* OneOp */
+    } else if (value <= 0xFF) {
+        build_append_value(table, value, 1);
+    } else if (value <= 0xFFFFF) {
+        build_append_value(table, value, 2);
+    } else {
+        build_append_value(table, value, 4);
+    }
+}
+
+static GArray *build_alloc_method(const char *name, uint8_t arg_count)
+{
+    GArray *method = build_alloc_array();
+
+    build_append_nameseg(method, name);
+    build_append_byte(method, arg_count); /* MethodFlags: ArgCount */
+
+    return method;
+}
+
+static void build_append_and_cleanup_method(GArray *device, GArray *method)
+{
+    uint8_t op = 0x14; /* MethodOp */
+
+    build_package(method, op, 0);
+
+    build_append_array(device, method);
+    build_free_array(method);
+}
+
+static void build_append_notify_target_ifequal(GArray *method,
+                                               GArray *target_name,
+                                               uint32_t value, int size)
 {
     GArray *notify = build_alloc_array();
     uint8_t op = 0xA0; /* IfOp */
@@ -413,6 +430,7 @@ static void build_append_notify_target(GArray *method, GArray *target_name,
     build_free_array(notify);
 }
 
+/* End here */
 #define ACPI_PORT_SMI_CMD           0x00b2 /* TODO: this is APM_CNT_IOPORT */
 
 static inline void *acpi_data_push(GArray *table_data, unsigned size)
@@ -621,44 +639,234 @@ static inline char acpi_get_hex(uint32_t val)
 #include "hw/i386/ssdt-pcihp.hex"
 
 static void
-build_append_notify(GArray *device, const char *name,
-                    const char *format, int skip, int count)
+build_append_notify_method(GArray *device, const char *name,
+                           const char *format, int count)
 {
     int i;
-    GArray *method = build_alloc_array();
-    uint8_t op = 0x14; /* MethodOp */
+    GArray *method = build_alloc_method(name, 2);
 
-    build_append_nameseg(method, name);
-    build_append_byte(method, 0x02); /* MethodFlags: ArgCount */
-    for (i = skip; i < count; i++) {
+    for (i = 0; i < count; i++) {
         GArray *target = build_alloc_array();
         build_append_nameseg(target, format, i);
         assert(i < 256); /* Fits in 1 byte */
-        build_append_notify_target(method, target, i, 1);
+        build_append_notify_target_ifequal(method, target, i, 1);
         build_free_array(target);
     }
-    build_package(method, op, 2);
 
-    build_append_array(device, method);
-    build_free_array(method);
+    build_append_and_cleanup_method(device, method);
 }
 
-static void patch_pcihp(int slot, uint8_t *ssdt_ptr, uint32_t eject)
+static void patch_pcihp(int slot, uint8_t *ssdt_ptr)
 {
-    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(slot >> 4);
-    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(slot);
+    unsigned devfn = PCI_DEVFN(slot, 0);
+
+    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX] = acpi_get_hex(devfn >> 4);
+    ssdt_ptr[ACPI_PCIHP_OFFSET_HEX + 1] = acpi_get_hex(devfn);
     ssdt_ptr[ACPI_PCIHP_OFFSET_ID] = slot;
     ssdt_ptr[ACPI_PCIHP_OFFSET_ADR + 2] = slot;
+}
+
+/* Assign BSEL property to all buses.  In the future, this can be changed
+ * to only assign to buses that support hotplug.
+ */
+static void *acpi_set_bsel(PCIBus *bus, void *opaque)
+{
+    unsigned *bsel_alloc = opaque;
+    unsigned *bus_bsel = g_malloc(sizeof *bus_bsel);
+
+    *bus_bsel = (*bsel_alloc)++;
+    object_property_add_uint32_ptr(OBJECT(bus), ACPI_PCIHP_PROP_BSEL,
+                                   bus_bsel, NULL);
 
-    /* Runtime patching of ACPI_EJ0: to disable hotplug for a slot,
-     * replace the method name: _EJ0 by ACPI_EJ0_.
+    return bsel_alloc;
+}
+
+static void acpi_set_pci_info(void)
+{
+    PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
+    unsigned bsel_alloc = 0;
+
+    if (bus) {
+        /* Scan all PCI buses. Generate tables to support
+         * PCI hotplug. Set property to enable acpi based hotplug.
+         */
+        pci_for_each_bus_depth_first(bus, acpi_set_bsel, NULL, &bsel_alloc);
+    }
+}
+
+static void build_pci_bus_state_init(AcpiBuildPciBusHotplugState *state,
+                                     AcpiBuildPciBusHotplugState *parent)
+{
+    state->parent = parent;
+    state->device_table = build_alloc_array();
+    state->notify_table = build_alloc_array();
+}
+
+static void build_pci_bus_state_cleanup(AcpiBuildPciBusHotplugState *state)
+{
+    build_free_array(state->device_table);
+    build_free_array(state->notify_table);
+}
+
+static void *build_pci_bus_begin(PCIBus *bus, void *parent_state)
+{
+    AcpiBuildPciBusHotplugState *parent = parent_state;
+    AcpiBuildPciBusHotplugState *child = g_malloc(sizeof *child);
+
+    build_pci_bus_state_init(child, parent);
+
+    return child;
+}
+
+static void build_pci_bus_end(PCIBus *bus, void *bus_state)
+{
+    AcpiBuildPciBusHotplugState *child = bus_state;
+    AcpiBuildPciBusHotplugState *parent = child->parent;
+    GArray *bus_table = build_alloc_array();
+    DECLARE_BITMAP(slot_hotplug_enable, PCI_SLOT_MAX);
+    uint8_t op;
+    int i;
+    QObject *bsel;
+    GArray *method;
+    bool bus_hotplug_support = false;
+
+    if (bus->parent_dev) {
+        op = 0x82; /* DeviceOp */
+        build_append_nameseg(bus_table, "S%0.02X_",
+                             bus->parent_dev->devfn);
+        build_append_byte(bus_table, 0x08); /* NameOp */
+        build_append_nameseg(bus_table, "_SUN");
+        build_append_value(bus_table, PCI_SLOT(bus->parent_dev->devfn), 1);
+        build_append_byte(bus_table, 0x08); /* NameOp */
+        build_append_nameseg(bus_table, "_ADR");
+        build_append_value(bus_table, (PCI_SLOT(bus->parent_dev->devfn) << 16) |
+                           PCI_FUNC(bus->parent_dev->devfn), 4);
+    } else {
+        op = 0x10; /* ScopeOp */;
+        build_append_nameseg(bus_table, "PCI0");
+    }
+
+    bsel = object_property_get_qobject(OBJECT(bus), ACPI_PCIHP_PROP_BSEL, NULL);
+    if (bsel) {
+        build_append_byte(bus_table, 0x08); /* NameOp */
+        build_append_nameseg(bus_table, "BSEL");
+        build_append_int(bus_table, qint_get_int(qobject_to_qint(bsel)));
+
+        memset(slot_hotplug_enable, 0xff, sizeof slot_hotplug_enable);
+
+        for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
+            PCIDeviceClass *pc;
+            PCIDevice *pdev = bus->devices[i];
+
+            if (!pdev) {
+                continue;
+            }
+
+            pc = PCI_DEVICE_GET_CLASS(pdev);
+
+            if (pc->no_hotplug || pc->is_bridge) {
+                int slot = PCI_SLOT(i);
+
+                clear_bit(slot, slot_hotplug_enable);
+            }
+        }
+
+        /* Append Device object for each slot which supports eject */
+        for (i = 0; i < PCI_SLOT_MAX; i++) {
+            bool can_eject = test_bit(i, slot_hotplug_enable);
+            if (can_eject) {
+                void *pcihp = acpi_data_push(bus_table,
+                                             ACPI_PCIHP_SIZEOF);
+                memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
+                patch_pcihp(i, pcihp);
+                bus_hotplug_support = true;
+            }
+        }
+
+        method = build_alloc_method("DVNT", 2);
+
+        for (i = 0; i < PCI_SLOT_MAX; i++) {
+            GArray *notify;
+            uint8_t op;
+
+            if (!test_bit(i, slot_hotplug_enable)) {
+                continue;
+            }
+
+            notify = build_alloc_array();
+            op = 0xA0; /* IfOp */
+
+            build_append_byte(notify, 0x7B); /* AndOp */
+            build_append_byte(notify, 0x68); /* Arg0Op */
+            build_append_int(notify, 0x1 << i);
+            build_append_byte(notify, 0x00); /* NullName */
+            build_append_byte(notify, 0x86); /* NotifyOp */
+            build_append_nameseg(notify, "S%0.02X_", PCI_DEVFN(i, 0));
+            build_append_byte(notify, 0x69); /* Arg1Op */
+
+            /* Pack it up */
+            build_package(notify, op, 0);
+
+            build_append_array(method, notify);
+
+            build_free_array(notify);
+        }
+
+        build_append_and_cleanup_method(bus_table, method);
+    }
+
+    /* Append PCNT method to notify about events on local and child buses.
+     * Add unconditionally for root since DSDT expects it.
      */
-    /* Sanity check */
-    assert(!memcmp(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "_EJ0", 4));
+    if (bus_hotplug_support || child->notify_table->len || !bus->parent_dev) {
+        method = build_alloc_method("PCNT", 0);
+
+        /* If bus supports hotplug select it and notify about local events */
+        if (bsel) {
+            build_append_byte(method, 0x70); /* StoreOp */
+            build_append_int(method, qint_get_int(qobject_to_qint(bsel)));
+            build_append_nameseg(method, "BNUM");
+            build_append_nameseg(method, "DVNT");
+            build_append_nameseg(method, "PCIU");
+            build_append_int(method, 1); /* Device Check */
+            build_append_nameseg(method, "DVNT");
+            build_append_nameseg(method, "PCID");
+            build_append_int(method, 3); /* Eject Request */
+        }
+
+        /* Notify about child bus events in any case */
+        build_append_array(method, child->notify_table);
+
+        build_append_and_cleanup_method(bus_table, method);
+
+        /* Append description of child buses */
+        build_append_array(bus_table, child->device_table);
+
+        /* Pack it up */
+        if (bus->parent_dev) {
+            build_extop_package(bus_table, op);
+        } else {
+            build_package(bus_table, op, 0);
+        }
 
-    if (!eject) {
-        memcpy(ssdt_ptr + ACPI_PCIHP_OFFSET_EJ0, "EJ0_", 4);
+        /* Append our bus description to parent table */
+        build_append_array(parent->device_table, bus_table);
+
+        /* Also tell parent how to notify us, invoking PCNT method.
+         * At the moment this is not needed for root as we have a single root.
+         */
+        if (bus->parent_dev) {
+            build_append_byte(parent->notify_table, '^'); /* ParentPrefixChar */
+            build_append_byte(parent->notify_table, 0x2E); /* DualNamePrefix */
+            build_append_nameseg(parent->notify_table, "S%0.02X_",
+                                 bus->parent_dev->devfn);
+            build_append_nameseg(parent->notify_table, "PCNT");
+        }
     }
+
+    build_free_array(bus_table);
+    build_pci_bus_state_cleanup(child);
+    g_free(child);
 }
 
 static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
@@ -730,7 +938,7 @@ build_ssdt(GArray *table_data, GArray *linker,
          *   Method(NTFY, 2) {If (LEqual(Arg0, 0x00)) {Notify(CP00, Arg1)} ...}
          */
         /* Arg0 = Processor ID = APIC ID */
-        build_append_notify(sb_scope, "NTFY", "CP%0.02X", 0, acpi_cpus);
+        build_append_notify_method(sb_scope, "NTFY", "CP%0.02X", acpi_cpus);
 
         /* build "Name(CPON, Package() { One, One, ..., Zero, Zero, ... })" */
         build_append_byte(sb_scope, 0x08); /* NameOp */
@@ -752,24 +960,21 @@ build_ssdt(GArray *table_data, GArray *linker,
         }
 
         {
-            GArray *pci0 = build_alloc_array();
-            uint8_t op = 0x10; /* ScopeOp */;
+            AcpiBuildPciBusHotplugState hotplug_state;
+            PCIBus *bus = find_i440fx(); /* TODO: Q35 support */
 
-            build_append_nameseg(pci0, "PCI0");
+            build_pci_bus_state_init(&hotplug_state, NULL);
 
-            /* build Device object for each slot */
-            for (i = 1; i < PCI_SLOT_MAX; i++) {
-                bool eject = test_bit(i, misc->slot_hotplug_enable);
-                void *pcihp = acpi_data_push(pci0, ACPI_PCIHP_SIZEOF);
-
-                memcpy(pcihp, ACPI_PCIHP_AML, ACPI_PCIHP_SIZEOF);
-                patch_pcihp(i, pcihp, eject);
+            if (bus) {
+                /* Scan all PCI buses. Generate tables to support
+                 * PCI hotplug. Set property to enable acpi based hotplug.
+                */
+                pci_for_each_bus_depth_first(bus, build_pci_bus_begin,
+                                             build_pci_bus_end, &hotplug_state);
             }
 
-            build_append_notify(pci0, "PCNT", "S%0.02X_", 1, PCI_SLOT_MAX);
-            build_package(pci0, op, 3);
-            build_append_array(sb_scope, pci0);
-            build_free_array(pci0);
+            build_append_array(sb_scope, hotplug_state.device_table);
+            build_pci_bus_state_cleanup(&hotplug_state);
         }
 
         build_package(sb_scope, op, 3);
@@ -1046,7 +1251,6 @@ void acpi_build(PcGuestInfo *guest_info, AcpiBuildTables *tables)
     acpi_get_cpu_info(&cpu);
     acpi_get_pm_info(&pm);
     acpi_get_dsdt(&misc);
-    acpi_get_hotplug_info(&misc);
     acpi_get_misc_info(&misc);
     acpi_get_pci_info(&pci);
 
@@ -1186,6 +1390,8 @@ void acpi_setup(PcGuestInfo *guest_info)
 
     build_state->guest_info = guest_info;
 
+    acpi_set_pci_info();
+
     acpi_build_tables_init(&tables);
     acpi_build(build_state->guest_info, &tables);
 
diff --git a/hw/i386/acpi-dsdt.dsl b/hw/i386/acpi-dsdt.dsl
index 90efce0..70b8329 100644
--- a/hw/i386/acpi-dsdt.dsl
+++ b/hw/i386/acpi-dsdt.dsl
@@ -133,32 +133,28 @@ DefinitionBlock (
             B0EJ, 32,
         }
 
+        OperationRegion(BNMR, SystemIO, 0xae10, 0x04)
+        Field(BNMR, DWordAcc, NoLock, WriteAsZeros) {
+            BNUM, 32,
+        }
+
+        /* Lock to protect access to fields above. */
+        Mutex(BLCK, 0)
+
         /* Methods called by bulk generated PCI devices below */
 
         /* Methods called by hotplug devices */
-        Method(PCEJ, 1, NotSerialized) {
+        Method(PCEJ, 2, NotSerialized) {
             // _EJ0 method - eject callback
-            Store(ShiftLeft(1, Arg0), B0EJ)
+            Acquire(BLCK, 0xFFFF)
+            Store(Arg0, BNUM)
+            Store(ShiftLeft(1, Arg1), B0EJ)
+            Release(BLCK)
             Return (0x0)
         }
 
         /* Hotplug notification method supplied by SSDT */
         External(\_SB.PCI0.PCNT, MethodObj)
-
-        /* PCI hotplug notify method */
-        Method(PCNF, 0) {
-            // Local0 = iterator
-            Store(Zero, Local0)
-            While (LLess(Local0, 31)) {
-                Increment(Local0)
-                If (And(PCIU, ShiftLeft(1, Local0))) {
-                    PCNT(Local0, 1)
-                }
-                If (And(PCID, ShiftLeft(1, Local0))) {
-                    PCNT(Local0, 3)
-                }
-            }
-        }
     }
 
 
@@ -307,7 +303,9 @@ DefinitionBlock (
         }
         Method(_E01) {
             // PCI hotplug event
-            \_SB.PCI0.PCNF()
+            Acquire(\_SB.PCI0.BLCK, 0xFFFF)
+            \_SB.PCI0.PCNT()
+            Release(\_SB.PCI0.BLCK)
         }
         Method(_E02) {
             // CPU hotplug event
diff --git a/hw/i386/ssdt-pcihp.dsl b/hw/i386/ssdt-pcihp.dsl
index d29a5b9..cc245c3 100644
--- a/hw/i386/ssdt-pcihp.dsl
+++ b/hw/i386/ssdt-pcihp.dsl
@@ -25,6 +25,7 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
     /* Objects supplied by DSDT */
     External(\_SB.PCI0, DeviceObj)
     External(\_SB.PCI0.PCEJ, MethodObj)
+    External(BSEL, IntObj)
 
     Scope(\_SB.PCI0) {
 
@@ -33,19 +34,17 @@ DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
         ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end
         ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name
 
-        // Method _EJ0 can be patched by BIOS to EJ0_
-        // at runtime, if the slot is detected to not support hotplug.
-        // Extract the offset of the address dword and the
-        // _EJ0 name to allow this patching.
+        // Extract the offsets of the device name, address dword and the slot
+        // name byte - we fill them in for each device.
         Device(SAA) {
             ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id
             Name(_SUN, 0xAA)
             ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr
             Name(_ADR, 0xAA0000)
-            ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0
             Method(_EJ0, 1) {
-                Return (PCEJ(_SUN))
+                PCEJ(BSEL, _SUN)
             }
         }
+
     }
 }
-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Anthony Liguori]

"Michael S. Tsirkin" <mst@redhat.com> writes:

> Anthony, I know you wanted to review some of the patches,
> since you didn't respond either all's well or you
> could not find the time.
> I think we are better off merging them for 1.7 and then - worst case,
> if major issues surface - disabling the functionality at the last minute
> than delaying the merge even more.

There is no way I'll pull this for 1.7.  Changes like this aren't going
to get merged at the last minute.  A good chunk of the series lacks
any Reviewed-bys including the actual hotplug behind a pci bridge bits
which is the whole point of the series.

This is a huge series and I still am not convinced this is the right
path forward.  The alternative to this series is a small set of changes
to SeaBIOS to support PCI bridge hotplug, no?

Or 10k SLOC of code into QEMU that includes breaking migration
compatibility.

Regards,

Anthony Liguori

> The following changes since commit e26d3e734650640fabd7d95ace4f3a6f88725e0b:
>
>   smbios: Factor out smbios_maybe_add_str() (2013-09-28 23:49:39 +0300)
>
> are available in the git repository at:
>
>   git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
>
> for you to fetch changes up to 6cab1e7000021fa6a487f67e1dba986f68fee30d:
>
>   acpi-build: enable hotplug for PCI bridges (2013-10-14 17:48:58 +0300)
>
> ----------------------------------------------------------------
> pci, pc, acpi fixes, enhancements
>
> This includes some pretty big changes:
> - pci master abort support by Marcel
> - pci IRQ API rework by Marcel
> - acpi generation and pci bridge hotplug support by myself
>
> Everything has gone through several revisions, latest versions have been on
> list for a while without any more comments, tested by several
> people.
>
> Please pull for 1.7.
>
> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>
> ----------------------------------------------------------------
> Igor Mammedov (1):
>       cleanup object.h: include error.h directly
>
> Marcel Apfelbaum (11):
>       memory: Change MemoryRegion priorities from unsigned to signed
>       docs/memory: Explictly state that MemoryRegion priority is signed
>       hw/pci: partially handle pci master abort
>       hw/core: Add interface to allocate and free a single IRQ
>       hw/pci: add pci wrappers for allocating and asserting irqs
>       hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init
>       hw/vmxnet3: set interrupts using pci irq wrappers
>       hw/vfio: set interrupts using pci irq wrappers
>       hw: set interrupts using pci irq wrappers
>       hw/pcie: AER and hot-plug events must use device's interrupt
>       hw/pci: removed irq field from PCIDevice
>
> Michael S. Tsirkin (31):
>       qom: cleanup struct Error references
>       qom: add pointer to int property helpers
>       pci: fix up w64 size calculation helper
>       fw_cfg: interface to trigger callback on read
>       loader: support for unmapped ROM blobs
>       pcie_host: expose UNMAPPED macro
>       pcie_host: expose address format
>       q35: use macro for MCFG property name
>       q35: expose mmcfg size as a property
>       i386: add ACPI table files from seabios
>       acpi: add rules to compile ASL source
>       acpi: pre-compiled ASL files
>       acpi: ssdt pcihp: updat generated file
>       loader: use file path size from fw_cfg.h
>       i386: add bios linker/loader
>       loader: allow adding ROMs in done callbacks
>       i386: define pc guest info
>       acpi/piix: add macros for acpi property names
>       piix: APIs for pc guest info
>       ich9: APIs for pc guest info
>       pvpanic: add API to access io port
>       hpet: add API to find it
>       acpi: add interface to access user-installed tables
>       pc: use new api to add builtin tables
>       i386: ACPI table generation code from seabios
>       ssdt: fix PBLK length
>       ssdt-proc: update generated file
>       pci: add pci_for_each_bus_depth_first
>       pcihp: generalization of piix4 acpi
>       piix4: add acpi pci hotplug support
>       acpi-build: enable hotplug for PCI bridges
>
>  configure                           |    9 +-
>  hw/i386/acpi-build.h                |    9 +
>  hw/i386/acpi-defs.h                 |  331 ++
>  hw/i386/bios-linker-loader.h        |   27 +
>  hw/lm32/lm32_hwsetup.h              |    2 +-
>  include/exec/memory.h               |    4 +-
>  include/hw/acpi/acpi.h              |    4 +
>  include/hw/acpi/ich9.h              |    2 +
>  include/hw/acpi/pcihp.h             |   72 +
>  include/hw/acpi/piix4.h             |    8 +
>  include/hw/i386/ich9.h              |    2 +
>  include/hw/i386/pc.h                |   27 +
>  include/hw/irq.h                    |    7 +
>  include/hw/loader.h                 |    8 +-
>  include/hw/nvram/fw_cfg.h           |    8 +-
>  include/hw/pci-host/q35.h           |    2 +
>  include/hw/pci/pci.h                |   40 +-
>  include/hw/pci/pci_bus.h            |    1 +
>  include/hw/pci/pcie.h               |   18 -
>  include/hw/pci/pcie_host.h          |   27 +
>  include/hw/sysbus.h                 |    2 +-
>  include/hw/timer/hpet.h             |    2 +
>  include/qom/object.h                |   73 +-
>  hw/acpi/core.c                      |   40 +
>  hw/acpi/ich9.c                      |   24 +
>  hw/acpi/pcihp.c                     |  312 ++
>  hw/acpi/piix4.c                     |  125 +-
>  hw/audio/ac97.c                     |    4 +-
>  hw/audio/es1370.c                   |    4 +-
>  hw/audio/intel-hda.c                |    2 +-
>  hw/block/nvme.c                     |    2 +-
>  hw/char/serial-pci.c                |    5 +-
>  hw/char/tpci200.c                   |    8 +-
>  hw/core/irq.c                       |   16 +
>  hw/core/loader.c                    |   31 +-
>  hw/core/sysbus.c                    |    4 +-
>  hw/display/qxl.c                    |    2 +-
>  hw/i386/acpi-build.c                | 1420 +++++++
>  hw/i386/bios-linker-loader.c        |  158 +
>  hw/i386/pc.c                        |   25 +-
>  hw/i386/pc_piix.c                   |    5 +
>  hw/i386/pc_q35.c                    |    3 +
>  hw/ide/cmd646.c                     |    2 +-
>  hw/ide/ich.c                        |    3 +-
>  hw/isa/lpc_ich9.c                   |   40 +
>  hw/isa/vt82c686.c                   |    2 +-
>  hw/misc/ivshmem.c                   |    2 +-
>  hw/misc/pvpanic.c                   |   13 +-
>  hw/misc/vfio.c                      |   11 +-
>  hw/net/e1000.c                      |    2 +-
>  hw/net/eepro100.c                   |    4 +-
>  hw/net/ne2000.c                     |    3 +-
>  hw/net/pcnet-pci.c                  |    3 +-
>  hw/net/rtl8139.c                    |    2 +-
>  hw/net/vmxnet3.c                    |   13 +-
>  hw/nvram/fw_cfg.c                   |   33 +-
>  hw/pci-bridge/pci_bridge_dev.c      |    2 +-
>  hw/pci-host/piix.c                  |    8 +
>  hw/pci-host/q35.c                   |   26 +-
>  hw/pci/pci.c                        |  100 +-
>  hw/pci/pcie.c                       |    4 +-
>  hw/pci/pcie_aer.c                   |    4 +-
>  hw/pci/pcie_host.c                  |   24 -
>  hw/pci/shpc.c                       |    2 +-
>  hw/scsi/esp-pci.c                   |    3 +-
>  hw/scsi/lsi53c895a.c                |    2 +-
>  hw/scsi/megasas.c                   |    6 +-
>  hw/scsi/vmw_pvscsi.c                |    2 +-
>  hw/timer/hpet.c                     |    5 +
>  hw/usb/hcd-ehci-pci.c               |    2 +-
>  hw/usb/hcd-ohci.c                   |    2 +-
>  hw/usb/hcd-uhci.c                   |    6 +-
>  hw/usb/hcd-xhci.c                   |    7 +-
>  hw/virtio/virtio-pci.c              |    4 +-
>  memory.c                            |    4 +-
>  qom/object.c                        |   60 +
>  vl.c                                |    3 +
>  docs/memory.txt                     |    4 +
>  hw/acpi/Makefile.objs               |    2 +-
>  hw/i386/Makefile.objs               |   27 +
>  hw/i386/acpi-dsdt-cpu-hotplug.dsl   |   93 +
>  hw/i386/acpi-dsdt-dbug.dsl          |   41 +
>  hw/i386/acpi-dsdt-hpet.dsl          |   51 +
>  hw/i386/acpi-dsdt-isa.dsl           |  117 +
>  hw/i386/acpi-dsdt-pci-crs.dsl       |  105 +
>  hw/i386/acpi-dsdt.dsl               |  341 ++
>  hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
>  hw/i386/q35-acpi-dsdt.dsl           |  452 +++
>  hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
>  hw/i386/ssdt-misc.dsl               |  119 +
>  hw/i386/ssdt-misc.hex.generated     |  386 ++
>  hw/i386/ssdt-pcihp.dsl              |   50 +
>  hw/i386/ssdt-pcihp.hex.generated    |  108 +
>  hw/i386/ssdt-proc.dsl               |   63 +
>  hw/i386/ssdt-proc.hex.generated     |  134 +
>  scripts/acpi_extract.py             |  362 ++
>  scripts/acpi_extract_preprocess.py  |   51 +
>  scripts/update-acpi.sh              |    4 +
>  98 files changed, 17366 insertions(+), 183 deletions(-)
>  create mode 100644 hw/i386/acpi-build.h
>  create mode 100644 hw/i386/acpi-defs.h
>  create mode 100644 hw/i386/bios-linker-loader.h
>  create mode 100644 include/hw/acpi/pcihp.h
>  create mode 100644 include/hw/acpi/piix4.h
>  create mode 100644 hw/acpi/pcihp.c
>  create mode 100644 hw/i386/acpi-build.c
>  create mode 100644 hw/i386/bios-linker-loader.c
>  create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
>  create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
>  create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
>  create mode 100644 hw/i386/acpi-dsdt-isa.dsl
>  create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
>  create mode 100644 hw/i386/acpi-dsdt.dsl
>  create mode 100644 hw/i386/acpi-dsdt.hex.generated
>  create mode 100644 hw/i386/q35-acpi-dsdt.dsl
>  create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
>  create mode 100644 hw/i386/ssdt-misc.dsl
>  create mode 100644 hw/i386/ssdt-misc.hex.generated
>  create mode 100644 hw/i386/ssdt-pcihp.dsl
>  create mode 100644 hw/i386/ssdt-pcihp.hex.generated
>  create mode 100644 hw/i386/ssdt-proc.dsl
>  create mode 100644 hw/i386/ssdt-proc.hex.generated
>  create mode 100755 scripts/acpi_extract.py
>  create mode 100755 scripts/acpi_extract_preprocess.py
>  create mode 100644 scripts/update-acpi.sh

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > Anthony, I know you wanted to review some of the patches,
> > since you didn't respond either all's well or you
> > could not find the time.
> > I think we are better off merging them for 1.7 and then - worst case,
> > if major issues surface - disabling the functionality at the last minute
> > than delaying the merge even more.
> 
> There is no way I'll pull this for 1.7.  Changes like this aren't going
> to get merged at the last minute.

Last minute?  This has been on list for months.

>  A good chunk of the series lacks
> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> which is the whole point of the series.

It isn't. The point is getting ACPI out of seabios.
OK what if I drop the bridge hotplug part?

> This is a huge series and I still am not convinced this is the right
> path forward.  The alternative to this series is a small set of changes
> to SeaBIOS to support PCI bridge hotplug, no?

No, we also get alternative firmwares working correctly with QEMU.

> Or 10k SLOC of code into QEMU that includes breaking migration
> compatibility.

AFAIK it doesn't break migration compatibility.

> Regards,
> 
> Anthony Liguori
> 
> > The following changes since commit e26d3e734650640fabd7d95ace4f3a6f88725e0b:
> >
> >   smbios: Factor out smbios_maybe_add_str() (2013-09-28 23:49:39 +0300)
> >
> > are available in the git repository at:
> >
> >   git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
> >
> > for you to fetch changes up to 6cab1e7000021fa6a487f67e1dba986f68fee30d:
> >
> >   acpi-build: enable hotplug for PCI bridges (2013-10-14 17:48:58 +0300)
> >
> > ----------------------------------------------------------------
> > pci, pc, acpi fixes, enhancements
> >
> > This includes some pretty big changes:
> > - pci master abort support by Marcel
> > - pci IRQ API rework by Marcel
> > - acpi generation and pci bridge hotplug support by myself
> >
> > Everything has gone through several revisions, latest versions have been on
> > list for a while without any more comments, tested by several
> > people.
> >
> > Please pull for 1.7.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> >
> > ----------------------------------------------------------------
> > Igor Mammedov (1):
> >       cleanup object.h: include error.h directly
> >
> > Marcel Apfelbaum (11):
> >       memory: Change MemoryRegion priorities from unsigned to signed
> >       docs/memory: Explictly state that MemoryRegion priority is signed
> >       hw/pci: partially handle pci master abort
> >       hw/core: Add interface to allocate and free a single IRQ
> >       hw/pci: add pci wrappers for allocating and asserting irqs
> >       hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init
> >       hw/vmxnet3: set interrupts using pci irq wrappers
> >       hw/vfio: set interrupts using pci irq wrappers
> >       hw: set interrupts using pci irq wrappers
> >       hw/pcie: AER and hot-plug events must use device's interrupt
> >       hw/pci: removed irq field from PCIDevice
> >
> > Michael S. Tsirkin (31):
> >       qom: cleanup struct Error references
> >       qom: add pointer to int property helpers
> >       pci: fix up w64 size calculation helper
> >       fw_cfg: interface to trigger callback on read
> >       loader: support for unmapped ROM blobs
> >       pcie_host: expose UNMAPPED macro
> >       pcie_host: expose address format
> >       q35: use macro for MCFG property name
> >       q35: expose mmcfg size as a property
> >       i386: add ACPI table files from seabios
> >       acpi: add rules to compile ASL source
> >       acpi: pre-compiled ASL files
> >       acpi: ssdt pcihp: updat generated file
> >       loader: use file path size from fw_cfg.h
> >       i386: add bios linker/loader
> >       loader: allow adding ROMs in done callbacks
> >       i386: define pc guest info
> >       acpi/piix: add macros for acpi property names
> >       piix: APIs for pc guest info
> >       ich9: APIs for pc guest info
> >       pvpanic: add API to access io port
> >       hpet: add API to find it
> >       acpi: add interface to access user-installed tables
> >       pc: use new api to add builtin tables
> >       i386: ACPI table generation code from seabios
> >       ssdt: fix PBLK length
> >       ssdt-proc: update generated file
> >       pci: add pci_for_each_bus_depth_first
> >       pcihp: generalization of piix4 acpi
> >       piix4: add acpi pci hotplug support
> >       acpi-build: enable hotplug for PCI bridges
> >
> >  configure                           |    9 +-
> >  hw/i386/acpi-build.h                |    9 +
> >  hw/i386/acpi-defs.h                 |  331 ++
> >  hw/i386/bios-linker-loader.h        |   27 +
> >  hw/lm32/lm32_hwsetup.h              |    2 +-
> >  include/exec/memory.h               |    4 +-
> >  include/hw/acpi/acpi.h              |    4 +
> >  include/hw/acpi/ich9.h              |    2 +
> >  include/hw/acpi/pcihp.h             |   72 +
> >  include/hw/acpi/piix4.h             |    8 +
> >  include/hw/i386/ich9.h              |    2 +
> >  include/hw/i386/pc.h                |   27 +
> >  include/hw/irq.h                    |    7 +
> >  include/hw/loader.h                 |    8 +-
> >  include/hw/nvram/fw_cfg.h           |    8 +-
> >  include/hw/pci-host/q35.h           |    2 +
> >  include/hw/pci/pci.h                |   40 +-
> >  include/hw/pci/pci_bus.h            |    1 +
> >  include/hw/pci/pcie.h               |   18 -
> >  include/hw/pci/pcie_host.h          |   27 +
> >  include/hw/sysbus.h                 |    2 +-
> >  include/hw/timer/hpet.h             |    2 +
> >  include/qom/object.h                |   73 +-
> >  hw/acpi/core.c                      |   40 +
> >  hw/acpi/ich9.c                      |   24 +
> >  hw/acpi/pcihp.c                     |  312 ++
> >  hw/acpi/piix4.c                     |  125 +-
> >  hw/audio/ac97.c                     |    4 +-
> >  hw/audio/es1370.c                   |    4 +-
> >  hw/audio/intel-hda.c                |    2 +-
> >  hw/block/nvme.c                     |    2 +-
> >  hw/char/serial-pci.c                |    5 +-
> >  hw/char/tpci200.c                   |    8 +-
> >  hw/core/irq.c                       |   16 +
> >  hw/core/loader.c                    |   31 +-
> >  hw/core/sysbus.c                    |    4 +-
> >  hw/display/qxl.c                    |    2 +-
> >  hw/i386/acpi-build.c                | 1420 +++++++
> >  hw/i386/bios-linker-loader.c        |  158 +
> >  hw/i386/pc.c                        |   25 +-
> >  hw/i386/pc_piix.c                   |    5 +
> >  hw/i386/pc_q35.c                    |    3 +
> >  hw/ide/cmd646.c                     |    2 +-
> >  hw/ide/ich.c                        |    3 +-
> >  hw/isa/lpc_ich9.c                   |   40 +
> >  hw/isa/vt82c686.c                   |    2 +-
> >  hw/misc/ivshmem.c                   |    2 +-
> >  hw/misc/pvpanic.c                   |   13 +-
> >  hw/misc/vfio.c                      |   11 +-
> >  hw/net/e1000.c                      |    2 +-
> >  hw/net/eepro100.c                   |    4 +-
> >  hw/net/ne2000.c                     |    3 +-
> >  hw/net/pcnet-pci.c                  |    3 +-
> >  hw/net/rtl8139.c                    |    2 +-
> >  hw/net/vmxnet3.c                    |   13 +-
> >  hw/nvram/fw_cfg.c                   |   33 +-
> >  hw/pci-bridge/pci_bridge_dev.c      |    2 +-
> >  hw/pci-host/piix.c                  |    8 +
> >  hw/pci-host/q35.c                   |   26 +-
> >  hw/pci/pci.c                        |  100 +-
> >  hw/pci/pcie.c                       |    4 +-
> >  hw/pci/pcie_aer.c                   |    4 +-
> >  hw/pci/pcie_host.c                  |   24 -
> >  hw/pci/shpc.c                       |    2 +-
> >  hw/scsi/esp-pci.c                   |    3 +-
> >  hw/scsi/lsi53c895a.c                |    2 +-
> >  hw/scsi/megasas.c                   |    6 +-
> >  hw/scsi/vmw_pvscsi.c                |    2 +-
> >  hw/timer/hpet.c                     |    5 +
> >  hw/usb/hcd-ehci-pci.c               |    2 +-
> >  hw/usb/hcd-ohci.c                   |    2 +-
> >  hw/usb/hcd-uhci.c                   |    6 +-
> >  hw/usb/hcd-xhci.c                   |    7 +-
> >  hw/virtio/virtio-pci.c              |    4 +-
> >  memory.c                            |    4 +-
> >  qom/object.c                        |   60 +
> >  vl.c                                |    3 +
> >  docs/memory.txt                     |    4 +
> >  hw/acpi/Makefile.objs               |    2 +-
> >  hw/i386/Makefile.objs               |   27 +
> >  hw/i386/acpi-dsdt-cpu-hotplug.dsl   |   93 +
> >  hw/i386/acpi-dsdt-dbug.dsl          |   41 +
> >  hw/i386/acpi-dsdt-hpet.dsl          |   51 +
> >  hw/i386/acpi-dsdt-isa.dsl           |  117 +
> >  hw/i386/acpi-dsdt-pci-crs.dsl       |  105 +
> >  hw/i386/acpi-dsdt.dsl               |  341 ++
> >  hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
> >  hw/i386/q35-acpi-dsdt.dsl           |  452 +++
> >  hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
> >  hw/i386/ssdt-misc.dsl               |  119 +
> >  hw/i386/ssdt-misc.hex.generated     |  386 ++
> >  hw/i386/ssdt-pcihp.dsl              |   50 +
> >  hw/i386/ssdt-pcihp.hex.generated    |  108 +
> >  hw/i386/ssdt-proc.dsl               |   63 +
> >  hw/i386/ssdt-proc.hex.generated     |  134 +
> >  scripts/acpi_extract.py             |  362 ++
> >  scripts/acpi_extract_preprocess.py  |   51 +
> >  scripts/update-acpi.sh              |    4 +
> >  98 files changed, 17366 insertions(+), 183 deletions(-)
> >  create mode 100644 hw/i386/acpi-build.h
> >  create mode 100644 hw/i386/acpi-defs.h
> >  create mode 100644 hw/i386/bios-linker-loader.h
> >  create mode 100644 include/hw/acpi/pcihp.h
> >  create mode 100644 include/hw/acpi/piix4.h
> >  create mode 100644 hw/acpi/pcihp.c
> >  create mode 100644 hw/i386/acpi-build.c
> >  create mode 100644 hw/i386/bios-linker-loader.c
> >  create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-isa.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
> >  create mode 100644 hw/i386/acpi-dsdt.dsl
> >  create mode 100644 hw/i386/acpi-dsdt.hex.generated
> >  create mode 100644 hw/i386/q35-acpi-dsdt.dsl
> >  create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
> >  create mode 100644 hw/i386/ssdt-misc.dsl
> >  create mode 100644 hw/i386/ssdt-misc.hex.generated
> >  create mode 100644 hw/i386/ssdt-pcihp.dsl
> >  create mode 100644 hw/i386/ssdt-pcihp.hex.generated
> >  create mode 100644 hw/i386/ssdt-proc.dsl
> >  create mode 100644 hw/i386/ssdt-proc.hex.generated
> >  create mode 100755 scripts/acpi_extract.py
> >  create mode 100755 scripts/acpi_extract_preprocess.py
> >  create mode 100644 scripts/update-acpi.sh

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Anthony Liguori]

On Mon, Oct 14, 2013 at 10:28 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
>> "Michael S. Tsirkin" <mst@redhat.com> writes:
>>
>> > Anthony, I know you wanted to review some of the patches,
>> > since you didn't respond either all's well or you
>> > could not find the time.
>> > I think we are better off merging them for 1.7 and then - worst case,
>> > if major issues surface - disabling the functionality at the last minute
>> > than delaying the merge even more.
>>
>> There is no way I'll pull this for 1.7.  Changes like this aren't going
>> to get merged at the last minute.
>
> Last minute?  This has been on list for months.

It doesn't matter how long the patches have been on the list.  We have
a very short testing cycle for releases.

This pull request lacks any automated testing.  Something like this
really should come with at least some qtest validation that we are
still generating the right ACPI tables but certainly could have
simpler unit tests too.

There is no statement about what manual testing you actually did.
Have you run kvm autotest?  Have you tested a variety of Windows
guests?

The pull request has a patch with a binary diff and a comment of:

"update generated file, not sure what changed"

And that didn't concern you prior to sending the pull request?

This series is not ready to merge.

>>  A good chunk of the series lacks
>> any Reviewed-bys including the actual hotplug behind a pci bridge bits
>> which is the whole point of the series.
>
> It isn't. The point is getting ACPI out of seabios.
> OK what if I drop the bridge hotplug part?

How does that address the above?

>> This is a huge series and I still am not convinced this is the right
>> path forward.  The alternative to this series is a small set of changes
>> to SeaBIOS to support PCI bridge hotplug, no?
>
> No, we also get alternative firmwares working correctly with QEMU.
>
>> Or 10k SLOC of code into QEMU that includes breaking migration
>> compatibility.
>
> AFAIK it doesn't break migration compatibility.

>From 41/43:

"The interface is actually backwards-compatible with
 existing PIIX4 ACPI (though not migration compatible)."

And does "AFAIK" translate to, "I have tested migration from new and
old and old and new with this series"?  I suspect the answer is no.

Regards,

Anthony Liguori

>> Regards,
>>
>> Anthony Liguori
>>
>> > The following changes since commit e26d3e734650640fabd7d95ace4f3a6f88725e0b:
>> >
>> >   smbios: Factor out smbios_maybe_add_str() (2013-09-28 23:49:39 +0300)
>> >
>> > are available in the git repository at:
>> >
>> >   git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
>> >
>> > for you to fetch changes up to 6cab1e7000021fa6a487f67e1dba986f68fee30d:
>> >
>> >   acpi-build: enable hotplug for PCI bridges (2013-10-14 17:48:58 +0300)
>> >
>> > ----------------------------------------------------------------
>> > pci, pc, acpi fixes, enhancements
>> >
>> > This includes some pretty big changes:
>> > - pci master abort support by Marcel
>> > - pci IRQ API rework by Marcel
>> > - acpi generation and pci bridge hotplug support by myself
>> >
>> > Everything has gone through several revisions, latest versions have been on
>> > list for a while without any more comments, tested by several
>> > people.
>> >
>> > Please pull for 1.7.
>> >
>> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
>> >
>> > ----------------------------------------------------------------
>> > Igor Mammedov (1):
>> >       cleanup object.h: include error.h directly
>> >
>> > Marcel Apfelbaum (11):
>> >       memory: Change MemoryRegion priorities from unsigned to signed
>> >       docs/memory: Explictly state that MemoryRegion priority is signed
>> >       hw/pci: partially handle pci master abort
>> >       hw/core: Add interface to allocate and free a single IRQ
>> >       hw/pci: add pci wrappers for allocating and asserting irqs
>> >       hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init
>> >       hw/vmxnet3: set interrupts using pci irq wrappers
>> >       hw/vfio: set interrupts using pci irq wrappers
>> >       hw: set interrupts using pci irq wrappers
>> >       hw/pcie: AER and hot-plug events must use device's interrupt
>> >       hw/pci: removed irq field from PCIDevice
>> >
>> > Michael S. Tsirkin (31):
>> >       qom: cleanup struct Error references
>> >       qom: add pointer to int property helpers
>> >       pci: fix up w64 size calculation helper
>> >       fw_cfg: interface to trigger callback on read
>> >       loader: support for unmapped ROM blobs
>> >       pcie_host: expose UNMAPPED macro
>> >       pcie_host: expose address format
>> >       q35: use macro for MCFG property name
>> >       q35: expose mmcfg size as a property
>> >       i386: add ACPI table files from seabios
>> >       acpi: add rules to compile ASL source
>> >       acpi: pre-compiled ASL files
>> >       acpi: ssdt pcihp: updat generated file
>> >       loader: use file path size from fw_cfg.h
>> >       i386: add bios linker/loader
>> >       loader: allow adding ROMs in done callbacks
>> >       i386: define pc guest info
>> >       acpi/piix: add macros for acpi property names
>> >       piix: APIs for pc guest info
>> >       ich9: APIs for pc guest info
>> >       pvpanic: add API to access io port
>> >       hpet: add API to find it
>> >       acpi: add interface to access user-installed tables
>> >       pc: use new api to add builtin tables
>> >       i386: ACPI table generation code from seabios
>> >       ssdt: fix PBLK length
>> >       ssdt-proc: update generated file
>> >       pci: add pci_for_each_bus_depth_first
>> >       pcihp: generalization of piix4 acpi
>> >       piix4: add acpi pci hotplug support
>> >       acpi-build: enable hotplug for PCI bridges
>> >
>> >  configure                           |    9 +-
>> >  hw/i386/acpi-build.h                |    9 +
>> >  hw/i386/acpi-defs.h                 |  331 ++
>> >  hw/i386/bios-linker-loader.h        |   27 +
>> >  hw/lm32/lm32_hwsetup.h              |    2 +-
>> >  include/exec/memory.h               |    4 +-
>> >  include/hw/acpi/acpi.h              |    4 +
>> >  include/hw/acpi/ich9.h              |    2 +
>> >  include/hw/acpi/pcihp.h             |   72 +
>> >  include/hw/acpi/piix4.h             |    8 +
>> >  include/hw/i386/ich9.h              |    2 +
>> >  include/hw/i386/pc.h                |   27 +
>> >  include/hw/irq.h                    |    7 +
>> >  include/hw/loader.h                 |    8 +-
>> >  include/hw/nvram/fw_cfg.h           |    8 +-
>> >  include/hw/pci-host/q35.h           |    2 +
>> >  include/hw/pci/pci.h                |   40 +-
>> >  include/hw/pci/pci_bus.h            |    1 +
>> >  include/hw/pci/pcie.h               |   18 -
>> >  include/hw/pci/pcie_host.h          |   27 +
>> >  include/hw/sysbus.h                 |    2 +-
>> >  include/hw/timer/hpet.h             |    2 +
>> >  include/qom/object.h                |   73 +-
>> >  hw/acpi/core.c                      |   40 +
>> >  hw/acpi/ich9.c                      |   24 +
>> >  hw/acpi/pcihp.c                     |  312 ++
>> >  hw/acpi/piix4.c                     |  125 +-
>> >  hw/audio/ac97.c                     |    4 +-
>> >  hw/audio/es1370.c                   |    4 +-
>> >  hw/audio/intel-hda.c                |    2 +-
>> >  hw/block/nvme.c                     |    2 +-
>> >  hw/char/serial-pci.c                |    5 +-
>> >  hw/char/tpci200.c                   |    8 +-
>> >  hw/core/irq.c                       |   16 +
>> >  hw/core/loader.c                    |   31 +-
>> >  hw/core/sysbus.c                    |    4 +-
>> >  hw/display/qxl.c                    |    2 +-
>> >  hw/i386/acpi-build.c                | 1420 +++++++
>> >  hw/i386/bios-linker-loader.c        |  158 +
>> >  hw/i386/pc.c                        |   25 +-
>> >  hw/i386/pc_piix.c                   |    5 +
>> >  hw/i386/pc_q35.c                    |    3 +
>> >  hw/ide/cmd646.c                     |    2 +-
>> >  hw/ide/ich.c                        |    3 +-
>> >  hw/isa/lpc_ich9.c                   |   40 +
>> >  hw/isa/vt82c686.c                   |    2 +-
>> >  hw/misc/ivshmem.c                   |    2 +-
>> >  hw/misc/pvpanic.c                   |   13 +-
>> >  hw/misc/vfio.c                      |   11 +-
>> >  hw/net/e1000.c                      |    2 +-
>> >  hw/net/eepro100.c                   |    4 +-
>> >  hw/net/ne2000.c                     |    3 +-
>> >  hw/net/pcnet-pci.c                  |    3 +-
>> >  hw/net/rtl8139.c                    |    2 +-
>> >  hw/net/vmxnet3.c                    |   13 +-
>> >  hw/nvram/fw_cfg.c                   |   33 +-
>> >  hw/pci-bridge/pci_bridge_dev.c      |    2 +-
>> >  hw/pci-host/piix.c                  |    8 +
>> >  hw/pci-host/q35.c                   |   26 +-
>> >  hw/pci/pci.c                        |  100 +-
>> >  hw/pci/pcie.c                       |    4 +-
>> >  hw/pci/pcie_aer.c                   |    4 +-
>> >  hw/pci/pcie_host.c                  |   24 -
>> >  hw/pci/shpc.c                       |    2 +-
>> >  hw/scsi/esp-pci.c                   |    3 +-
>> >  hw/scsi/lsi53c895a.c                |    2 +-
>> >  hw/scsi/megasas.c                   |    6 +-
>> >  hw/scsi/vmw_pvscsi.c                |    2 +-
>> >  hw/timer/hpet.c                     |    5 +
>> >  hw/usb/hcd-ehci-pci.c               |    2 +-
>> >  hw/usb/hcd-ohci.c                   |    2 +-
>> >  hw/usb/hcd-uhci.c                   |    6 +-
>> >  hw/usb/hcd-xhci.c                   |    7 +-
>> >  hw/virtio/virtio-pci.c              |    4 +-
>> >  memory.c                            |    4 +-
>> >  qom/object.c                        |   60 +
>> >  vl.c                                |    3 +
>> >  docs/memory.txt                     |    4 +
>> >  hw/acpi/Makefile.objs               |    2 +-
>> >  hw/i386/Makefile.objs               |   27 +
>> >  hw/i386/acpi-dsdt-cpu-hotplug.dsl   |   93 +
>> >  hw/i386/acpi-dsdt-dbug.dsl          |   41 +
>> >  hw/i386/acpi-dsdt-hpet.dsl          |   51 +
>> >  hw/i386/acpi-dsdt-isa.dsl           |  117 +
>> >  hw/i386/acpi-dsdt-pci-crs.dsl       |  105 +
>> >  hw/i386/acpi-dsdt.dsl               |  341 ++
>> >  hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
>> >  hw/i386/q35-acpi-dsdt.dsl           |  452 +++
>> >  hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
>> >  hw/i386/ssdt-misc.dsl               |  119 +
>> >  hw/i386/ssdt-misc.hex.generated     |  386 ++
>> >  hw/i386/ssdt-pcihp.dsl              |   50 +
>> >  hw/i386/ssdt-pcihp.hex.generated    |  108 +
>> >  hw/i386/ssdt-proc.dsl               |   63 +
>> >  hw/i386/ssdt-proc.hex.generated     |  134 +
>> >  scripts/acpi_extract.py             |  362 ++
>> >  scripts/acpi_extract_preprocess.py  |   51 +
>> >  scripts/update-acpi.sh              |    4 +
>> >  98 files changed, 17366 insertions(+), 183 deletions(-)
>> >  create mode 100644 hw/i386/acpi-build.h
>> >  create mode 100644 hw/i386/acpi-defs.h
>> >  create mode 100644 hw/i386/bios-linker-loader.h
>> >  create mode 100644 include/hw/acpi/pcihp.h
>> >  create mode 100644 include/hw/acpi/piix4.h
>> >  create mode 100644 hw/acpi/pcihp.c
>> >  create mode 100644 hw/i386/acpi-build.c
>> >  create mode 100644 hw/i386/bios-linker-loader.c
>> >  create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt-isa.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt.dsl
>> >  create mode 100644 hw/i386/acpi-dsdt.hex.generated
>> >  create mode 100644 hw/i386/q35-acpi-dsdt.dsl
>> >  create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
>> >  create mode 100644 hw/i386/ssdt-misc.dsl
>> >  create mode 100644 hw/i386/ssdt-misc.hex.generated
>> >  create mode 100644 hw/i386/ssdt-pcihp.dsl
>> >  create mode 100644 hw/i386/ssdt-pcihp.hex.generated
>> >  create mode 100644 hw/i386/ssdt-proc.dsl
>> >  create mode 100644 hw/i386/ssdt-proc.hex.generated
>> >  create mode 100755 scripts/acpi_extract.py
>> >  create mode 100755 scripts/acpi_extract_preprocess.py
>> >  create mode 100644 scripts/update-acpi.sh

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Paolo Bonzini]

Il 15/10/2013 15:51, Anthony Liguori ha scritto:
> From 41/43:
> 
> "The interface is actually backwards-compatible with
>  existing PIIX4 ACPI (though not migration compatible)."
> 
> And does "AFAIK" translate to, "I have tested migration from new and
> old and old and new with this series"?  I suspect the answer is no.

Since when do we support migration from new to old?

Paolo

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Anthony Liguori]

On Tue, Oct 15, 2013 at 7:01 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> Il 15/10/2013 15:51, Anthony Liguori ha scritto:
>> From 41/43:
>>
>> "The interface is actually backwards-compatible with
>>  existing PIIX4 ACPI (though not migration compatible)."
>>
>> And does "AFAIK" translate to, "I have tested migration from new and
>> old and old and new with this series"?  I suspect the answer is no.
>
> Since when do we support migration from new to old?

We allow it to break because we only send the newest version of things
but we should try our best to avoid that from happening.  That's why
we have things like subsections.

Regards,

Anthony Liguori

> Paolo

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 07:17:59AM -0700, Anthony Liguori wrote:
> On Tue, Oct 15, 2013 at 7:01 AM, Paolo Bonzini <pbonzini@redhat.com> wrote:
> > Il 15/10/2013 15:51, Anthony Liguori ha scritto:
> >> From 41/43:
> >>
> >> "The interface is actually backwards-compatible with
> >>  existing PIIX4 ACPI (though not migration compatible)."
> >>
> >> And does "AFAIK" translate to, "I have tested migration from new and
> >> old and old and new with this series"?  I suspect the answer is no.
> >
> > Since when do we support migration from new to old?
> 
> We allow it to break because we only send the newest version of things
> but we should try our best to avoid that from happening.  That's why
> we have things like subsections.
> 
> Regards,
> 
> Anthony Liguori
> 
> > Paolo

I addressed this using _TEST VMSTATE macros:

+static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
+{
+    PIIX4PMState *s = opaque;
+    return s->use_acpi_pci_hotplug;
+}
+
+static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
+{
+    PIIX4PMState *s = opaque;
+    return !s->use_acpi_pci_hotplug;
+}
+


use_acpi_pci_hotplug is set only for new machine.

Did you miss this during review or is something wrong with this?

-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Igor Mammedov]

On Tue, 15 Oct 2013 06:51:30 -0700
Anthony Liguori <anthony@codemonkey.ws> wrote:

> On Mon, Oct 14, 2013 at 10:28 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
> >> "Michael S. Tsirkin" <mst@redhat.com> writes:
> >>
> >> > Anthony, I know you wanted to review some of the patches,
> >> > since you didn't respond either all's well or you
> >> > could not find the time.
> >> > I think we are better off merging them for 1.7 and then - worst case,
> >> > if major issues surface - disabling the functionality at the last minute
> >> > than delaying the merge even more.
> >>
> >> There is no way I'll pull this for 1.7.  Changes like this aren't going
> >> to get merged at the last minute.
> >
> > Last minute?  This has been on list for months.
> 
> It doesn't matter how long the patches have been on the list.  We have
> a very short testing cycle for releases.
> 
> This pull request lacks any automated testing.  Something like this
> really should come with at least some qtest validation that we are
> still generating the right ACPI tables but certainly could have
> simpler unit tests too.
> 
> There is no statement about what manual testing you actually did.
> Have you run kvm autotest?  Have you tested a variety of Windows
> guests?
I've manually boot/install tested a bunch of x64 based OSes
rhel6/fc18/ws2008/ws2012/ws2003r2/XP
There were no regressions so far.

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 06:51:30AM -0700, Anthony Liguori wrote:
> On Mon, Oct 14, 2013 at 10:28 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
> >> "Michael S. Tsirkin" <mst@redhat.com> writes:
> >>
> >> > Anthony, I know you wanted to review some of the patches,
> >> > since you didn't respond either all's well or you
> >> > could not find the time.
> >> > I think we are better off merging them for 1.7 and then - worst case,
> >> > if major issues surface - disabling the functionality at the last minute
> >> > than delaying the merge even more.
> >>
> >> There is no way I'll pull this for 1.7.  Changes like this aren't going
> >> to get merged at the last minute.
> >
> > Last minute?  This has been on list for months.
> 
> It doesn't matter how long the patches have been on the list.  We have
> a very short testing cycle for releases.
> 
> This pull request lacks any automated testing.  Something like this
> really should come with at least some qtest validation that we are
> still generating the right ACPI tables but certainly could have
> simpler unit tests too.

It did go through autotest testing though.

> There is no statement about what manual testing you actually did.

Manually I loaded tables and verified that they match
the bios bit for bit except pointer values.

> Have you run kvm autotest?  Have you tested a variety of Windows
> guests?

Yes, both.

> The pull request has a patch with a binary diff and a comment of:
> 
> "update generated file, not sure what changed"
> 
> And that didn't concern you prior to sending the pull request?


Sorry, I forgot to update the description. V2 has it right:
IASL sticks its own version when it builds tables,
this is what changed.

> This series is not ready to merge.

Because a single commit message was out of date?

> >>  A good chunk of the series lacks
> >> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> >> which is the whole point of the series.
> >
> > It isn't. The point is getting ACPI out of seabios.
> > OK what if I drop the bridge hotplug part?
> 
> How does that address the above?

It addresses the issues you have raised which was with
the bridge.

> >> This is a huge series and I still am not convinced this is the right
> >> path forward.  The alternative to this series is a small set of changes
> >> to SeaBIOS to support PCI bridge hotplug, no?
> >
> > No, we also get alternative firmwares working correctly with QEMU.
> >
> >> Or 10k SLOC of code into QEMU that includes breaking migration
> >> compatibility.
> >
> > AFAIK it doesn't break migration compatibility.
> 
> >From 41/43:
> 
> "The interface is actually backwards-compatible with
>  existing PIIX4 ACPI (though not migration compatible)."
> 
> And does "AFAIK" translate to, "I have tested migration from new and
> old and old and new with this series"?  I suspect the answer is no.
> 
> Regards,
> 
> Anthony Liguori

But the code to handle it is there, at least.
I will test it but I think minor fixes like this can go
in after soft freeze.


-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Anthony Liguori]

On Tue, Oct 15, 2013 at 7:20 AM, Michael S. Tsirkin <mst@redhat.com> wrote:
> On Tue, Oct 15, 2013 at 06:51:30AM -0700, Anthony Liguori wrote:
>> On Mon, Oct 14, 2013 at 10:28 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
>> > On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
>> >> "Michael S. Tsirkin" <mst@redhat.com> writes:
>> >>
>> >> > Anthony, I know you wanted to review some of the patches,
>> >> > since you didn't respond either all's well or you
>> >> > could not find the time.
>> >> > I think we are better off merging them for 1.7 and then - worst case,
>> >> > if major issues surface - disabling the functionality at the last minute
>> >> > than delaying the merge even more.
>> >>
>> >> There is no way I'll pull this for 1.7.  Changes like this aren't going
>> >> to get merged at the last minute.
>> >
>> > Last minute?  This has been on list for months.
>>
>> It doesn't matter how long the patches have been on the list.  We have
>> a very short testing cycle for releases.
>>
>> This pull request lacks any automated testing.  Something like this
>> really should come with at least some qtest validation that we are
>> still generating the right ACPI tables but certainly could have
>> simpler unit tests too.
>
> It did go through autotest testing though.

This specific tree or some previous version of the series?  A full run
or just a restricted run?

>> There is no statement about what manual testing you actually did.
>
> Manually I loaded tables and verified that they match
> the bios bit for bit except pointer values.
>
>> Have you run kvm autotest?  Have you tested a variety of Windows
>> guests?
>
> Yes, both.
>
>> The pull request has a patch with a binary diff and a comment of:
>>
>> "update generated file, not sure what changed"
>>
>> And that didn't concern you prior to sending the pull request?
>
>
> Sorry, I forgot to update the description. V2 has it right:
> IASL sticks its own version when it builds tables,
> this is what changed.
>
>> This series is not ready to merge.
>
> Because a single commit message was out of date?
>
>> >>  A good chunk of the series lacks
>> >> any Reviewed-bys including the actual hotplug behind a pci bridge bits
>> >> which is the whole point of the series.
>> >
>> > It isn't. The point is getting ACPI out of seabios.
>> > OK what if I drop the bridge hotplug part?
>>
>> How does that address the above?
>
> It addresses the issues you have raised which was with
> the bridge.
>
>> >> This is a huge series and I still am not convinced this is the right
>> >> path forward.  The alternative to this series is a small set of changes
>> >> to SeaBIOS to support PCI bridge hotplug, no?
>> >
>> > No, we also get alternative firmwares working correctly with QEMU.
>> >
>> >> Or 10k SLOC of code into QEMU that includes breaking migration
>> >> compatibility.
>> >
>> > AFAIK it doesn't break migration compatibility.
>>
>> >From 41/43:
>>
>> "The interface is actually backwards-compatible with
>>  existing PIIX4 ACPI (though not migration compatible)."
>>
>> And does "AFAIK" translate to, "I have tested migration from new and
>> old and old and new with this series"?  I suspect the answer is no.
>>
>> Regards,
>>
>> Anthony Liguori
>
> But the code to handle it is there, at least.
> I will test it but I think minor fixes like this can go
> in after soft freeze.

I cannot reasonable revert a series like this before we cut GA.  We
would have to delay the release until everything was fixed.   The
release is a month away and most of us will lose at least a week to
KVM Forum so our ducks need to be in a row here.

Please put together a summary of the testing this series has gone
through.  I still think there should be automated testing as part of
this but if the manual testing is sufficiently thorough I'll
reconsider for 1.7.

Regards,

Anthony Liguori

>
> --
> MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 07:21:34AM -0700, Anthony Liguori wrote:
> On Tue, Oct 15, 2013 at 7:20 AM, Michael S. Tsirkin <mst@redhat.com> wrote:
> > On Tue, Oct 15, 2013 at 06:51:30AM -0700, Anthony Liguori wrote:
> >> On Mon, Oct 14, 2013 at 10:28 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> >> > On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
> >> >> "Michael S. Tsirkin" <mst@redhat.com> writes:
> >> >>
> >> >> > Anthony, I know you wanted to review some of the patches,
> >> >> > since you didn't respond either all's well or you
> >> >> > could not find the time.
> >> >> > I think we are better off merging them for 1.7 and then - worst case,
> >> >> > if major issues surface - disabling the functionality at the last minute
> >> >> > than delaying the merge even more.
> >> >>
> >> >> There is no way I'll pull this for 1.7.  Changes like this aren't going
> >> >> to get merged at the last minute.
> >> >
> >> > Last minute?  This has been on list for months.
> >>
> >> It doesn't matter how long the patches have been on the list.  We have
> >> a very short testing cycle for releases.
> >>
> >> This pull request lacks any automated testing.  Something like this
> >> really should come with at least some qtest validation that we are
> >> still generating the right ACPI tables but certainly could have
> >> simpler unit tests too.
> >
> > It did go through autotest testing though.
> 
> This specific tree or some previous version of the series?

This specific tree + updated seabios.

> A full run
> or just a restricted run?

All tests I normally use for PCI: install guest, migrate, virtio net+blk.

If you want more just give me a list: last I looked full run has lots of
known failures, that's one of the issues with autotest.

I think that ACPI tables being exactly identical
when used with seabios is also a convincing argument.


> >> There is no statement about what manual testing you actually did.
> >
> > Manually I loaded tables and verified that they match
> > the bios bit for bit except pointer values.
> >
> >> Have you run kvm autotest?  Have you tested a variety of Windows
> >> guests?
> >
> > Yes, both.
> >
> >> The pull request has a patch with a binary diff and a comment of:
> >>
> >> "update generated file, not sure what changed"
> >>
> >> And that didn't concern you prior to sending the pull request?
> >
> >
> > Sorry, I forgot to update the description. V2 has it right:
> > IASL sticks its own version when it builds tables,
> > this is what changed.
> >
> >> This series is not ready to merge.
> >
> > Because a single commit message was out of date?
> >
> >> >>  A good chunk of the series lacks
> >> >> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> >> >> which is the whole point of the series.
> >> >
> >> > It isn't. The point is getting ACPI out of seabios.
> >> > OK what if I drop the bridge hotplug part?
> >>
> >> How does that address the above?
> >
> > It addresses the issues you have raised which was with
> > the bridge.
> >
> >> >> This is a huge series and I still am not convinced this is the right
> >> >> path forward.  The alternative to this series is a small set of changes
> >> >> to SeaBIOS to support PCI bridge hotplug, no?
> >> >
> >> > No, we also get alternative firmwares working correctly with QEMU.
> >> >
> >> >> Or 10k SLOC of code into QEMU that includes breaking migration
> >> >> compatibility.
> >> >
> >> > AFAIK it doesn't break migration compatibility.
> >>
> >> >From 41/43:
> >>
> >> "The interface is actually backwards-compatible with
> >>  existing PIIX4 ACPI (though not migration compatible)."
> >>
> >> And does "AFAIK" translate to, "I have tested migration from new and
> >> old and old and new with this series"?  I suspect the answer is no.
> >>
> >> Regards,
> >>
> >> Anthony Liguori
> >
> > But the code to handle it is there, at least.
> > I will test it but I think minor fixes like this can go
> > in after soft freeze.
> 
> I cannot reasonable revert a series like this before we cut GA.

But we can *very* easily disable the new stuff from being exported
to guests. Just tweak machine definitions in i386/pc.


>  We
> would have to delay the release until everything was fixed.   The
> release is a month away and most of us will lose at least a week to
> KVM Forum so our ducks need to be in a row here.
> 
> Please put together a summary of the testing this series has gone
> through.  I still think there should be automated testing as part of
> this but if the manual testing is sufficiently thorough I'll
> reconsider for 1.7.

OK this goes for bridge as well or just for the infrastructure?

> Regards,
> 
> Anthony Liguori
> 
> >
> > --
> > MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 07:21:34AM -0700, Anthony Liguori wrote:
> I cannot reasonable revert a series like this before we cut GA.

It's very simple actually.
Here's a patch to disable it all.

diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 63ae2ae..1a5a70c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -59,7 +59,7 @@ static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
 
 static bool has_pvpanic;
 static bool has_pci_info = true;
-static bool has_acpi_build = true;
+static bool has_acpi_build = false;
 
 /* PC hardware initialisation */
 static void pc_init1(QEMUMachineInitArgs *args,
diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
index 4c191d3..4db95de 100644
--- a/hw/i386/pc_q35.c
+++ b/hw/i386/pc_q35.c
@@ -49,7 +49,7 @@
 
 static bool has_pvpanic;
 static bool has_pci_info = true;
-static bool has_acpi_build = true;
+static bool has_acpi_build = false;
 
 /* PC hardware initialisation */
 static void pc_q35_init(QEMUMachineInitArgs *args)

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 07:21:34AM -0700, Anthony Liguori wrote:
> Please put together a summary of the testing this series has gone
> through.  I still think there should be automated testing as part of
> this but if the manual testing is sufficiently thorough I'll
> reconsider for 1.7.
> 
> Regards,
> 
> Anthony Liguori

This is the list I have. Note: it's all x86 only: all new code
is local to x86.


Core ACPI changes:

Both piix and q35:

    KVM only:
        seabios:
        boot/install:
            rhel6/fc18/ws2008/ws2012/ws2003r2/XP

        seabios + coreboot
        fedora guest

    KVM and TCG:
    boot live CD, dump tables in guest, compare bit by bit with
    host, analyse differences (I can send diff if required)



autotest:
piix only, KVM only

  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.unattended_ins
+tall.cdrom.floppy_ks.aio_native
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.tcp
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.unix
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec.g
+zip_exec
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.fd
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.physical_resou
+rces_check
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.boot
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.reboot
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.shutdown
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.unattended_ins
+tall.cdrom.extra_cdrom_ks.aio_native
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.tcp
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.unix
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec.g
+zip_exec
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.fd
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.physical_resou
+rces_check
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.boot
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.reboot
  virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.shutdown
  boot.0



PCI bridge patches:

piix only:
    KVM and TCG:
    boot live CD linux, remove/add device by hotplug

    boot windows 7, remove/add device by hotplug


Core ACPI changes have been through much more testing.
On the other hand bridge would be much easier to revert.

If you think we reasonably can merge the bridge hotplug, please let me know
I'll address the minor comments that Paolo and you made, test cross version
compatibility and resubmit ASAP.

-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Igor Mammedov]

On Tue, 15 Oct 2013 17:51:28 +0300
"Michael S. Tsirkin" <mst@redhat.com> wrote:

> On Tue, Oct 15, 2013 at 07:21:34AM -0700, Anthony Liguori wrote:
> > Please put together a summary of the testing this series has gone
> > through.  I still think there should be automated testing as part of
> > this but if the manual testing is sufficiently thorough I'll
> > reconsider for 1.7.
> > 
> > Regards,
> > 
> > Anthony Liguori
> 
> This is the list I have. Note: it's all x86 only: all new code
> is local to x86.
> 
> 
> Core ACPI changes:
> 
> Both piix and q35:
> 
>     KVM only:
>         seabios:
>         boot/install:
>             rhel6/fc18/ws2008/ws2012/ws2003r2/XP
> 
>         seabios + coreboot
>         fedora guest
> 
>     KVM and TCG:
>     boot live CD, dump tables in guest, compare bit by bit with
>     host, analyse differences (I can send diff if required)
>
> 
> 
> autotest:
> piix only, KVM only
> 
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.unattended_ins
> +tall.cdrom.floppy_ks.aio_native
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.tcp
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.unix
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec.g
> +zip_exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.fd
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.physical_resou
> +rces_check
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.boot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.reboot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.shutdown
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.unattended_ins
> +tall.cdrom.extra_cdrom_ks.aio_native
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.tcp
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.unix
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec.g
> +zip_exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.fd
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.physical_resou
> +rces_check
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.boot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.reboot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.shutdown
>   boot.0
> 
> 
> 
> PCI bridge patches:
> 
> piix only:
>     KVM and TCG:
>     boot live CD linux, remove/add device by hotplug
> 
>     boot windows 7, remove/add device by hotplug

+     CPU hotplug with RHEL6 and ws2008/ws2012/ws2003r2 guests
 
> 
> Core ACPI changes have been through much more testing.
> On the other hand bridge would be much easier to revert.
> 
> If you think we reasonably can merge the bridge hotplug, please let me know
> I'll address the minor comments that Paolo and you made, test cross version
> compatibility and resubmit ASAP.
> 

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 05:51:28PM +0300, Michael S. Tsirkin wrote:
> On Tue, Oct 15, 2013 at 07:21:34AM -0700, Anthony Liguori wrote:
> > Please put together a summary of the testing this series has gone
> > through.  I still think there should be automated testing as part of
> > this but if the manual testing is sufficiently thorough I'll
> > reconsider for 1.7.
> > 
> > Regards,
> > 
> > Anthony Liguori
> 
> This is the list I have. Note: it's all x86 only: all new code
> is local to x86.
> 
> 
> Core ACPI changes:
> 
> Both piix and q35:
> 
>     KVM only:
>         seabios:
>         boot/install:
>             rhel6/fc18/ws2008/ws2012/ws2003r2/XP

I forgot:
	boot+hotunplug/hotplug device
             rhel6/systemrescuecd/win7/winxp

>         seabios + coreboot
>         fedora guest
> 
>     KVM and TCG:
>     boot live CD, dump tables in guest, compare bit by bit with
>     host, analyse differences (I can send diff if required)
> 
> 
> 
> autotest:
> piix only, KVM only
> 
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.unattended_ins
> +tall.cdrom.floppy_ks.aio_native
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.tcp
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.unix
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.exec.g
> +zip_exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.migrate.fd
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.physical_resou
> +rces_check
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.boot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.reboot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.Win7.x86_64.sp1.shutdown
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.unattended_ins
> +tall.cdrom.extra_cdrom_ks.aio_native
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.tcp
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.unix
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.exec.g
> +zip_exec
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.migrate.fd
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.physical_resou
> +rces_check
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.boot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.reboot
>   virt.qemu.qemu-mst-baseline-git.qcow2.virtio_blk.smp2.virtio_net.RHEL.6.4.x86_64.shutdown
>   boot.0
> 
> 
> 
> PCI bridge patches:
> 
> piix only:
>     KVM and TCG:
>     boot live CD linux, remove/add device by hotplug
> 
>     boot windows 7, remove/add device by hotplug
> 
> 
> Core ACPI changes have been through much more testing.
> On the other hand bridge would be much easier to revert.
> 
> If you think we reasonably can merge the bridge hotplug, please let me know
> I'll address the minor comments that Paolo and you made, test cross version
> compatibility and resubmit ASAP.
> 
> -- 
> MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Mon, Oct 14, 2013 at 03:42:37PM -0700, Anthony Liguori wrote:
> This is a huge series and I still am not convinced this is the right
> path forward.

Also, this kind of response is quite unexpected after this direction was
discussed multiple times and largely agreed upon on the phone meeting,
and after multiple people spent lots of time discussing and testing this
on list.

-- 
MST

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Igor Mammedov]

On Mon, 14 Oct 2013 15:42:37 -0700
Anthony Liguori <anthony@codemonkey.ws> wrote:

> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > Anthony, I know you wanted to review some of the patches,
> > since you didn't respond either all's well or you
> > could not find the time.
> > I think we are better off merging them for 1.7 and then - worst case,
> > if major issues surface - disabling the functionality at the last minute
> > than delaying the merge even more.
> 
> There is no way I'll pull this for 1.7.  Changes like this aren't going
> to get merged at the last minute.  A good chunk of the series lacks
> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> which is the whole point of the series.
>
> This is a huge series and I still am not convinced this is the right
> path forward.  The alternative to this series is a small set of changes
> to SeaBIOS to support PCI bridge hotplug, no?
It's also needed for memory hotplug to make any progress, there is no point
posting it before ACPI tables are merged.
  
> Or 10k SLOC of code into QEMU that includes breaking migration
> compatibility.
> 
> Regards,
> 
> Anthony Liguori
> 
> > The following changes since commit e26d3e734650640fabd7d95ace4f3a6f88725e0b:
> >
> >   smbios: Factor out smbios_maybe_add_str() (2013-09-28 23:49:39 +0300)
> >
> > are available in the git repository at:
> >
> >   git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
> >
> > for you to fetch changes up to 6cab1e7000021fa6a487f67e1dba986f68fee30d:
> >
> >   acpi-build: enable hotplug for PCI bridges (2013-10-14 17:48:58 +0300)
> >
> > ----------------------------------------------------------------
> > pci, pc, acpi fixes, enhancements
> >
> > This includes some pretty big changes:
> > - pci master abort support by Marcel
> > - pci IRQ API rework by Marcel
> > - acpi generation and pci bridge hotplug support by myself
> >
> > Everything has gone through several revisions, latest versions have been on
> > list for a while without any more comments, tested by several
> > people.
> >
> > Please pull for 1.7.
> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> >
> > ----------------------------------------------------------------
> > Igor Mammedov (1):
> >       cleanup object.h: include error.h directly
> >
> > Marcel Apfelbaum (11):
> >       memory: Change MemoryRegion priorities from unsigned to signed
> >       docs/memory: Explictly state that MemoryRegion priority is signed
> >       hw/pci: partially handle pci master abort
> >       hw/core: Add interface to allocate and free a single IRQ
> >       hw/pci: add pci wrappers for allocating and asserting irqs
> >       hw/pci-bridge: set PCI_INTERRUPT_PIN register before shpc init
> >       hw/vmxnet3: set interrupts using pci irq wrappers
> >       hw/vfio: set interrupts using pci irq wrappers
> >       hw: set interrupts using pci irq wrappers
> >       hw/pcie: AER and hot-plug events must use device's interrupt
> >       hw/pci: removed irq field from PCIDevice
> >
> > Michael S. Tsirkin (31):
> >       qom: cleanup struct Error references
> >       qom: add pointer to int property helpers
> >       pci: fix up w64 size calculation helper
> >       fw_cfg: interface to trigger callback on read
> >       loader: support for unmapped ROM blobs
> >       pcie_host: expose UNMAPPED macro
> >       pcie_host: expose address format
> >       q35: use macro for MCFG property name
> >       q35: expose mmcfg size as a property
> >       i386: add ACPI table files from seabios
> >       acpi: add rules to compile ASL source
> >       acpi: pre-compiled ASL files
> >       acpi: ssdt pcihp: updat generated file
> >       loader: use file path size from fw_cfg.h
> >       i386: add bios linker/loader
> >       loader: allow adding ROMs in done callbacks
> >       i386: define pc guest info
> >       acpi/piix: add macros for acpi property names
> >       piix: APIs for pc guest info
> >       ich9: APIs for pc guest info
> >       pvpanic: add API to access io port
> >       hpet: add API to find it
> >       acpi: add interface to access user-installed tables
> >       pc: use new api to add builtin tables
> >       i386: ACPI table generation code from seabios
> >       ssdt: fix PBLK length
> >       ssdt-proc: update generated file
> >       pci: add pci_for_each_bus_depth_first
> >       pcihp: generalization of piix4 acpi
> >       piix4: add acpi pci hotplug support
> >       acpi-build: enable hotplug for PCI bridges
> >
> >  configure                           |    9 +-
> >  hw/i386/acpi-build.h                |    9 +
> >  hw/i386/acpi-defs.h                 |  331 ++
> >  hw/i386/bios-linker-loader.h        |   27 +
> >  hw/lm32/lm32_hwsetup.h              |    2 +-
> >  include/exec/memory.h               |    4 +-
> >  include/hw/acpi/acpi.h              |    4 +
> >  include/hw/acpi/ich9.h              |    2 +
> >  include/hw/acpi/pcihp.h             |   72 +
> >  include/hw/acpi/piix4.h             |    8 +
> >  include/hw/i386/ich9.h              |    2 +
> >  include/hw/i386/pc.h                |   27 +
> >  include/hw/irq.h                    |    7 +
> >  include/hw/loader.h                 |    8 +-
> >  include/hw/nvram/fw_cfg.h           |    8 +-
> >  include/hw/pci-host/q35.h           |    2 +
> >  include/hw/pci/pci.h                |   40 +-
> >  include/hw/pci/pci_bus.h            |    1 +
> >  include/hw/pci/pcie.h               |   18 -
> >  include/hw/pci/pcie_host.h          |   27 +
> >  include/hw/sysbus.h                 |    2 +-
> >  include/hw/timer/hpet.h             |    2 +
> >  include/qom/object.h                |   73 +-
> >  hw/acpi/core.c                      |   40 +
> >  hw/acpi/ich9.c                      |   24 +
> >  hw/acpi/pcihp.c                     |  312 ++
> >  hw/acpi/piix4.c                     |  125 +-
> >  hw/audio/ac97.c                     |    4 +-
> >  hw/audio/es1370.c                   |    4 +-
> >  hw/audio/intel-hda.c                |    2 +-
> >  hw/block/nvme.c                     |    2 +-
> >  hw/char/serial-pci.c                |    5 +-
> >  hw/char/tpci200.c                   |    8 +-
> >  hw/core/irq.c                       |   16 +
> >  hw/core/loader.c                    |   31 +-
> >  hw/core/sysbus.c                    |    4 +-
> >  hw/display/qxl.c                    |    2 +-
> >  hw/i386/acpi-build.c                | 1420 +++++++
> >  hw/i386/bios-linker-loader.c        |  158 +
> >  hw/i386/pc.c                        |   25 +-
> >  hw/i386/pc_piix.c                   |    5 +
> >  hw/i386/pc_q35.c                    |    3 +
> >  hw/ide/cmd646.c                     |    2 +-
> >  hw/ide/ich.c                        |    3 +-
> >  hw/isa/lpc_ich9.c                   |   40 +
> >  hw/isa/vt82c686.c                   |    2 +-
> >  hw/misc/ivshmem.c                   |    2 +-
> >  hw/misc/pvpanic.c                   |   13 +-
> >  hw/misc/vfio.c                      |   11 +-
> >  hw/net/e1000.c                      |    2 +-
> >  hw/net/eepro100.c                   |    4 +-
> >  hw/net/ne2000.c                     |    3 +-
> >  hw/net/pcnet-pci.c                  |    3 +-
> >  hw/net/rtl8139.c                    |    2 +-
> >  hw/net/vmxnet3.c                    |   13 +-
> >  hw/nvram/fw_cfg.c                   |   33 +-
> >  hw/pci-bridge/pci_bridge_dev.c      |    2 +-
> >  hw/pci-host/piix.c                  |    8 +
> >  hw/pci-host/q35.c                   |   26 +-
> >  hw/pci/pci.c                        |  100 +-
> >  hw/pci/pcie.c                       |    4 +-
> >  hw/pci/pcie_aer.c                   |    4 +-
> >  hw/pci/pcie_host.c                  |   24 -
> >  hw/pci/shpc.c                       |    2 +-
> >  hw/scsi/esp-pci.c                   |    3 +-
> >  hw/scsi/lsi53c895a.c                |    2 +-
> >  hw/scsi/megasas.c                   |    6 +-
> >  hw/scsi/vmw_pvscsi.c                |    2 +-
> >  hw/timer/hpet.c                     |    5 +
> >  hw/usb/hcd-ehci-pci.c               |    2 +-
> >  hw/usb/hcd-ohci.c                   |    2 +-
> >  hw/usb/hcd-uhci.c                   |    6 +-
> >  hw/usb/hcd-xhci.c                   |    7 +-
> >  hw/virtio/virtio-pci.c              |    4 +-
> >  memory.c                            |    4 +-
> >  qom/object.c                        |   60 +
> >  vl.c                                |    3 +
> >  docs/memory.txt                     |    4 +
> >  hw/acpi/Makefile.objs               |    2 +-
> >  hw/i386/Makefile.objs               |   27 +
> >  hw/i386/acpi-dsdt-cpu-hotplug.dsl   |   93 +
> >  hw/i386/acpi-dsdt-dbug.dsl          |   41 +
> >  hw/i386/acpi-dsdt-hpet.dsl          |   51 +
> >  hw/i386/acpi-dsdt-isa.dsl           |  117 +
> >  hw/i386/acpi-dsdt-pci-crs.dsl       |  105 +
> >  hw/i386/acpi-dsdt.dsl               |  341 ++
> >  hw/i386/acpi-dsdt.hex.generated     | 4409 +++++++++++++++++++++
> >  hw/i386/q35-acpi-dsdt.dsl           |  452 +++
> >  hw/i386/q35-acpi-dsdt.hex.generated | 7346 +++++++++++++++++++++++++++++++++++
> >  hw/i386/ssdt-misc.dsl               |  119 +
> >  hw/i386/ssdt-misc.hex.generated     |  386 ++
> >  hw/i386/ssdt-pcihp.dsl              |   50 +
> >  hw/i386/ssdt-pcihp.hex.generated    |  108 +
> >  hw/i386/ssdt-proc.dsl               |   63 +
> >  hw/i386/ssdt-proc.hex.generated     |  134 +
> >  scripts/acpi_extract.py             |  362 ++
> >  scripts/acpi_extract_preprocess.py  |   51 +
> >  scripts/update-acpi.sh              |    4 +
> >  98 files changed, 17366 insertions(+), 183 deletions(-)
> >  create mode 100644 hw/i386/acpi-build.h
> >  create mode 100644 hw/i386/acpi-defs.h
> >  create mode 100644 hw/i386/bios-linker-loader.h
> >  create mode 100644 include/hw/acpi/pcihp.h
> >  create mode 100644 include/hw/acpi/piix4.h
> >  create mode 100644 hw/acpi/pcihp.c
> >  create mode 100644 hw/i386/acpi-build.c
> >  create mode 100644 hw/i386/bios-linker-loader.c
> >  create mode 100644 hw/i386/acpi-dsdt-cpu-hotplug.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-dbug.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-hpet.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-isa.dsl
> >  create mode 100644 hw/i386/acpi-dsdt-pci-crs.dsl
> >  create mode 100644 hw/i386/acpi-dsdt.dsl
> >  create mode 100644 hw/i386/acpi-dsdt.hex.generated
> >  create mode 100644 hw/i386/q35-acpi-dsdt.dsl
> >  create mode 100644 hw/i386/q35-acpi-dsdt.hex.generated
> >  create mode 100644 hw/i386/ssdt-misc.dsl
> >  create mode 100644 hw/i386/ssdt-misc.hex.generated
> >  create mode 100644 hw/i386/ssdt-pcihp.dsl
> >  create mode 100644 hw/i386/ssdt-pcihp.hex.generated
> >  create mode 100644 hw/i386/ssdt-proc.dsl
> >  create mode 100644 hw/i386/ssdt-proc.hex.generated
> >  create mode 100755 scripts/acpi_extract.py
> >  create mode 100755 scripts/acpi_extract_preprocess.py
> >  create mode 100644 scripts/update-acpi.sh

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Gerd Hoffmann]

On Mo, 2013-10-14 at 15:42 -0700, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > Anthony, I know you wanted to review some of the patches,
> > since you didn't respond either all's well or you
> > could not find the time.
> > I think we are better off merging them for 1.7 and then - worst case,
> > if major issues surface - disabling the functionality at the last minute
> > than delaying the merge even more.
> 
> There is no way I'll pull this for 1.7.  Changes like this aren't going
> to get merged at the last minute.

Hmm?  Patches are discussed and tested for months, with the core not
having seen no big changes since weeks.  Recent revisions of the series
are only fixing the bugs which showed up in testing and some finishing
touches.  It certainly isn't something new poping out of the blue the
last minute.

Why do you ignore the patches and discussions until things are settled
and the pull request comes in?

> A good chunk of the series lacks
> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> which is the whole point of the series.

pci bridge hotplug is only a part of the whole picture.

It is about using an existing standard (ACPI) to communicate hardware
config information between qemu and the guest OS.  Without requiring the
middle man (seabios or other firmware) knowing details it doesn't need
to know for its own job.  And avoid creating one paravirtual interface
after the other to give the firmware the information it needs to
generate the acpi tables.

It is also about having *one* instance (qemu) generates the acpi tables
instead of expecting each firmware duplicate that functionality.  It
makes live a lot easier for alternative firmwares such as ovmf and
coreboot.  For coreboot the patch series (with the complementary
coreboot patches to load the tables from qemu) is a big step forward to
feature parity with seabios.

And, yes, implementing features like pci bridge hotplug and memory
hotplug (oh, and lets not forget pvpanic) on top of the acpi generation
series is alot easier:

 * You implement it in qemu, and you are done.

> This is a huge series and I still am not convinced this is the right
> path forward.  The alternative to this series is a small set of changes
> to SeaBIOS to support PCI bridge hotplug, no?

No.  The alternative is:

 * You create a paravirt interface to communicate the
   config information for $newfeature.
 * You implement that in qemu.
 * You implement that in seabios.
 * You implement that in OVMF.
 * You implement that in coreboot.

> Or 10k SLOC of code into QEMU that includes breaking migration
> compatibility.

On the plus side we can stop maintaining those 10k SLOC in seabios.

The bits will stay there for a while for compatibility with older qemu
versions, but don't need much care any more as all new stuff will go
into qemu instead.

cheers,
  Gerd

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Anthony Liguori]

On Tue, Oct 15, 2013 at 6:43 AM, Gerd Hoffmann <kraxel@redhat.com> wrote:
> On Mo, 2013-10-14 at 15:42 -0700, Anthony Liguori wrote:
>> "Michael S. Tsirkin" <mst@redhat.com> writes:
>>
>> > Anthony, I know you wanted to review some of the patches,
>> > since you didn't respond either all's well or you
>> > could not find the time.
>> > I think we are better off merging them for 1.7 and then - worst case,
>> > if major issues surface - disabling the functionality at the last minute
>> > than delaying the merge even more.
>>
>> There is no way I'll pull this for 1.7.  Changes like this aren't going
>> to get merged at the last minute.
>
> Hmm?  Patches are discussed and tested for months, with the core not
> having seen no big changes since weeks.  Recent revisions of the series
> are only fixing the bugs which showed up in testing and some finishing
> touches.  It certainly isn't something new poping out of the blue the
> last minute.
>
> Why do you ignore the patches and discussions until things are settled
> and the pull request comes in?

Sorry, I shouldn't mix in general complaining with why I am not happy
with this pull request.  I already said I would take this change given
a clear use-case and I would have merged it if the series was in a
better state.  I am sympathetic to not wanting to maintain this stuff
in SeaBIOS.

But I am not happy with the state of the pull request for reasons I
explained in another note.

Regards,

Anthony Liguori

>
>> A good chunk of the series lacks
>> any Reviewed-bys including the actual hotplug behind a pci bridge bits
>> which is the whole point of the series.
>
> pci bridge hotplug is only a part of the whole picture.
>
> It is about using an existing standard (ACPI) to communicate hardware
> config information between qemu and the guest OS.  Without requiring the
> middle man (seabios or other firmware) knowing details it doesn't need
> to know for its own job.  And avoid creating one paravirtual interface
> after the other to give the firmware the information it needs to
> generate the acpi tables.
>
> It is also about having *one* instance (qemu) generates the acpi tables
> instead of expecting each firmware duplicate that functionality.  It
> makes live a lot easier for alternative firmwares such as ovmf and
> coreboot.  For coreboot the patch series (with the complementary
> coreboot patches to load the tables from qemu) is a big step forward to
> feature parity with seabios.
>
> And, yes, implementing features like pci bridge hotplug and memory
> hotplug (oh, and lets not forget pvpanic) on top of the acpi generation
> series is alot easier:
>
>  * You implement it in qemu, and you are done.
>
>> This is a huge series and I still am not convinced this is the right
>> path forward.  The alternative to this series is a small set of changes
>> to SeaBIOS to support PCI bridge hotplug, no?
>
> No.  The alternative is:
>
>  * You create a paravirt interface to communicate the
>    config information for $newfeature.
>  * You implement that in qemu.
>  * You implement that in seabios.
>  * You implement that in OVMF.
>  * You implement that in coreboot.
>
>> Or 10k SLOC of code into QEMU that includes breaking migration
>> compatibility.
>
> On the plus side we can stop maintaining those 10k SLOC in seabios.
>
> The bits will stay there for a while for compatibility with older qemu
> versions, but don't need much care any more as all new stuff will go
> into qemu instead.
>
> cheers,
>   Gerd
>
>
>

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Michael S. Tsirkin]

On Tue, Oct 15, 2013 at 06:53:54AM -0700, Anthony Liguori wrote:
> On Tue, Oct 15, 2013 at 6:43 AM, Gerd Hoffmann <kraxel@redhat.com> wrote:
> > On Mo, 2013-10-14 at 15:42 -0700, Anthony Liguori wrote:
> >> "Michael S. Tsirkin" <mst@redhat.com> writes:
> >>
> >> > Anthony, I know you wanted to review some of the patches,
> >> > since you didn't respond either all's well or you
> >> > could not find the time.
> >> > I think we are better off merging them for 1.7 and then - worst case,
> >> > if major issues surface - disabling the functionality at the last minute
> >> > than delaying the merge even more.
> >>
> >> There is no way I'll pull this for 1.7.  Changes like this aren't going
> >> to get merged at the last minute.
> >
> > Hmm?  Patches are discussed and tested for months, with the core not
> > having seen no big changes since weeks.  Recent revisions of the series
> > are only fixing the bugs which showed up in testing and some finishing
> > touches.  It certainly isn't something new poping out of the blue the
> > last minute.
> >
> > Why do you ignore the patches and discussions until things are settled
> > and the pull request comes in?
> 
> Sorry, I shouldn't mix in general complaining with why I am not happy
> with this pull request.  I already said I would take this change given
> a clear use-case and I would have merged it if the series was in a
> better state.  I am sympathetic to not wanting to maintain this stuff
> in SeaBIOS.
> 
> But I am not happy with the state of the pull request for reasons I
> explained in another note.
> 
> Regards,
> 
> Anthony Liguori

Is v2 better?

I think I have addressed your complaints by
1. dropping bridge code for now
2. fixing the commit log issue for the patch with generated code
   that you noticed

The use case is coreboot support.

> >
> >> A good chunk of the series lacks
> >> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> >> which is the whole point of the series.
> >
> > pci bridge hotplug is only a part of the whole picture.
> >
> > It is about using an existing standard (ACPI) to communicate hardware
> > config information between qemu and the guest OS.  Without requiring the
> > middle man (seabios or other firmware) knowing details it doesn't need
> > to know for its own job.  And avoid creating one paravirtual interface
> > after the other to give the firmware the information it needs to
> > generate the acpi tables.
> >
> > It is also about having *one* instance (qemu) generates the acpi tables
> > instead of expecting each firmware duplicate that functionality.  It
> > makes live a lot easier for alternative firmwares such as ovmf and
> > coreboot.  For coreboot the patch series (with the complementary
> > coreboot patches to load the tables from qemu) is a big step forward to
> > feature parity with seabios.
> >
> > And, yes, implementing features like pci bridge hotplug and memory
> > hotplug (oh, and lets not forget pvpanic) on top of the acpi generation
> > series is alot easier:
> >
> >  * You implement it in qemu, and you are done.
> >
> >> This is a huge series and I still am not convinced this is the right
> >> path forward.  The alternative to this series is a small set of changes
> >> to SeaBIOS to support PCI bridge hotplug, no?
> >
> > No.  The alternative is:
> >
> >  * You create a paravirt interface to communicate the
> >    config information for $newfeature.
> >  * You implement that in qemu.
> >  * You implement that in seabios.
> >  * You implement that in OVMF.
> >  * You implement that in coreboot.
> >
> >> Or 10k SLOC of code into QEMU that includes breaking migration
> >> compatibility.
> >
> > On the plus side we can stop maintaining those 10k SLOC in seabios.
> >
> > The bits will stay there for a while for compatibility with older qemu
> > versions, but don't need much care any more as all new stuff will go
> > into qemu instead.
> >
> > cheers,
> >   Gerd
> >
> >
> >

Re: [Qemu-devel] [PULL 00/43] pci, pc, acpi fixes, enhancements

[Gerd Hoffmann]

On Mo, 2013-10-14 at 15:42 -0700, Anthony Liguori wrote:
> "Michael S. Tsirkin" <mst@redhat.com> writes:
> 
> > Anthony, I know you wanted to review some of the patches,
> > since you didn't respond either all's well or you
> > could not find the time.
> > I think we are better off merging them for 1.7 and then - worst case,
> > if major issues surface - disabling the functionality at the last minute
> > than delaying the merge even more.
> 
> There is no way I'll pull this for 1.7.  Changes like this aren't going
> to get merged at the last minute.

Hmm?  Patches are discussed and tested for months, with the core not
having seen no big changes since weeks.  Recent revisions of the series
are only fixing the bugs which showed up in testing and some finishing
touches.  It certainly isn't something new poping out of the blue the
last minute.

Why do you ignore the patches and discussions until things are settled
and the pull request comes in?

> A good chunk of the series lacks
> any Reviewed-bys including the actual hotplug behind a pci bridge bits
> which is the whole point of the series.

pci bridge hotplug is only a part of the whole picture.

It is about using an existing standard (ACPI) to communicate hardware
config information between qemu and the guest OS.  Without requiring the
middle man (seabios or other firmware) knowing details it doesn't need
to know for its own job.  And avoid creating one paravirtual interface
after the other to give the firmware the information it needs to
generate the acpi tables.

It is also about having *one* instance (qemu) generates the acpi tables
instead of expecting each firmware duplicate that functionality.  It
makes live a lot easier for alternative firmwares such as ovmf and
coreboot.  For coreboot the patch series (with the complementary
coreboot patches to load the tables from qemu) is a big step forward to
feature parity with seabios.

And, yes, it makes implementing features like pci bridge hotplug and
memory hotplug (oh, and lets not forget pvpanic) alot easier:

 * You implement it in qemu, and you are done.

> This is a huge series and I still am not convinced this is the right
> path forward.  The alternative to this series is a small set of changes
> to SeaBIOS to support PCI bridge hotplug, no?

No.  The alternative is:

 * You create a paravirt interface to communicate the
   config information for $newfeature.
 * You implement that in qemu.
 * You implement that in seabios.
 * You implement that in OVMF.
 * You implement that in coreboot.

> Or 10k SLOC of code into QEMU that includes breaking migration
> compatibility.

On the plus side we can stop maintaining those 10k SLOC in seabios.

The bits will stay there for a while for compatibility with older qemu
versions, but don't need much care any more as all new stuff will go
into qemu instead.

cheers,
  Gerd