From: Nathan Rossi <nathan@nathanrossi.com>
To: Alistair Francis <alistair.francis@xilinx.com>
Cc: peter.maydell@linaro.org,
Peter Crosthwaite <crosthwaitepeter@gmail.com>,
qemu-devel@nongnu.org, alindsay@codeaurora.org,
cov@codeaurora.org
Subject: Re: [Qemu-devel] [PATCH v1 1/3] target-arm: Add the pmceid0 and pmceid1 registers
Date: Fri, 5 Feb 2016 23:08:42 +1000 [thread overview]
Message-ID: <CA+aJhH2Khqw77PtvmvEBf9Eyv3TKy+1pfHSnN4u2X4ZTtgVqHQ@mail.gmail.com> (raw)
In-Reply-To: <0dd1e7f1975002650a10588d683ad3bc988fe87b.1454545837.git.alistair.francis@xilinx.com>
On Thu, Feb 4, 2016 at 10:34 AM, Alistair Francis
<alistair.francis@xilinx.com> wrote:
> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Tested-by: Nathan Rossi <nathan@nathanrossi.com>
> ---
>
> target-arm/cpu-qom.h | 2 ++
> target-arm/cpu.c | 2 ++
> target-arm/cpu64.c | 2 ++
> target-arm/helper.c | 8 ++++++++
> 4 files changed, 14 insertions(+)
>
> diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
> index 07c0a71..1cc4502 100644
> --- a/target-arm/cpu-qom.h
> +++ b/target-arm/cpu-qom.h
> @@ -148,6 +148,8 @@ typedef struct ARMCPU {
> uint32_t id_pfr0;
> uint32_t id_pfr1;
> uint32_t id_dfr0;
> + uint32_t pmceid0;
> + uint32_t pmceid1;
> uint32_t id_afr0;
> uint32_t id_mmfr0;
> uint32_t id_mmfr1;
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 0e582c4..d3d789c 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -1147,6 +1147,8 @@ static void cortex_a15_initfn(Object *obj)
> cpu->id_pfr0 = 0x00001131;
> cpu->id_pfr1 = 0x00011011;
> cpu->id_dfr0 = 0x02010555;
> + cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */
> + cpu->pmceid1 = 0x00000000;
> cpu->id_afr0 = 0x00000000;
> cpu->id_mmfr0 = 0x10201105;
> cpu->id_mmfr1 = 0x20000000;
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index c847513..8c4b6fd 100644
> --- a/target-arm/cpu64.c
> +++ b/target-arm/cpu64.c
> @@ -134,6 +134,8 @@ static void aarch64_a57_initfn(Object *obj)
> cpu->id_isar5 = 0x00011121;
> cpu->id_aa64pfr0 = 0x00002222;
> cpu->id_aa64dfr0 = 0x10305106;
> + cpu->pmceid0 = 0x00000481; /* PMUv3 events 0x0, 0x8, and 0x11 */
> + cpu->pmceid1 = 0x00000000;
> cpu->id_aa64isar0 = 0x00011120;
> cpu->id_aa64mmfr0 = 0x00001124;
> cpu->dbgdidr = 0x3516d000;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index ae02486..100b6ad 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -4192,6 +4192,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
> .access = PL1_R, .type = ARM_CP_CONST,
> .resetvalue = cpu->id_aa64dfr1 },
> + { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->pmceid0},
> + { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
> + .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
> + .access = PL1_R, .type = ARM_CP_CONST,
> + .resetvalue = cpu->pmceid1},
> { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
> .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
> .access = PL1_R, .type = ARM_CP_CONST,
> --
> 2.5.0
>
next prev parent reply other threads:[~2016-02-05 13:08 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-04 0:34 [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers Alistair Francis
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 1/3] target-arm: Add the pmceid0 and pmceid1 registers Alistair Francis
2016-02-05 13:08 ` Nathan Rossi [this message]
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 2/3] target-arm: Add Some of the performance monitor registers Alistair Francis
2016-02-05 13:08 ` Nathan Rossi
2016-02-04 0:34 ` [Qemu-devel] [PATCH v1 3/3] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers Alistair Francis
2016-02-05 13:09 ` Nathan Rossi
2016-02-04 13:39 ` [Qemu-devel] [PATCH v1 0/3] Extend the performance monitoring registers Aaron Lindsay
2016-02-04 18:52 ` Alistair Francis
2016-02-05 13:37 ` Aaron Lindsay
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