From: Furquan Shaikh <furquan@rivosinc.com>
To: Richard Henderson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH] riscv: Make semihosting configurable for all privilege modes
Date: Fri, 12 Aug 2022 17:50:47 -0700 [thread overview]
Message-ID: <CA+tJHD6gNrtcrZ9bkDet8NuiR8mcSQfeN-Rk3dtm3LmeakKnvQ@mail.gmail.com> (raw)
In-Reply-To: <804cd7cd-e83c-2b89-f2ba-cc2ca5c7f835@linaro.org>
On Fri, Aug 12, 2022 at 5:30 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 8/12/22 16:57, Furquan Shaikh wrote:
> > I am not sure if I understood your comment correctly. Currently, qemu
> > has a check in `riscv_cpu_do_interrupt` to allow semihosting calls
> > only in S and M modes. This prevents semihosting calls from U mode.
> > This patch changes the default behavior of checking `>= PRV_S` for
> > semihosting and instead replaces it with the usage of
> > ebreak{m,s,u,vs,vu} properties to allow the user to configure what
> > modes should allow semihosting calls when `-semihosting` argument is
> > selected.
>
> Why do you need such fine-grained control? What is the use-case?
I ran into a problem when I was testing a project (with a microkernel
in M-mode and tasks in U-mode) that uses semihosting for debugging.
The semihosting worked fine for M-mode but not in U-mode. As I started
digging into this, I realized that this is because qemu restricts
semihosting to only M and S modes. From reading the debug spec, I
understood that the DCSR presents options for ebreak behavior in each
mode including VS and VU. Adding CPU settable features to enable
ebreak behavior seemed like a flexible solution to support different
cases:
1. Old behavior of restricting semihosting to M and S modes by setting
only ebreakm and ebreaks.
2. My case of enabling semihosting to work in U-mode by setting only ebreaku.
3. Any future case where users would want to enable semihosting in
either M,S,U,VS or VU modes or any combination of these.
>
> r~
next prev parent reply other threads:[~2022-08-13 0:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-11 20:41 [PATCH] riscv: Make semihosting configurable for all privilege modes Furquan Shaikh
2022-08-11 20:56 ` Furquan Shaikh
2022-08-11 23:27 ` Philippe Mathieu-Daudé via
2022-08-12 11:04 ` Andrew Jones
2022-08-12 22:05 ` Furquan Shaikh
2022-08-12 23:00 ` Palmer Dabbelt
2022-08-12 23:28 ` Furquan Shaikh
2022-08-12 11:28 ` Peter Maydell
2022-08-12 23:11 ` Furquan Shaikh
2022-08-12 23:27 ` Richard Henderson
2022-08-12 23:42 ` Richard Henderson
2022-08-12 23:57 ` Furquan Shaikh
2022-08-13 0:30 ` Richard Henderson
2022-08-13 0:50 ` Furquan Shaikh [this message]
2022-08-13 2:31 ` Richard Henderson
2022-08-13 5:22 ` Furquan Shaikh
2022-08-13 10:19 ` Peter Maydell
2022-08-14 22:03 ` Alistair Francis
2022-08-15 6:24 ` Furquan Shaikh
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