[PATCH 0/2] target/i386: Some mmx/sse instructions don't require

[PATCH 0/2] target/i386: Some mmx/sse instructions don't require

[Wei Li]

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/427

All instructions decoded by 'gen_see' is assumed to require CRO.TS=0. But
according to SDM, CRC32 doesn't require it. In fact, EMMS, FMMS and some
mmx/sse instructions(0F38F[0-F], 0F3AF[0-F]) don't require it.

To solve the problem, first to move EMMS and FMMS out of gen_sse. Then
instructions in 'gen_sse' require it only when modrm & 0xF0 is false.

Wei Li (2):
  Move EMMS and FEMMS instructions out of gen_sse
  Some mmx/sse instructions in 'gen_sse' don't require CRO.TS=0

 target/i386/tcg/translate.c | 45 +++++++++++++++++--------------------
 1 file changed, 21 insertions(+), 24 deletions(-)

-- 
2.30.2

[PATCH 1/2] Move EMMS and FEMMS instructions out of gen_sse

[Wei Li]

Move EMMS and FEMMS instructions out of gen_sse to avoid the requirement
of CR0.TS and get a better code readability.

Signed-off-by: Wei Li <lw945lw945@yahoo.com>
---
 target/i386/tcg/translate.c | 28 ++++++++++++----------------
 1 file changed, 12 insertions(+), 16 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 2a94d33742..fe9fcdae96 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3154,20 +3154,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
         && (b != 0x38 && b != 0x3a)) {
         goto unknown_op;
     }
-    if (b == 0x0e) {
-        if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
-            /* If we were fully decoding this we might use illegal_op.  */
-            goto unknown_op;
-        }
-        /* femms */
-        gen_helper_emms(cpu_env);
-        return;
-    }
-    if (b == 0x77) {
-        /* emms */
-        gen_helper_emms(cpu_env);
-        return;
-    }
     /* prepare MMX state (XXX: optimize by storing fptt and fptags in
        the static cpu state) */
     if (!is_xmm) {
@@ -8451,14 +8437,24 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
 
         set_cc_op(s, CC_OP_POPCNT);
         break;
-    case 0x10e ... 0x10f:
+    case 0x10e: /* femms */
+        if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW)) {
+            /* If we were fully decoding this we might use illegal_op.  */
+            goto unknown_op;
+        }
+        /* fall through */
+    case 0x177: /* emms */
+        gen_helper_emms(cpu_env);
+        break;
+    case 0x10f:
         /* 3DNow! instructions, ignore prefixes */
         s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
         /* fall through */
     case 0x110 ... 0x117:
     case 0x128 ... 0x12f:
     case 0x138 ... 0x13a:
-    case 0x150 ... 0x179:
+    case 0x150 ... 0x176:
+    case 0x178 ... 0x179:
     case 0x17c ... 0x17f:
     case 0x1c2:
     case 0x1c4 ... 0x1c6:
-- 
2.30.2

[PATCH 2/2] Some mmx/sse instructions in 'gen_sse' don't require CRO.TS=0

[Wei Li]

Some instructions in 'gen_sse' don't require CRO.TS=0 and the opcode of them are
0F38F[0-F], 0F3AF[0-F].

Signed-off-by: Wei Li <lw945lw945@yahoo.com>
---
 target/i386/tcg/translate.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index fe9fcdae96..14cf11771c 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3139,8 +3139,16 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
             is_xmm = 1;
         }
     }
+
+    modrm = x86_ldub_code(env, s);
+    reg = ((modrm >> 3) & 7);
+    if (is_xmm) {
+        reg |= REX_R(s);
+    }
+    mod = (modrm >> 6) & 3;
     /* simple MMX/SSE operation */
-    if (s->flags & HF_TS_MASK) {
+    if ((s->flags & HF_TS_MASK)
+        && (!(modrm & 0xF0))) {
         gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
         return;
     }
@@ -3159,13 +3167,6 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b,
     if (!is_xmm) {
         gen_helper_enter_mmx(cpu_env);
     }
-
-    modrm = x86_ldub_code(env, s);
-    reg = ((modrm >> 3) & 7);
-    if (is_xmm) {
-        reg |= REX_R(s);
-    }
-    mod = (modrm >> 6) & 3;
     if (sse_fn_epp == SSE_SPECIAL) {
         b |= (b1 << 8);
         switch(b) {
-- 
2.30.2

Re: [PATCH 0/2] target/i386: Some mmx/sse instructions don't require

[Wei Li]

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Ping......

And the title is target/i386: Some mmx/sse instructions don't require
CR0.TS=0

On Fri, Mar 25, 2022 at 10:55 PM Wei Li <lw945lw945@yahoo.com> wrote:

> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/427
>
> All instructions decoded by 'gen_see' is assumed to require CRO.TS=0. But
> according to SDM, CRC32 doesn't require it. In fact, EMMS, FMMS and some
> mmx/sse instructions(0F38F[0-F], 0F3AF[0-F]) don't require it.
>
> To solve the problem, first to move EMMS and FMMS out of gen_sse. Then
> instructions in 'gen_sse' require it only when modrm & 0xF0 is false.
>
> Wei Li (2):
>   Move EMMS and FEMMS instructions out of gen_sse
>   Some mmx/sse instructions in 'gen_sse' don't require CRO.TS=0
>
>  target/i386/tcg/translate.c | 45 +++++++++++++++++--------------------
>  1 file changed, 21 insertions(+), 24 deletions(-)
>
> --
> 2.30.2
>
>
>
Thanks.
--
Wei Li

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