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Mon, 23 Mar 2026 14:26:11 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Taylor Simpson Date: Mon, 23 Mar 2026 15:25:59 -0600 X-Gm-Features: AaiRm52ZYF830kFAiMr_v6x-WKPRA88D_sYZLQ07yjggUtFhyPlAkqErgvBbfro Message-ID: Subject: Re: [PATCH 07/13] target/hexagon: add v68 HVX IEEE float conversion insns To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="00000000000012485f064db7afc6" Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --00000000000012485f064db7afc6 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > Add HVX IEEE floating-point conversion instructions: > - vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations > - vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions > - vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float > - vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int > > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > target/hexagon/mmvec/kvx_ieee.h | 21 +++++ > target/hexagon/mmvec/kvx_ieee.c | 98 ++++++++++++++++++++ > target/hexagon/imported/mmvec/encode_ext.def | 18 ++++ > target/hexagon/imported/mmvec/ext.idef | 97 +++++++++++++++++++ > 4 files changed, 234 insertions(+) > > diff --git a/target/hexagon/mmvec/kvx_ieee.c > b/target/hexagon/mmvec/kvx_ieee.c > index 33621a15f3..bbeec09707 100644 > --- a/target/hexagon/mmvec/kvx_ieee.c > +++ b/target/hexagon/mmvec/kvx_ieee.c > @@ -131,3 +131,101 @@ uint16_t qf_min_hf(uint16_t a1, uint16_t a2, > float_status *fp_status) > if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) return a1; > return fp_min_hf(a1, a2, fp_status); > } > + > +uint16_t f32_to_f16(uint32_t a, float_status *fp_status) > +{ > + return float16_val(float32_to_float16(make_float32(a), true, > fp_status)); > +} > + > +uint32_t f16_to_f32(uint16_t a, float_status *fp_status) > +{ > + return float32_val(float16_to_float32(make_float16(a), true, > fp_status)); > +} > + > +uint16_t f16_to_uh(uint16_t op1, float_status *fp_status) > +{ > + return float16_to_uint16_scalbn(make_float16(op1), > + float_round_nearest_even, > Does HVX always use this rounding mode? The scalar core uses the rounding mode in USR. There are several more instances below. > + 0, fp_status); > +} > + > +int16_t f16_to_h(uint16_t op1, float_status *fp_status) > +{ > + return float16_to_int16_scalbn(make_float16(op1), > + float_round_nearest_even, + 0, fp_status); > +} > + > +uint8_t f16_to_ub(uint16_t op1, float_status *fp_status) > +{ > + return float16_to_uint8_scalbn(make_float16(op1), > + float_round_nearest_even, + 0, fp_status); > +} > + > +int8_t f16_to_b(uint16_t op1, float_status *fp_status) > +{ > + return float16_to_int8_scalbn(make_float16(op1), > + float_round_nearest_even, + 0, fp_status); > +} > + > +uint16_t uh_to_f16(uint16_t op1) > +{ > + return uint64_to_float16_scalbn(op1, float_round_nearest_even, 0); > +} > + > +uint16_t h_to_f16(int16_t op1) > +{ > + return int64_to_float16_scalbn(op1, float_round_nearest_even, 0); > +} > + > +uint16_t ub_to_f16(uint8_t op1) > +{ > + return uint64_to_float16_scalbn(op1, float_round_nearest_even, 0); > +} > + > +uint16_t b_to_f16(int8_t op1) > +{ > + return int64_to_float16_scalbn(op1, float_round_nearest_even, 0); > +} > + > +int32_t conv_sf_w(int32_t a, float_status *fp_status) > +{ > + return float32_val(int32_to_float32(a, fp_status)); > +} > + > +int16_t conv_hf_h(int16_t a, float_status *fp_status) > +{ > + return float16_val(int16_to_float16(a, fp_status)); > +} > + > +int32_t conv_w_sf(uint32_t a, float_status *fp_status) > +{ > + float_status scratch_fpst =3D {}; > + const float32 W_MAX =3D int32_to_float32(INT32_MAX, &scratch_fpst); > + const float32 W_MIN =3D int32_to_float32(INT32_MIN, &scratch_fpst); > + float32 f1 =3D make_float32(a); > + > + if (float32_is_any_nan(f1) || float32_is_infinity(f1) || > + float32_le_quiet(W_MAX, f1, fp_status) || > + float32_le_quiet(f1, W_MIN, fp_status)) { > + return float32_is_neg(f1) ? INT32_MIN : INT32_MAX; > + } > Does float32_to_int32 handle these checks? > + return float32_to_int32_round_to_zero(f1, fp_status); > Rounding mode? > +} > + > +int16_t conv_h_hf(uint16_t a, float_status *fp_status) > +{/ > + float_status scratch_fpst =3D {}; > + const float16 H_MAX =3D int16_to_float16(INT16_MAX, &scratch_fpst); > + const float16 H_MIN =3D int16_to_float16(INT16_MIN, &scratch_fpst); > + float16 f1 =3D make_float16(a); > + > + if (float16_is_any_nan(f1) || float16_is_infinity(f1) || > + float16_le_quiet(H_MAX, f1, fp_status) || > + float16_le_quiet(f1, H_MIN, fp_status)) { > + return float16_is_neg(f1) ? INT16_MIN : INT16_MAX; > + } > + return float16_to_int16_round_to_zero(f1, fp_status); > +} > Ditto Thanks, Taylor --00000000000012485f064db7afc6 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23,= 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= > wrote:
Add = HVX IEEE floating-point conversion instructions:
- vconv_hf_h, vconv_h_hf, vconv_sf_w, vconv_w_sf: vconv operations
- vcvt_hf_sf, vcvt_sf_hf: float <-> half float conversions
- vcvt_hf_b, vcvt_hf_h, vcvt_hf_ub, vcvt_hf_uh: int to half float
- vcvt_b_hf, vcvt_h_hf, vcvt_ub_hf, vcvt_uh_hf: half float to int

Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm= .com>
---
=C2=A0target/hexagon/mmvec/kvx_ieee.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 21 +++++
=C2=A0target/hexagon/mmvec/kvx_ieee.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 98 ++++++++++++++++++++
=C2=A0target/hexagon/imported/mmvec/encode_ext.def | 18 ++++
=C2=A0target/hexagon/imported/mmvec/ext.idef=C2=A0 =C2=A0 =C2=A0 =C2=A0| 97= +++++++++++++++++++
=C2=A04 files changed, 234 insertions(+)

diff --git a/target/hexagon/mmvec/kvx_ieee.c b/target/hexagon/mmvec/kvx= _ieee.c
index 33621a15f3..bbeec09707 100644
--- a/target/hexagon/mmvec/kvx_ieee.c
+++ b/target/hexagon/mmvec/kvx_ieee.c
@@ -131,3 +131,101 @@ uint16_t qf_min_hf(uint16_t a1, uint16_t a2, float_st= atus *fp_status)
=C2=A0 =C2=A0 =C2=A0if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) r= eturn a1;
=C2=A0 =C2=A0 =C2=A0return fp_min_hf(a1, a2, fp_status);
=C2=A0}
+
+uint16_t f32_to_f16(uint32_t a, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_val(float32_to_float16(make_float32(a), true,= fp_status));
+}
+
+uint32_t f16_to_f32(uint16_t a, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float32_val(float16_to_float32(make_float16(a), true,= fp_status));
+}
+
+uint16_t f16_to_uh(uint16_t op1, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_to_uint16_scalbn(make_float16(op1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 float_round_nearest_ev= en,

Does HVX always use this rounding m= ode?=C2=A0 The scalar core uses the rounding mode in USR.

There are several more instances below.
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0, fp_status);
+}
+
+int16_t f16_to_h(uint16_t op1, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_to_int16_scalbn(make_float16(op1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0float_round_nearest_eve= n,=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, fp_status);
+}
+
+uint8_t f16_to_ub(uint16_t op1, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_to_uint8_scalbn(make_float16(op1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0float_round_nearest_eve= n,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, fp_status);
+}
+
+int8_t f16_to_b(uint16_t op1, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_to_int8_scalbn(make_float16(op1),
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0float_round_nearest_eve= n,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00, fp_status);
+}
+
+uint16_t uh_to_f16(uint16_t op1)
+{
+=C2=A0 =C2=A0 return uint64_to_float16_scalbn(op1, float_round_nearest_eve= n, 0);
+}
+
+uint16_t h_to_f16(int16_t op1)
+{
+=C2=A0 =C2=A0 return int64_to_float16_scalbn(op1, float_round_nearest_even= , 0);
+}
+
+uint16_t ub_to_f16(uint8_t op1)
+{
+=C2=A0 =C2=A0 return uint64_to_float16_scalbn(op1, float_round_nearest_eve= n, 0);
+}
+
+uint16_t b_to_f16(int8_t op1)
+{
+=C2=A0 =C2=A0 return int64_to_float16_scalbn(op1, float_round_nearest_even= , 0);
+}
+
+int32_t conv_sf_w(int32_t a, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float32_val(int32_to_float32(a, fp_status));
+}
+
+int16_t conv_hf_h(int16_t a, float_status *fp_status)
+{
+=C2=A0 =C2=A0 return float16_val(int16_to_float16(a, fp_status));
+}
+
+int32_t conv_w_sf(uint32_t a, float_status *fp_status)
+{
+=C2=A0 =C2=A0 float_status scratch_fpst =3D {};
+=C2=A0 =C2=A0 const float32 W_MAX =3D int32_to_float32(INT32_MAX, &scr= atch_fpst);
+=C2=A0 =C2=A0 const float32 W_MIN =3D int32_to_float32(INT32_MIN, &scr= atch_fpst);
+=C2=A0 =C2=A0 float32 f1 =3D make_float32(a);
+
+=C2=A0 =C2=A0 if (float32_is_any_nan(f1) || float32_is_infinity(f1) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float32_le_quiet(W_MAX, f1, fp_status) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float32_le_quiet(f1, W_MIN, fp_status)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return float32_is_neg(f1) ? INT32_MIN : INT32_= MAX;
+=C2=A0 =C2=A0 }

Does float32_to_int32 = handle these checks?
=C2=A0
+=C2=A0 =C2=A0 return float32_to_int32_round_to_zero(f1, fp_status);

Rounding mode?
=C2=A0
+}
+
+int16_t conv_h_hf(uint16_t a, float_status *fp_status)
+{/
+=C2=A0 =C2=A0 float_status scratch_fpst =3D {};
+=C2=A0 =C2=A0 const float16 H_MAX =3D int16_to_float16(INT16_MAX, &scr= atch_fpst);
+=C2=A0 =C2=A0 const float16 H_MIN =3D int16_to_float16(INT16_MIN, &scr= atch_fpst);
+=C2=A0 =C2=A0 float16 f1 =3D make_float16(a);
+
+=C2=A0 =C2=A0 if (float16_is_any_nan(f1) || float16_is_infinity(f1) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float16_le_quiet(H_MAX, f1, fp_status) ||
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float16_le_quiet(f1, H_MIN, fp_status)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 return float16_is_neg(f1) ? INT16_MIN : INT16_= MAX;
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 return float16_to_int16_round_to_zero(f1, fp_status);
+}

Ditto
=C2=A0
Tha= nks,
Taylor

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