From: Taylor Simpson <ltaylorsimpson@gmail.com>
To: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng,
anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org,
quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com
Subject: Re: [PATCH 12/13] tests/hexagon: add tests for v68 HVX IEEE float conversions
Date: Tue, 24 Mar 2026 13:30:46 -0600 [thread overview]
Message-ID: <CAATN3NpWTU_Aqn+EruVRRMjEjCWNs4g+fO8fWq=kVqDze=kD8A@mail.gmail.com> (raw)
In-Reply-To: <b3c261d1c76838c3b6c593ae77dc0b1ed1459f32.1774271525.git.matheus.bernardino@oss.qualcomm.com>
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On Mon, Mar 23, 2026 at 7:16 AM Matheus Tavares Bernardino <
matheus.bernardino@oss.qualcomm.com> wrote:
> Signed-off-by: Matheus Tavares Bernardino <
> matheus.bernardino@oss.qualcomm.com>
> ---
> tests/tcg/hexagon/hex_test.h | 15 +++
> tests/tcg/hexagon/hvx_misc.h | 2 +
> tests/tcg/hexagon/fp_hvx_cvt.c | 194 ++++++++++++++++++++++++++++++
> tests/tcg/hexagon/Makefile.target | 3 +
> 4 files changed, 214 insertions(+)
> create mode 100644 tests/tcg/hexagon/fp_hvx_cvt.c
>
> diff --git a/tests/tcg/hexagon/fp_hvx_cvt.c
> b/tests/tcg/hexagon/fp_hvx_cvt.c
> new file mode 100644
> index 0000000000..7497455ac6
> --- /dev/null
> +++ b/tests/tcg/hexagon/fp_hvx_cvt.c
> @@ -0,0 +1,194 @@
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include <stdio.h>
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include <string.h>
> +#include <hexagon_types.h>
> +#include <hvx_hexagon_protos.h>
> +
> +#if __HEXAGON_ARCH__ > 75
> +#error "After v75, compiler will replace some FP HVX instructions."
> +#endif
> +
> +int err;
> +#include "hvx_misc.h"
> +#include "hex_test.h"
> +
> +#define TEST_EXP(TO, FROM, VAL, EXP) do { \
> + ((MMVector *)&buffer)->FROM[index] = VAL; \
> + expect[0].TO[index] = EXP; \
> + index++; \
> +} while (0)
> +
> +#define DEF_TEST_CVT(TO, FROM, TESTS) \
> + void test_vcvt_##TO##_##FROM(void) \
>
static
> + { \
> + HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \
> + HVX_Vector buffer; \
> + int index = 0; \
> + memset(&buffer, 0, sizeof(buffer)); \
> + memset(expect, 0, sizeof(expect)); \
> + TESTS \
> + *hvx_output = Q6_V##TO##_vcvt_V##FROM(buffer); \
> + check_output_##TO(__LINE__, 1); \
> + }
> +
> +DEF_TEST_CVT(uh, hf, { \
> + TEST_EXP(uh, hf, HF_QNaN, UINT16_MAX); \
> + TEST_EXP(uh, hf, HF_SNaN, UINT16_MAX); \
> + TEST_EXP(uh, hf, HF_QNaN_neg, UINT16_MAX); \
> + TEST_EXP(uh, hf, HF_INF, UINT16_MAX); \
> + TEST_EXP(uh, hf, HF_INF_neg, 0); \
> + TEST_EXP(uh, hf, HF_neg_two, 0); \
> + TEST_EXP(uh, hf, HF_zero_neg, 0); \
> + TEST_EXP(uh, hf, raw_hf((_Float16)2.1), 2); \
> + TEST_EXP(uh, hf, HF_one_recip, 1); \
> +})
> +
> +DEF_TEST_CVT(h, hf, { \
> + TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \
> + TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \
> + TEST_EXP(h, hf, HF_QNaN_neg, INT16_MAX); \
> + TEST_EXP(h, hf, HF_INF, INT16_MAX); \
> + TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \
> + TEST_EXP(h, hf, HF_neg_two, -2); \
> + TEST_EXP(h, hf, HF_zero_neg, 0); \
> + TEST_EXP(h, hf, raw_hf((_Float16)2.1), 2); \
> + TEST_EXP(h, hf, HF_one_recip, 1); \
> +})
> +
> +/*
> + * Some cvt operations take two vectors as input and perform the
> following:
> + * VdV.TO[4*i] = OP(VuV.FROM[2*i]);
> + * VdV.TO[4*i+1] = OP(VuV.FROM[2*i+1]);
> + * VdV.TO[4*i+2] = OP(VvV.FROM[2*i]);
> + * VdV.TO[4*i+3] = OP(VvV.FROM[2*i+1]))
> + * We use bf_index and index in a way that the tests are always done
> either
> + * using the first or third line of the above snippet.
> + */
> +#define TEST_EXP_2(TO, FROM, VAL, EXP) do { \
> + ((MMVector *)&buffers[bf_index])->FROM[2 * index] = VAL; \
> + expect[0].TO[(4 * index) + (2 * bf_index)] = EXP; \
> + index++; \
> + bf_index = (bf_index + 1) % 2; \
> +} while (0)
> +
> +#define DEF_TEST_CVT_2(TO, FROM, TESTS) \
> + void test_vcvt_##TO##_##FROM(void) \
>
static
> + { \
> + HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \
> + HVX_Vector buffers[2]; \
> + int index = 0, bf_index = 0; \
> + memset(&buffers, 0, sizeof(buffers)); \
> + memset(expect, 0, sizeof(expect)); \
> + TESTS \
> + *hvx_output = Q6_V##TO##_vcvt_V##FROM##V##FROM(buffers[0],
> buffers[1]); \
> + check_output_##TO(__LINE__, 1); \
> + }
> +
> +DEF_TEST_CVT_2(ub, hf, { \
> + TEST_EXP_2(ub, hf, HF_QNaN, UINT8_MAX); \
> + TEST_EXP_2(ub, hf, HF_SNaN, UINT8_MAX); \
> + TEST_EXP_2(ub, hf, HF_QNaN_neg, UINT8_MAX); \
> + TEST_EXP_2(ub, hf, HF_INF, UINT8_MAX); \
> + TEST_EXP_2(ub, hf, HF_INF_neg, 0); \
> + TEST_EXP_2(ub, hf, HF_small_neg, 0); \
> + TEST_EXP_2(ub, hf, HF_neg_two, 0); \
> + TEST_EXP_2(ub, hf, HF_zero_neg, 0); \
> + TEST_EXP_2(ub, hf, raw_hf((_Float16)2.1), 2); \
> + TEST_EXP_2(ub, hf, HF_one_recip, 1); \
> +})
> +
> +DEF_TEST_CVT_2(b, hf, { \
> + TEST_EXP_2(b, hf, HF_QNaN, INT8_MAX); \
> + TEST_EXP_2(b, hf, HF_SNaN, INT8_MAX); \
> + TEST_EXP_2(b, hf, HF_QNaN_neg, INT8_MAX); \
> + TEST_EXP_2(b, hf, HF_INF, INT8_MAX); \
> + TEST_EXP_2(b, hf, HF_INF_neg, INT8_MIN); \
> + TEST_EXP_2(b, hf, HF_small_neg, 0); \
> + TEST_EXP_2(b, hf, HF_neg_two, -2); \
> + TEST_EXP_2(b, hf, HF_zero_neg, 0); \
> + TEST_EXP_2(b, hf, raw_hf((_Float16)2.1), 2); \
> + TEST_EXP_2(b, hf, HF_one_recip, 1); \
> +})
> +
> +#define DEF_TEST_VCONV(TO, FROM, TESTS) \
> + void test_vconv_##TO##_##FROM(void) \
>
static
> + { \
> + HVX_Vector *hvx_output = (HVX_Vector *)&output[0]; \
> + HVX_Vector buffer; \
> + int index = 0; \
> + memset(&buffer, 0, sizeof(buffer)); \
> + memset(expect, 0, sizeof(expect)); \
> + TESTS \
> + *hvx_output = Q6_V##TO##_equals_V##FROM(buffer); \
> + check_output_##TO(__LINE__, 1); \
> + }
> +
> +DEF_TEST_VCONV(w, sf, { \
> + TEST_EXP(w, sf, SF_QNaN, INT32_MAX); \
> + TEST_EXP(w, sf, SF_SNaN, INT32_MAX); \
> + TEST_EXP(w, sf, SF_QNaN_neg, INT32_MIN); \
> + TEST_EXP(w, sf, SF_INF, INT32_MAX); \
> + TEST_EXP(w, sf, SF_INF_neg, INT32_MIN); \
> + TEST_EXP(w, sf, SF_small_neg, 0); \
> + TEST_EXP(w, sf, SF_neg_two, -2); \
> + TEST_EXP(w, sf, SF_zero_neg, 0); \
> + TEST_EXP(w, sf, raw_sf(2.1f), 2); \
> + TEST_EXP(w, sf, raw_sf(2.8f), 2); \
> +})
> +
> +DEF_TEST_VCONV(h, hf, { \
> + TEST_EXP(h, hf, HF_QNaN, INT16_MAX); \
> + TEST_EXP(h, hf, HF_SNaN, INT16_MAX); \
> + TEST_EXP(h, hf, HF_QNaN_neg, INT16_MIN); \
> + TEST_EXP(h, hf, HF_INF, INT16_MAX); \
> + TEST_EXP(h, hf, HF_INF_neg, INT16_MIN); \
> + TEST_EXP(h, hf, HF_small_neg, 0); \
> + TEST_EXP(h, hf, HF_neg_two, -2); \
> + TEST_EXP(h, hf, HF_zero_neg, 0); \
> + TEST_EXP(h, hf, raw_hf(2.1), 2); \
> + TEST_EXP(h, hf, raw_hf(2.8), 2); \
> +})
> +
> +DEF_TEST_VCONV(hf, h, { \
> + TEST_EXP(hf, h, INT16_MAX, HF_QNaN); \
> + TEST_EXP(hf, h, INT16_MAX, HF_SNaN); \
> + TEST_EXP(hf, h, INT16_MIN, HF_QNaN_neg); \
> + TEST_EXP(hf, h, INT16_MAX, HF_INF); \
> + TEST_EXP(hf, h, INT16_MIN, HF_INF_neg); \
> + TEST_EXP(hf, h, 0, HF_small_neg); \
> + TEST_EXP(hf, h, -2, HF_neg_two); \
> + TEST_EXP(hf, h, 0, HF_zero_neg); \
> + TEST_EXP(hf, h, 2, raw_hf(2.1)); \
> + TEST_EXP(hf, h, 2, raw_hf(2.8)); \
> +})
> +
> +DEF_TEST_VCONV(sf, w, { \
> + TEST_EXP(sf, w, INT32_MAX, SF_QNaN); \
> + TEST_EXP(sf, w, INT32_MAX, SF_SNaN); \
> + TEST_EXP(sf, w, INT32_MIN, SF_QNaN_neg); \
> + TEST_EXP(sf, w, INT32_MAX, SF_INF); \
> + TEST_EXP(sf, w, INT32_MIN, SF_INF_neg); \
> + TEST_EXP(sf, w, 0, SF_small_neg); \
> + TEST_EXP(sf, w, -2, SF_neg_two); \
> + TEST_EXP(sf, w, 0, SF_zero_neg); \
> + TEST_EXP(sf, w, 2, raw_sf(2.1f)); \
> + TEST_EXP(sf, w, 2, raw_sf(2.8f)); \
> +})
> +
> +int main(void)
> +{
> + test_vcvt_uh_hf();
> + test_vcvt_h_hf();
> + test_vcvt_ub_hf();
> + test_vcvt_b_hf();
> + test_vconv_w_sf();
>
Several more of these were created above but not called here. Marking them
static will flag the errors.
> + puts(err ? "FAIL" : "PASS");
> + return err ? 1 : 0;
> +}
>
Also, add checks for FP flags.
Thanks,
Taylor
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next prev parent reply other threads:[~2026-03-24 19:31 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-23 13:15 [PATCH 00/13] hexagon: add missing HVX float instructions Matheus Tavares Bernardino
2026-03-23 13:15 ` [PATCH 01/13] tests/docker: Update hexagon cross toolchain to 22.1.0 Matheus Tavares Bernardino
2026-03-23 13:15 ` [PATCH 02/13] target/hexagon: fix incorrect/too-permissive HVX encodings Matheus Tavares Bernardino
2026-03-23 19:21 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 03/13] target/hexagon/cpu: add HVX IEEE FP extension Matheus Tavares Bernardino
2026-03-23 19:32 ` Taylor Simpson
2026-03-24 16:52 ` Matheus Bernardino
2026-03-24 18:48 ` Taylor Simpson
2026-03-24 19:20 ` Brian Cain
2026-03-24 19:46 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 04/13] target/hexagon: add v68 HVX IEEE float arithmetic insns Matheus Tavares Bernardino
2026-03-23 20:28 ` Taylor Simpson
2026-03-24 19:30 ` Matheus Bernardino
2026-03-24 19:51 ` Taylor Simpson
2026-03-24 19:59 ` Matheus Bernardino
2026-03-25 1:18 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 05/13] target/hexagon: add v68 HVX IEEE float min/max insns Matheus Tavares Bernardino
2026-03-23 20:47 ` Taylor Simpson
2026-03-24 20:15 ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 06/13] target/hexagon: add v68 HVX IEEE float misc insns Matheus Tavares Bernardino
2026-03-23 21:08 ` Taylor Simpson
2026-03-24 20:25 ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 07/13] target/hexagon: add v68 HVX IEEE float conversion insns Matheus Tavares Bernardino
2026-03-23 21:25 ` Taylor Simpson
2026-03-24 21:04 ` Matheus Bernardino
2026-03-25 1:15 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 08/13] target/hexagon: add v68 HVX IEEE float compare insns Matheus Tavares Bernardino
2026-03-23 21:42 ` Taylor Simpson
2026-03-26 13:00 ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 09/13] target/hexagon: add v73 HVX IEEE bfloat16 insns Matheus Tavares Bernardino
2026-03-23 22:03 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 10/13] tests/hexagon: add tests for v68 HVX IEEE float arithmetics Matheus Tavares Bernardino
2026-03-24 19:05 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 11/13] tests/hexagon: add tests for v68 HVX IEEE float min/max Matheus Tavares Bernardino
2026-03-24 19:07 ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 12/13] tests/hexagon: add tests for v68 HVX IEEE float conversions Matheus Tavares Bernardino
2026-03-24 19:30 ` Taylor Simpson [this message]
2026-03-23 13:15 ` [PATCH 13/13] tests/hexagon: add tests for v68 HVX IEEE float comparisons Matheus Tavares Bernardino
2026-03-24 19:37 ` Taylor Simpson
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