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Tue, 24 Mar 2026 12:05:39 -0700 (PDT) MIME-Version: 1.0 References: <82c5487435a72c68ceec1c09dd6fb986409328e1.1774271525.git.matheus.bernardino@oss.qualcomm.com> In-Reply-To: <82c5487435a72c68ceec1c09dd6fb986409328e1.1774271525.git.matheus.bernardino@oss.qualcomm.com> From: Taylor Simpson Date: Tue, 24 Mar 2026 13:05:28 -0600 X-Gm-Features: AaiRm534NtYCcygvGG175OOg9heji9TkL3ZYGYY-0WTpYRM2sp0ljm-WBcIXNbU Message-ID: Subject: Re: [PATCH 10/13] tests/hexagon: add tests for v68 HVX IEEE float arithmetics To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="0000000000004b774c064dc9d6b8" Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000004b774c064dc9d6b8 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > tests/tcg/hexagon/hvx_misc.h | 12 +++ > tests/tcg/hexagon/fp_hvx.c | 129 ++++++++++++++++++++++++++++ > tests/tcg/hexagon/fp_hvx_disabled.c | 32 +++++++ > tests/tcg/hexagon/Makefile.target | 8 ++ > 4 files changed, 181 insertions(+) > create mode 100644 tests/tcg/hexagon/fp_hvx.c > create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c > > diff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c > new file mode 100644 > index 0000000000..85b8ff78ed > --- /dev/null > +++ b/tests/tcg/hexagon/fp_hvx.c > @@ -0,0 +1,129 @@ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +int err; > +#include "hvx_misc.h" > + > +#if __HEXAGON_ARCH__ > 75 > +#error "After v75, compiler will replace some FP HVX instructions." > +#endif > + > > +/***********************************************************************= ******* > + * NAN handling > + > *************************************************************************= ****/ > + > +#define isnan(X) \ > + (sizeof(X) =3D=3D bytes_hf ? ((raw_hf(X) & ~0x8000) > 0x7c00) : \ > + ((raw_sf(X) & ~(1 << 31)) > 0x7f800000UL)) > + > +#define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A)) > +#define NAN_SF float_sf(0x7FFFFFFF) > +#define NAN_HF float_hf(0x7FFF) > + > > +/***********************************************************************= ******* > + * Binary operations > + > *************************************************************************= ****/ > + > +#define DEF_TEST_OP_2(vop, op, type_res, type_arg) \ > + static void test_##vop##_##type_res##_##type_arg(void) \ > + { \ > + memset(expect, 0xff, sizeof(expect)); \ > + memset(output, 0xff, sizeof(expect)); \ > sizeof(output) > + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; \ > + HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[0]; \ > + HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[0]; \ > + \ > + *hvx_output =3D \ > + > Q6_V##type_res##_##vop##_V##type_arg##V##type_arg(hvx_buffer0, \ > + > hvx_buffer1); \ > + \ > + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / bytes_##type_res; i++= ) { > \ > + expect[0].type_res[i] =3D \ > + > raw_##type_res(op(float_##type_arg(buffer0[0].type_arg[i]), \ > + > float_##type_arg(buffer1[0].type_arg[i]))); \ > + } \ > Put this in a loop over the input buffers to get more input values. Then change the second argument to check_output below. > + check_output_##type_res(__LINE__, 1); \ > + } > + > +#define SUM(X, Y, DEF_NAN) CHECK_NAN((X) + (Y), DEF_NAN) > +#define SUB(X, Y, DEF_NAN) CHECK_NAN((X) - (Y), DEF_NAN) > +#define MULT(X, Y, DEF_NAN) CHECK_NAN((X) * (Y), DEF_NAN) > + > +#define SUM_SF(X, Y) SUM(X, Y, NAN_SF) > +#define SUM_HF(X, Y) SUM(X, Y, NAN_HF) > +#define SUB_SF(X, Y) SUB(X, Y, NAN_SF) > +#define SUB_HF(X, Y) SUB(X, Y, NAN_HF) > +#define MULT_SF(X, Y) MULT(X, Y, NAN_SF) > +#define MULT_HF(X, Y) MULT(X, Y, NAN_HF) > + > +DEF_TEST_OP_2(vadd, SUM_SF, sf, sf); > +DEF_TEST_OP_2(vadd, SUM_HF, hf, hf); > +DEF_TEST_OP_2(vsub, SUB_SF, sf, sf); > +DEF_TEST_OP_2(vsub, SUB_HF, hf, hf); > +DEF_TEST_OP_2(vmpy, MULT_SF, sf, sf); > +DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf); > + > > +/***********************************************************************= ******* > + * Other tests > + > *************************************************************************= ****/ > + > +void test_vdmpy_sf_hf(bool acc) > +{ > + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; > + HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[0]; > + HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[0]; > + > + uint32_t PREFIL_VAL =3D 0x111222; > + memset(expect, 0xff, sizeof(expect)); > + *hvx_output =3D Q6_V_vsplat_R(PREFIL_VAL); > + > + if (!acc) { > + *hvx_output =3D Q6_Vsf_vdmpy_VhfVhf(hvx_buffer0, hvx_buffer1); > + } else { > + *hvx_output =3D Q6_Vsf_vdmpyacc_VsfVhfVhf(*hvx_output, hvx_buffe= r0, > + hvx_buffer1); > + } > + > + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { > + float a1 =3D float_hf_to_sf(float_hf(buffer0[0].hf[2 * i + 1])); > + float a2 =3D float_hf_to_sf(float_hf(buffer0[0].hf[2 * i])); > + float a3 =3D float_hf_to_sf(float_hf(buffer1[0].hf[2 * i + 1])); > + float a4 =3D float_hf_to_sf(float_hf(buffer1[0].hf[2 * i])); > + float prev =3D acc ? float_sf(PREFIL_VAL) : 0; > + expect[0].sf[i] =3D raw_sf(CHECK_NAN((a1 * a3) + (a2 * a4) + pre= v, > NAN_SF)); > + } > Put this into a loop also. > + > + check_output_sf(__LINE__, 1); > +} > + > +int main(void) > +{ > + init_buffers(); > The init_buffers function is designed to create inputs for non-FP functions= . Create a new function to initialize the buffers with interesting FP values (e.g., NaN, large FP values that will lead to overflow). Also, see my prior comment about FP flags. We'll want to check those here. We should also add some tests with packets. See my prior comment about .new values. > + > + /* add/sub */ > + test_vadd_sf_sf(); > + test_vadd_hf_hf(); > + test_vsub_sf_sf(); > + test_vsub_hf_hf(); > + > + /* multiply */ > + test_vmpy_sf_sf(); > + test_vmpy_hf_hf(); > + > + /* dot product */ > + test_vdmpy_sf_hf(false); > + test_vdmpy_sf_hf(true); > + > + puts(err ? "FAIL" : "PASS"); > + return err ? 1 : 0; > +} > diff --git a/tests/tcg/hexagon/fp_hvx_disabled.c > b/tests/tcg/hexagon/fp_hvx_disabled.c > new file mode 100644 > index 0000000000..af409ab8d2 > --- /dev/null > +++ b/tests/tcg/hexagon/fp_hvx_disabled.c > @@ -0,0 +1,32 @@ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include > +#include > +#include > +#include > + > +int err; > +#include "hvx_misc.h" > + > +int main(void) > +{ > + asm volatile("r0 =3D #0xff\n" > + "v0 =3D vsplat(r0)\n" > + "vmem(%1 + #0) =3D v0\n" > + "r1 =3D #0x1\n" > + "v1 =3D vsplat(r1)\n" > + "v2 =3D vsplat(r1)\n" > + "v0.sf =3D vadd(v1.sf, v2.sf)\n" > + "vmem(%0 + #0) =3D v0\n" > + : > + : "r"(output), "r"(expect) > + : "r0", "r1", "v0", "v1", "v2", "memory"); > Add a test where the result is used in a .new context. > + > + check_output_w(__LINE__, 1); > + puts(err ? "FAIL" : "PASS"); > + return err ? 1 : 0; > +} > > --0000000000004b774c064dc9d6b8 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23, 2026= at 7:16=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qua= lcomm.com> wrote:
Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@o= ss.qualcomm.com>
---
=C2=A0tests/tcg/hexagon/hvx_misc.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 12 ++= +
=C2=A0tests/tcg/hexagon/fp_hvx.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 129 ++= ++++++++++++++++++++++++++
=C2=A0tests/tcg/hexagon/fp_hvx_disabled.c |=C2=A0 32 +++++++
=C2=A0tests/tcg/hexagon/Makefile.target=C2=A0 =C2=A0|=C2=A0 =C2=A08 ++
=C2=A04 files changed, 181 insertions(+)
=C2=A0create mode 100644 tests/tcg/hexagon/fp_hvx.c
=C2=A0create mode 100644 tests/tcg/hexagon/fp_hvx_disabled.c

diff --git a/tests/tcg/hexagon/fp_hvx.c b/tests/tcg/hexagon/fp_hvx.c new file mode 100644
index 0000000000..85b8ff78ed
--- /dev/null
+++ b/tests/tcg/hexagon/fp_hvx.c
@@ -0,0 +1,129 @@
+/*
+ *=C2=A0 Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries= .
+ *
+ *=C2=A0 SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <hexagon_types.h>
+#include <hvx_hexagon_protos.h>
+
+int err;
+#include "hvx_misc.h"
+
+#if __HEXAGON_ARCH__ > 75
+#error "After v75, compiler will replace some FP HVX instructions.&qu= ot;
+#endif
+
+/*************************************************************************= *****
+ * NAN handling
+ *************************************************************************= ****/
+
+#define isnan(X) \
+=C2=A0 =C2=A0 =C2=A0(sizeof(X) =3D=3D bytes_hf ? ((raw_hf(X) & ~0x8000= ) > 0x7c00) : \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ((raw_sf(X) & ~(1 << 31)) > 0x= 7f800000UL))
+
+#define CHECK_NAN(A, DEF_NAN) (isnan(A) ? DEF_NAN : (A))
+#define NAN_SF float_sf(0x7FFFFFFF)
+#define NAN_HF float_hf(0x7FFF)
+
+/*************************************************************************= *****
+ * Binary operations
+ *************************************************************************= ****/
+
+#define DEF_TEST_OP_2(vop, op, type_res, type_arg) \
+=C2=A0 =C2=A0 static void test_##vop##_##type_res##_##type_arg(void) \
+=C2=A0 =C2=A0 { \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 memset(expect, 0xff, sizeof(expect)); \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 memset(output, 0xff, sizeof(expect)); \

sizeof(output)
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 HVX_Vector *hvx_output =3D (HVX_Vector *)&= output[0]; \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&= ;buffer0[0]; \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&= ;buffer1[0]; \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 *hvx_output =3D \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 Q6_V##type_res##_##vop##_V##type= _arg##V##type_arg(hvx_buffer0, \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 hvx_b= uffer1); \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / = bytes_##type_res; i++) { \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 expect[0].type_res[i] =3D \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 raw_##type_res(op(= float_##type_arg(buffer0[0].type_arg[i]), \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 float_##type_arg(buffer1[0].t= ype_arg[i]))); \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 } \

Put th= is in a loop over the input buffers to get more input values.=C2=A0 Then ch= ange the second argument to check_output below.
=C2=A0
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 check_output_##type_res(__LINE__, 1); \
+=C2=A0 =C2=A0 }
+
+#define SUM(X, Y, DEF_NAN) CHECK_NAN((X) + (Y), DEF_NAN)
+#define SUB(X, Y, DEF_NAN) CHECK_NAN((X) - (Y), DEF_NAN)
+#define MULT(X, Y, DEF_NAN) CHECK_NAN((X) * (Y), DEF_NAN)
+
+#define SUM_SF(X, Y) SUM(X, Y, NAN_SF)
+#define SUM_HF(X, Y) SUM(X, Y, NAN_HF)
+#define SUB_SF(X, Y) SUB(X, Y, NAN_SF)
+#define SUB_HF(X, Y) SUB(X, Y, NAN_HF)
+#define MULT_SF(X, Y) MULT(X, Y, NAN_SF)
+#define MULT_HF(X, Y) MULT(X, Y, NAN_HF)
+
+DEF_TEST_OP_2(vadd, SUM_SF, sf, sf);
+DEF_TEST_OP_2(vadd, SUM_HF, hf, hf);
+DEF_TEST_OP_2(vsub, SUB_SF, sf, sf);
+DEF_TEST_OP_2(vsub, SUB_HF, hf, hf);
+DEF_TEST_OP_2(vmpy, MULT_SF, sf, sf);
+DEF_TEST_OP_2(vmpy, MULT_HF, hf, hf);
+
+/*************************************************************************= *****
+ * Other tests
+ *************************************************************************= ****/
+
+void test_vdmpy_sf_hf(bool acc)
+{
+=C2=A0 =C2=A0 HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0];
+=C2=A0 =C2=A0 HVX_Vector hvx_buffer0 =3D *(HVX_Vector *)&buffer0[0]; +=C2=A0 =C2=A0 HVX_Vector hvx_buffer1 =3D *(HVX_Vector *)&buffer1[0]; +
+=C2=A0 =C2=A0 uint32_t PREFIL_VAL =3D 0x111222;
+=C2=A0 =C2=A0 memset(expect, 0xff, sizeof(expect));
+=C2=A0 =C2=A0 *hvx_output =3D Q6_V_vsplat_R(PREFIL_VAL);
+
+=C2=A0 =C2=A0 if (!acc) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 *hvx_output =3D Q6_Vsf_vdmpy_VhfVhf(hvx_buffer= 0, hvx_buffer1);
+=C2=A0 =C2=A0 } else {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 *hvx_output =3D Q6_Vsf_vdmpyacc_VsfVhfVhf(*hvx= _output, hvx_buffer0,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 hvx_buffer1);
+=C2=A0 =C2=A0 }
+
+=C2=A0 =C2=A0 for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float a1 =3D float_hf_to_sf(float_hf(buffer0[0= ].hf[2 * i + 1]));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float a2 =3D float_hf_to_sf(float_hf(buffer0[0= ].hf[2 * i]));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float a3 =3D float_hf_to_sf(float_hf(buffer1[0= ].hf[2 * i + 1]));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float a4 =3D float_hf_to_sf(float_hf(buffer1[0= ].hf[2 * i]));
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 float prev =3D acc ? float_sf(PREFIL_VAL) : 0;=
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 expect[0].sf[i] =3D raw_sf(CHECK_NAN((a1 * a3)= + (a2 * a4) + prev, NAN_SF));
+=C2=A0 =C2=A0 }

Put this into a loop a= lso.
=C2=A0
+
+=C2=A0 =C2=A0 /* add/sub */
+=C2=A0 =C2=A0 test_vadd_sf_sf();
+=C2=A0 =C2=A0 test_vadd_hf_hf();
+=C2=A0 =C2=A0 test_vsub_sf_sf();
+=C2=A0 =C2=A0 test_vsub_hf_hf();
+
+=C2=A0 =C2=A0 /* multiply */
+=C2=A0 =C2=A0 test_vmpy_sf_sf();
+=C2=A0 =C2=A0 test_vmpy_hf_hf();
+
+=C2=A0 =C2=A0 /* dot product */
+=C2=A0 =C2=A0 test_vdmpy_sf_hf(false);
+=C2=A0 =C2=A0 test_vdmpy_sf_hf(true);
+
+=C2=A0 =C2=A0 puts(err ? "FAIL" : "PASS");
+=C2=A0 =C2=A0 return err ? 1 : 0;
+}
diff --git a/tests/tcg/hexagon/fp_hvx_disabled.c b/tests/tcg/hexagon/fp_hvx= _disabled.c
new file mode 100644
index 0000000000..af409ab8d2
--- /dev/null
+++ b/tests/tcg/hexagon/fp_hvx_disabled.c
@@ -0,0 +1,32 @@
+/*
+ *=C2=A0 Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries= .
+ *
+ *=C2=A0 SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <hexagon_types.h>
+#include <hvx_hexagon_protos.h>
+
+int err;
+#include "hvx_misc.h"
+
+int main(void)
+{
+=C2=A0 =C2=A0 asm volatile("r0 =3D #0xff\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"v0 =3D= vsplat(r0)\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"vmem(%= 1 + #0) =3D v0\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"r1 =3D= #0x1\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"v1 =3D= vsplat(r1)\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"v2 =3D= vsplat(r1)\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"v0.sf = =3D vadd(v1.sf, v2.sf)\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0"vmem(%= 0 + #0) =3D v0\n"
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0:
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0: "r&qu= ot;(output), "r"(expect)
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0: "r0&q= uot;, "r1", "v0", "v1", "v2", "= ;memory");

Add a test where the re= sult is used in a .new context.
=C2=A0
+
+=C2=A0 =C2=A0 check_output_w(__LINE__, 1);
+=C2=A0 =C2=A0 puts(err ? "FAIL" : "PASS");
+=C2=A0 =C2=A0 return err ? 1 : 0;
+}

--0000000000004b774c064dc9d6b8--