Re: [PATCH 06/13] target/hexagon: add v68 HVX IEEE float misc insns

[Taylor Simpson <ltaylorsimpson@gmail.com>]

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On Mon, Mar 23, 2026 at 7:15 AM Matheus Tavares Bernardino <
matheus.bernardino@oss.qualcomm.com> wrote:

> Add HVX IEEE floating-point miscellaneous instructions:
> - vassign_fp (vfmv): vector move
> - vfneg_hf, vfneg_sf: vector floating-point negate
> - vabs_hf, vabs_sf: vector absolute value
>
> Signed-off-by: Matheus Tavares Bernardino <
> matheus.bernardino@oss.qualcomm.com>
> ---
>  target/hexagon/mmvec/kvx_ieee.h              |  3 +++
>  target/hexagon/imported/mmvec/encode_ext.def |  7 +++++++
>  target/hexagon/imported/mmvec/ext.idef       | 14 ++++++++++++++
>  3 files changed, 24 insertions(+)
>
> diff --git a/target/hexagon/mmvec/kvx_ieee.h
> b/target/hexagon/mmvec/kvx_ieee.h
> index 78f546eb8e..263feb7e94 100644
> --- a/target/hexagon/mmvec/kvx_ieee.h
> +++ b/target/hexagon/mmvec/kvx_ieee.h
> @@ -13,6 +13,9 @@
>  #define FP32_DEF_NAN      0x7FFFFFFF
>  #define FP16_DEF_NAN      0x7FFF
>
> +#define signF32UI(a) ((bool)((uint32_t)(a) >> 31))
> +#define signF16UI(a) ((bool)((uint16_t)(a) >> 15))
>

Use softfloat routines here
    !float32_is_neg
    !float16_is_neg

Actually, these aren't needed.  See below.


> diff --git a/target/hexagon/imported/mmvec/ext.idef
> b/target/hexagon/imported/mmvec/ext.idef
> index 43153366b1..5ef5baa404 100644
> --- a/target/hexagon/imported/mmvec/ext.idef
> +++ b/target/hexagon/imported/mmvec/ext.idef
> @@ -3018,6 +3018,20 @@
> ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf=vmax(Vu32.hf,Vv32.hf)", \
>  ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=vmin(Vu32.hf,Vv32.hf)", \
>      "Vector min of hf input", VdV.hf[i] = qf_min_hf(VuV.hf[i], VvV.hf[i],
> &env->fp_status))
>
> +/* IEEE FP move, negate, abs instructions */
> +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vassign_fp, "Vd32.w=vfmv(Vu32.w)", \
> +    "Vector IEEE move", VdV.w[i]  = VuV.w[i])
> +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfneg_hf, "Vd32.hf=vfneg(Vu32.hf)", \
> +    "Vector IEEE neg: hf", VdV.hf[i] = (VuV.hf[i] ^ 0x8000))
>

Use softfloat routines
    VdV.hf[i] = float16_set_sign(VuV.hf[i], float16_is_neg(VuV.hf[i]) ? 1 :
0)


> +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfneg_sf, "Vd32.sf=vfneg(Vu32.sf)", \
> +    "Vector IEEE neg: sf", VdV.sf[i] = (VuV.sf[i] ^ 0x80000000))
>

Ditto, but float32_


> +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf,  "Vd32.hf=vabs(Vu32.hf)", \
> +    "Vector IEEE abs: hf", \
> +    VdV.hf[i] = ((signF16UI(VuV.hf[i])) ? (VuV.hf[i] ^ 0x8000) :
> VuV.hf[i]))
>

Use softfloat routines
    VdV.hf[i] = float16_abs(VuV.hf[i])


> +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf,  "Vd32.sf=vabs(Vu32.sf)", \
> +    "Vector IEEE abs: sf", \
> +    VdV.sf[i] = ((signF32UI(VuV.sf[i])) ? (VuV.sf[i] ^ 0x80000000) :
> VuV.sf[i]))
>

Ditto, but float32_

Thanks,
Taylor

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