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Mon, 23 Mar 2026 14:08:34 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Taylor Simpson Date: Mon, 23 Mar 2026 15:08:23 -0600 X-Gm-Features: AaiRm51keyiIZXVyQtP_ewSungcH02C9ENtN0XC1WnsgCCF7pfBG9ecvr68hOCA Message-ID: Subject: Re: [PATCH 06/13] target/hexagon: add v68 HVX IEEE float misc insns To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="0000000000000c9e46064db77035" Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000000c9e46064db77035 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:15=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > Add HVX IEEE floating-point miscellaneous instructions: > - vassign_fp (vfmv): vector move > - vfneg_hf, vfneg_sf: vector floating-point negate > - vabs_hf, vabs_sf: vector absolute value > > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > target/hexagon/mmvec/kvx_ieee.h | 3 +++ > target/hexagon/imported/mmvec/encode_ext.def | 7 +++++++ > target/hexagon/imported/mmvec/ext.idef | 14 ++++++++++++++ > 3 files changed, 24 insertions(+) > > diff --git a/target/hexagon/mmvec/kvx_ieee.h > b/target/hexagon/mmvec/kvx_ieee.h > index 78f546eb8e..263feb7e94 100644 > --- a/target/hexagon/mmvec/kvx_ieee.h > +++ b/target/hexagon/mmvec/kvx_ieee.h > @@ -13,6 +13,9 @@ > #define FP32_DEF_NAN 0x7FFFFFFF > #define FP16_DEF_NAN 0x7FFF > > +#define signF32UI(a) ((bool)((uint32_t)(a) >> 31)) > +#define signF16UI(a) ((bool)((uint16_t)(a) >> 15)) > Use softfloat routines here !float32_is_neg !float16_is_neg Actually, these aren't needed. See below. > diff --git a/target/hexagon/imported/mmvec/ext.idef > b/target/hexagon/imported/mmvec/ext.idef > index 43153366b1..5ef5baa404 100644 > --- a/target/hexagon/imported/mmvec/ext.idef > +++ b/target/hexagon/imported/mmvec/ext.idef > @@ -3018,6 +3018,20 @@ > ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf=3Dvmax(Vu32.hf,Vv32.hf)",= \ > ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvmin(Vu32.hf,Vv32.hf)"= , \ > "Vector min of hf input", VdV.hf[i] =3D qf_min_hf(VuV.hf[i], VvV.hf[= i], > &env->fp_status)) > > +/* IEEE FP move, negate, abs instructions */ > +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vassign_fp, "Vd32.w=3Dvfmv(Vu32.w)"= , \ > + "Vector IEEE move", VdV.w[i] =3D VuV.w[i]) > +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfneg_hf, "Vd32.hf=3Dvfneg(Vu32.hf)= ", \ > + "Vector IEEE neg: hf", VdV.hf[i] =3D (VuV.hf[i] ^ 0x8000)) > Use softfloat routines VdV.hf[i] =3D float16_set_sign(VuV.hf[i], float16_is_neg(VuV.hf[i]) ? 1= : 0) > +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfneg_sf, "Vd32.sf=3Dvfneg(Vu32.sf)= ", \ > + "Vector IEEE neg: sf", VdV.sf[i] =3D (VuV.sf[i] ^ 0x80000000)) > Ditto, but float32_ > +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf, "Vd32.hf=3Dvabs(Vu32.hf)"= , \ > + "Vector IEEE abs: hf", \ > + VdV.hf[i] =3D ((signF16UI(VuV.hf[i])) ? (VuV.hf[i] ^ 0x8000) : > VuV.hf[i])) > Use softfloat routines VdV.hf[i] =3D float16_abs(VuV.hf[i]) > +ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf, "Vd32.sf=3Dvabs(Vu32.sf)"= , \ > + "Vector IEEE abs: sf", \ > + VdV.sf[i] =3D ((signF32UI(VuV.sf[i])) ? (VuV.sf[i] ^ 0x80000000) : > VuV.sf[i])) > Ditto, but float32_ Thanks, Taylor --0000000000000c9e46064db77035 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23,= 2026 at 7:15=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= > wrote:
Add = HVX IEEE floating-point miscellaneous instructions:
- vassign_fp (vfmv): vector move
- vfneg_hf, vfneg_sf: vector floating-point negate
- vabs_hf, vabs_sf: vector absolute value

Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm= .com>
---
=C2=A0target/hexagon/mmvec/kvx_ieee.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 3 +++
=C2=A0target/hexagon/imported/mmvec/encode_ext.def |=C2=A0 7 +++++++
=C2=A0target/hexagon/imported/mmvec/ext.idef=C2=A0 =C2=A0 =C2=A0 =C2=A0| 14= ++++++++++++++
=C2=A03 files changed, 24 insertions(+)

diff --git a/target/hexagon/mmvec/kvx_ieee.h b/target/hexagon/mmvec/kvx_iee= e.h
index 78f546eb8e..263feb7e94 100644
--- a/target/hexagon/mmvec/kvx_ieee.h
+++ b/target/hexagon/mmvec/kvx_ieee.h
@@ -13,6 +13,9 @@
=C2=A0#define FP32_DEF_NAN=C2=A0 =C2=A0 =C2=A0 0x7FFFFFFF
=C2=A0#define FP16_DEF_NAN=C2=A0 =C2=A0 =C2=A0 0x7FFF

+#define signF32UI(a) ((bool)((uint32_t)(a) >> 31))
+#define signF16UI(a) ((bool)((uint16_t)(a) >> 15))
<= div>
Use softfloat routines here
=C2=A0 =C2=A0 !flo= at32_is_neg
=C2=A0 =C2=A0 !float16_is_neg

Actually, these aren't needed.=C2=A0 See below.
=C2=A0
diff --git a/target/hexa= gon/imported/mmvec/ext.idef b/target/hexagon/imported/mmvec/ext.idef
index 43153366b1..5ef5baa404 100644
--- a/target/hexagon/imported/mmvec/ext.idef
+++ b/target/hexagon/imported/mmvec/ext.idef
@@ -3018,6 +3018,20 @@ ITERATOR_INSN_ANY_SLOT_2SRC(16,vmax_hf,"Vd32.hf= =3Dvmax(Vu32.hf,Vv32.hf)", \
=C2=A0ITERATOR_INSN_ANY_SLOT_2SRC(16,vmin_hf,"Vd32.hf=3Dvmin(Vu32.hf,V= v32.hf)", \
=C2=A0 =C2=A0 =C2=A0"Vector min of hf input", VdV.hf[i] =3D qf_mi= n_hf(VuV.hf[i], VvV.hf[i], &env->fp_status))

+/* IEEE FP move, negate, abs instructions */
+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vassign_fp, "Vd32.w=3Dvfmv(Vu32.= w)", \
+=C2=A0 =C2=A0 "Vector IEEE move", VdV.w[i]=C2=A0 =3D VuV.w[i]) +ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vfneg_hf, "Vd32.hf=3Dvfneg(Vu32.= hf)", \
+=C2=A0 =C2=A0 "Vector IEEE neg: hf", VdV.hf[i] =3D (VuV.hf[i] ^ = 0x8000))

Use softfloat routines
=C2=A0 =C2=A0 VdV.hf[i] =3D float16_set_sign(VuV.hf[i], float16_is_neg(V= uV.hf[i]) ? 1 : 0)
=C2=A0
+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vfneg_sf, "Vd32.sf=3Dvfneg(Vu32.= sf)", \
+=C2=A0 =C2=A0 "Vector IEEE neg: sf", VdV.sf[i] =3D (VuV.sf[i] ^ = 0x80000000))

Ditto, but float32_
<= div>=C2=A0
+ITERATOR_INSN_IEEE_FP_16_32_LATE(16, vabs_hf,=C2=A0 "Vd32.hf=3Dvabs(V= u32.hf)", \
+=C2=A0 =C2=A0 "Vector IEEE abs: hf", \
+=C2=A0 =C2=A0 VdV.hf[i] =3D ((signF16UI(VuV.hf[i])) ? (VuV.hf[i] ^ 0x8000)= : VuV.hf[i]))

Use softfloat routines
=C2=A0 =C2=A0 VdV.hf[i] =3D float16_abs(VuV.hf[i])
=C2= =A0
+ITERATOR_INSN_IEEE_FP_16_32_LATE(32, vabs_sf,=C2=A0 "Vd32.sf=3Dvabs(V= u32.sf)", \
+=C2=A0 =C2=A0 "Vector IEEE abs: sf", \
+=C2=A0 =C2=A0 VdV.sf[i] =3D ((signF32UI(VuV.sf[i])) ? (VuV.sf[i] ^ 0x80000= 000) : VuV.sf[i]))

Ditto, but float32_<= /div>

Thanks,
Taylor
=C2=A0

=C2=A0
--0000000000000c9e46064db77035--