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Mon, 23 Mar 2026 15:03:17 -0700 (PDT) MIME-Version: 1.0 References: <003328f47c0b5e286ef06ba55cc9734e7bba4af8.1774271525.git.matheus.bernardino@oss.qualcomm.com> In-Reply-To: <003328f47c0b5e286ef06ba55cc9734e7bba4af8.1774271525.git.matheus.bernardino@oss.qualcomm.com> From: Taylor Simpson Date: Mon, 23 Mar 2026 16:03:05 -0600 X-Gm-Features: AaiRm53BCrIlKvdfJs6O2y4bs98CHHYyAWTxBfNwlEj0IjhEeathpS3b3Bufj2w Message-ID: Subject: Re: [PATCH 09/13] target/hexagon: add v73 HVX IEEE bfloat16 insns To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="000000000000b418ab064db83357" Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000b418ab064db83357 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > Add HVX IEEE bfloat16 (bf16) instructions: > > Arithmetic operations: > - V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output > - V6_vmpy_sf_bf: multiply bf16 widening to sf output > - V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output > > Min/Max operations: > - V6_vmin_bf, V6_vmax_bf: bf16 min/max > > Comparison operations: > - V6_vgtbf: greater-than compare > - V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants > > Conversion operations: > - V6_vcvt_bf_sf: convert sf to bf16 > > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > target/hexagon/mmvec/kvx_ieee.h | 36 +++++++++++ > target/hexagon/mmvec/macros.h | 5 ++ > target/hexagon/mmvec/mmvec.h | 1 + > target/hexagon/mmvec/kvx_ieee.c | 3 + > target/hexagon/imported/mmvec/encode_ext.def | 15 +++++ > target/hexagon/imported/mmvec/ext.idef | 64 ++++++++++++++++++++ > 6 files changed, 124 insertions(+) > > diff --git a/target/hexagon/mmvec/kvx_ieee.h > b/target/hexagon/mmvec/kvx_ieee.h > index 8a6816f6b3..eb670d4ec3 100644 > --- a/target/hexagon/mmvec/kvx_ieee.h > +++ b/target/hexagon/mmvec/kvx_ieee.h > @@ -80,4 +80,40 @@ int16_t conv_hf_h(int16_t a, float_status *fp_status); > int32_t conv_w_sf(uint32_t a, float_status *fp_status); > int16_t conv_h_hf(uint16_t a, float_status *fp_status); > > +/* IEEE BFloat instructions */ > + > +#define fp_mult_sf_bf(A, B) \ > + fp_mult_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) << 16, > &env->fp_status) > +#define fp_add_sf_bf(A, B) \ > + fp_add_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) << 16, > &env->fp_status) > +#define fp_sub_sf_bf(A, B) \ > + fp_sub_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) << 16, > &env->fp_status) > Can we use softfloat routine bfloat16_to_float32 instead of shifting by 16? > + > +uint32_t fp_mult_sf_bf_acc(uint16_t op1, uint16_t op2, uint32_t acc, > + float_status *fp_status); > + > +#define bf_to_sf(A) (((uint32_t)(A)) << 16) > Ditto > + > +#define fp_min_bf(A, B) ({ \ > + uint32_t _bf_res =3D fp_min_sf(bf_to_sf(A), bf_to_sf(B), > &env->fp_status); \ > + (uint16_t)((_bf_res >> 16) & 0xffff); \ > float32_to_bfloat16 > +}) > + > +#define fp_max_bf(A, B) ({ \ > + uint32_t _bf_res =3D fp_max_sf(bf_to_sf(A), bf_to_sf(B), > &env->fp_status); \ > + (uint16_t)((_bf_res >> 16) & 0xffff); \ > Ditto > +}) > + > +static inline uint16_t sf_to_bf(int32_t A) > +{ > + uint32_t rslt =3D A; > + if ((rslt & 0x1FFFF) =3D=3D 0x08000) { > + /* do not round up if exactly .5 and even already */ > + } else if ((rslt & 0x8000) =3D=3D 0x8000) { > + rslt +=3D 0x8000; /* rounding to nearest number */ > + } > + rslt =3D float32_is_any_nan(A) ? FP32_DEF_NAN : rslt; > + return rslt >> 16; > +} > float32_to_bfloat16 > + > #endif > diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.= h > index c342507d1a..b70996578e 100644 > --- a/target/hexagon/mmvec/macros.h > +++ b/target/hexagon/mmvec/macros.h > @@ -25,6 +25,9 @@ > #include "accel/tcg/probe.h" > #include "mmvec/kvx_ieee.h" > > +#define fBFLOAT() > +#define fCVI_VX_NO_TMP_LD() > + > #ifndef QEMU_GENERATE > #define VdV (*(MMVector *restrict)(VdV_void)) > #define VsV (*(MMVector *restrict)(VsV_void)) > @@ -366,4 +369,6 @@ > (int16_t)(A) > (int16_t)(B) : \ > float16_compare((A), (B), &env->fp_status) =3D=3D float_relation_gre= ater) > > +#define fCMPGT_BF(A, B) fCMPGT_SF(((int)A) << 16, ((int)B) << 16) > bfloat16_to_float32 > + > #endif > diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h > index eaedfe0d6d..9d8d57c7c6 100644 > --- a/target/hexagon/mmvec/mmvec.h > +++ b/target/hexagon/mmvec/mmvec.h > @@ -40,6 +40,7 @@ typedef union { > int8_t b[MAX_VEC_SIZE_BYTES / 1]; > int32_t sf[MAX_VEC_SIZE_BYTES / 4]; /* single float (32-bit) */ > int16_t hf[MAX_VEC_SIZE_BYTES / 2]; /* half float (16-bit) */ > + uint16_t bf[MAX_VEC_SIZE_BYTES / 2]; /* bfloat16 */ > Consider using bfloat16 Also float32 for sf and float16 for hf. > } MMVector; Thanks, Taylor --000000000000b418ab064db83357 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23,= 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= > wrote:
Add = HVX IEEE bfloat16 (bf16) instructions:

Arithmetic operations:
- V6_vadd_sf_bf, V6_vsub_sf_bf: add/sub bf16 widening to sf output
- V6_vmpy_sf_bf: multiply bf16 widening to sf output
- V6_vmpy_sf_bf_acc: multiply-accumulate bf16 widening to sf output

Min/Max operations:
- V6_vmin_bf, V6_vmax_bf: bf16 min/max

Comparison operations:
- V6_vgtbf: greater-than compare
- V6_vgtbf_and, V6_vgtbf_or, V6_vgtbf_xor: predicate variants

Conversion operations:
- V6_vcvt_bf_sf: convert sf to bf16

Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm= .com>
---
=C2=A0target/hexagon/mmvec/kvx_ieee.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 | 36 +++++++++++
=C2=A0target/hexagon/mmvec/macros.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 |=C2=A0 5 ++
=C2=A0target/hexagon/mmvec/mmvec.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
=C2=A0target/hexagon/mmvec/kvx_ieee.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 3 +
=C2=A0target/hexagon/imported/mmvec/encode_ext.def | 15 +++++
=C2=A0target/hexagon/imported/mmvec/ext.idef=C2=A0 =C2=A0 =C2=A0 =C2=A0| 64= ++++++++++++++++++++
=C2=A06 files changed, 124 insertions(+)

diff --git a/target/hexagon/mmvec/kvx_ieee.h b/target/hexagon/mmvec/kvx_iee= e.h
index 8a6816f6b3..eb670d4ec3 100644
--- a/target/hexagon/mmvec/kvx_ieee.h
+++ b/target/hexagon/mmvec/kvx_ieee.h
@@ -80,4 +80,40 @@ int16_t conv_hf_h(int16_t a, float_status *fp_status); =C2=A0int32_t conv_w_sf(uint32_t a, float_status *fp_status);
=C2=A0int16_t conv_h_hf(uint16_t a, float_status *fp_status);

+/* IEEE BFloat instructions */
+
+#define fp_mult_sf_bf(A, B) \
+=C2=A0 =C2=A0 fp_mult_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) &= lt;< 16, &env->fp_status)
+#define fp_add_sf_bf(A, B) \
+=C2=A0 =C2=A0 fp_add_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) &l= t;< 16, &env->fp_status)
+#define fp_sub_sf_bf(A, B) \
+=C2=A0 =C2=A0 fp_sub_sf_sf(((uint32_t)(A)) << 16, ((uint32_t)(B)) &l= t;< 16, &env->fp_status)

Can = we use softfloat routine bfloat16_to_float32 instead of shifting by 16?
=C2=A0
+
+uint32_t fp_mult_sf_bf_acc(uint16_t op1, uint16_t op2, uint32_t acc,
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0float_status *fp_status);
+
+#define bf_to_sf(A) (((uint32_t)(A)) << 16)
Ditto
=C2=A0
+
+#define fp_min_bf(A, B) ({ \
+=C2=A0 =C2=A0 uint32_t _bf_res =3D fp_min_sf(bf_to_sf(A), bf_to_sf(B), &am= p;env->fp_status); \
+=C2=A0 =C2=A0 (uint16_t)((_bf_res >> 16) & 0xffff); \

float32_to_bfloat16
=C2=A0
+})
+
+#define fp_max_bf(A, B) ({ \
+=C2=A0 =C2=A0 uint32_t _bf_res =3D fp_max_sf(bf_to_sf(A), bf_to_sf(B), &am= p;env->fp_status); \
+=C2=A0 =C2=A0 (uint16_t)((_bf_res >> 16) & 0xffff); \

Ditto
=C2=A0
+})
+
+static inline uint16_t sf_to_bf(int32_t A)
+{
+=C2=A0 =C2=A0 uint32_t rslt =3D A;
+=C2=A0 =C2=A0 if ((rslt & 0x1FFFF) =3D=3D 0x08000) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 /* do not round up if exactly .5 and even alre= ady */
+=C2=A0 =C2=A0 } else if ((rslt & 0x8000) =3D=3D 0x8000) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 rslt +=3D 0x8000; /* rounding to nearest numbe= r */
+=C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 rslt =3D float32_is_any_nan(A) ? FP32_DEF_NAN : rslt;
+=C2=A0 =C2=A0 return rslt >> 16;
+}

float32_to_bfloat16
=C2=A0=
+
=C2=A0#endif
diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h<= br> index c342507d1a..b70996578e 100644
--- a/target/hexagon/mmvec/macros.h
+++ b/target/hexagon/mmvec/macros.h
@@ -25,6 +25,9 @@
=C2=A0#include "accel/tcg/probe.h"
=C2=A0#include "mmvec/kvx_ieee.h"

+#define fBFLOAT()
+#define fCVI_VX_NO_TMP_LD()
+
=C2=A0#ifndef QEMU_GENERATE
=C2=A0#define VdV=C2=A0 =C2=A0 =C2=A0 (*(MMVector *restrict)(VdV_void))
=C2=A0#define VsV=C2=A0 =C2=A0 =C2=A0 (*(MMVector *restrict)(VsV_void))
@@ -366,4 +369,6 @@
=C2=A0 =C2=A0 =C2=A0(int16_t)(A) > (int16_t)(B) : \
=C2=A0 =C2=A0 =C2=A0float16_compare((A), (B), &env->fp_status) =3D= =3D float_relation_greater)

+#define fCMPGT_BF(A, B) fCMPGT_SF(((int)A) << 16, ((int)B) << = 16)

bfloat16_to_float32
=C2= =A0
+
=C2=A0#endif
diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h index eaedfe0d6d..9d8d57c7c6 100644
--- a/target/hexagon/mmvec/mmvec.h
+++ b/target/hexagon/mmvec/mmvec.h
@@ -40,6 +40,7 @@ typedef union {
=C2=A0 =C2=A0 =C2=A0int8_t=C2=A0 =C2=A0 b[MAX_VEC_SIZE_BYTES / 1];
=C2=A0 =C2=A0 =C2=A0int32_t=C2=A0 sf[MAX_VEC_SIZE_BYTES / 4];=C2=A0 =C2=A0/= * single float (32-bit) */
=C2=A0 =C2=A0 =C2=A0int16_t=C2=A0 hf[MAX_VEC_SIZE_BYTES / 2];=C2=A0 =C2=A0/= * half float (16-bit) */
+=C2=A0 =C2=A0 uint16_t bf[MAX_VEC_SIZE_BYTES / 2];=C2=A0 =C2=A0/* bfloat16= */

Consider using bfloat16
<= br>
Also float32 for sf and float16 for hf.
=C2=A0
=C2=A0} MMVector;

=C2=A0Thanks,
T= aylor=C2=A0
--000000000000b418ab064db83357--