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Tue, 24 Mar 2026 18:15:13 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Taylor Simpson Date: Tue, 24 Mar 2026 19:15:00 -0600 X-Gm-Features: AaiRm50EfpfaHG57M0L7EXWlwLjLy61CIl18WfOWgwW3Upmc0vwFdvBU7A9Fki4 Message-ID: Subject: Re: [PATCH 07/13] target/hexagon: add v68 HVX IEEE float conversion insns To: Matheus Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="000000000000f6b05a064dceff84" Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000f6b05a064dceff84 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Mar 24, 2026 at 3:04=E2=80=AFPM Matheus Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > On Mon, Mar 23, 2026 at 6:26=E2=80=AFPM Taylor Simpson > wrote: > > > > > > > > On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> wrote: > >> > >> > >> diff --git a/target/hexagon/mmvec/kvx_ieee.c > b/target/hexagon/mmvec/kvx_ieee.c > >> index 33621a15f3..bbeec09707 100644 > >> --- a/target/hexagon/mmvec/kvx_ieee.c > >> +++ b/target/hexagon/mmvec/kvx_ieee.c > >> @@ -131,3 +131,101 @@ uint16_t qf_min_hf(uint16_t a1, uint16_t a2, > float_status *fp_status) > >> if (float16_is_pos_nan(f2) || float16_is_neg_nan(f1)) return a1; > >> return fp_min_hf(a1, a2, fp_status); > >> } > >> + > >> +uint16_t f16_to_uh(uint16_t op1, float_status *fp_status) > >> +{ > >> + return float16_to_uint16_scalbn(make_float16(op1), > >> + float_round_nearest_even, > > > > > > Does HVX always use this rounding mode? The scalar core uses the > rounding mode in USR. > > Yeah, almost always this mode, with the exception of some > instructions. It's not configurable via USR (or anything else). > You can set that in the hvx_fp_status, and the softfloat lib will handle it from there. > > >> + > >> +int32_t conv_w_sf(uint32_t a, float_status *fp_status) > >> +{ > >> + float_status scratch_fpst =3D {}; > >> + const float32 W_MAX =3D int32_to_float32(INT32_MAX, &scratch_fpst= ); > >> + const float32 W_MIN =3D int32_to_float32(INT32_MIN, &scratch_fpst= ); > >> + float32 f1 =3D make_float32(a); > >> + > >> + if (float32_is_any_nan(f1) || float32_is_infinity(f1) || > >> + float32_le_quiet(W_MAX, f1, fp_status) || > >> + float32_le_quiet(f1, W_MIN, fp_status)) { > >> + return float32_is_neg(f1) ? INT32_MIN : INT32_MAX; > >> + } > > > > > > Does float32_to_int32 handle these checks? > > Hmm, I don't think they are exactly the same. For example, > float32_to_int32 will return INT32_MAX for any NAN. But the hexagon > implementation here returns INT32_MIN for negative NAN. > Look around in the softfloat code - especially fields in float_status. Ths scalar core has a few exceptions, but not alot. --000000000000f6b05a064dceff84 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Tue, Mar 24,= 2026 at 3:04=E2=80=AFPM Matheus Bernardino <matheus.bernardino@oss.qualcomm.com> wro= te:
On Mon, Mar = 23, 2026 at 6:26=E2=80=AFPM Taylor Simpson <ltaylorsimpson@gmail.com> wrote: >
>
>
> On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino <= ;m= atheus.bernardino@oss.qualcomm.com> wrote:
>>
>>
>> diff --git a/target/hexagon/mmvec/kvx_ieee.c b/target/hexagon/mmve= c/kvx_ieee.c
>> index 33621a15f3..bbeec09707 100644
>> --- a/target/hexagon/mmvec/kvx_ieee.c
>> +++ b/target/hexagon/mmvec/kvx_ieee.c
>> @@ -131,3 +131,101 @@ uint16_t qf_min_hf(uint16_t a1, uint16_t a2,= float_status *fp_status)
>>=C2=A0 =C2=A0 =C2=A0 if (float16_is_pos_nan(f2) || float16_is_neg_n= an(f1)) return a1;
>>=C2=A0 =C2=A0 =C2=A0 return fp_min_hf(a1, a2, fp_status);
>>=C2=A0 }
>> +
>> +uint16_t f16_to_uh(uint16_t op1, float_status *fp_status)
>> +{
>> +=C2=A0 =C2=A0 return float16_to_uint16_scalbn(make_float16(op1),<= br> >> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 float_round_= nearest_even,
>
>
> Does HVX always use this rounding mode?=C2=A0 The scalar core uses the= rounding mode in USR.

Yeah, almost always this mode, with the exception of some
instructions. It's not configurable via USR (or anything else).

You can set that in the hvx_fp_status, and the= softfloat lib=C2=A0will handle=C2=A0it from there.
=C2=A0
<= blockquote class=3D"gmail_quote" style=3D"margin:0px 0px 0px 0.8ex;border-l= eft:1px solid rgb(204,204,204);padding-left:1ex">
>> +
>> +int32_t conv_w_sf(uint32_t a, float_status *fp_status)
>> +{
>> +=C2=A0 =C2=A0 float_status scratch_fpst =3D {};
>> +=C2=A0 =C2=A0 const float32 W_MAX =3D int32_to_float32(INT32_MAX,= &scratch_fpst);
>> +=C2=A0 =C2=A0 const float32 W_MIN =3D int32_to_float32(INT32_MIN,= &scratch_fpst);
>> +=C2=A0 =C2=A0 float32 f1 =3D make_float32(a);
>> +
>> +=C2=A0 =C2=A0 if (float32_is_any_nan(f1) || float32_is_infinity(f= 1) ||
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 float32_le_quiet(W_MAX, f1, fp_status= ) ||
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 float32_le_quiet(f1, W_MIN, fp_status= )) {
>> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return float32_is_neg(f1) ? INT32_MIN= : INT32_MAX;
>> +=C2=A0 =C2=A0 }
>
>
> Does float32_to_int32 handle these checks?

Hmm, I don't think they are exactly the same. For example,
float32_to_int32 will return INT32_MAX for any NAN. But the hexagon
implementation here returns INT32_MIN for negative NAN.

Look around in the softfloat code - especially fields in f= loat_status.=C2=A0 Ths scalar core has a few exceptions, but not alot.
=C2=A0
--000000000000f6b05a064dceff84--