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Tue, 24 Mar 2026 12:37:55 -0700 (PDT) MIME-Version: 1.0 References: <76a65d4bf9062558256d29756e9e847d18692be9.1774271525.git.matheus.bernardino@oss.qualcomm.com> In-Reply-To: <76a65d4bf9062558256d29756e9e847d18692be9.1774271525.git.matheus.bernardino@oss.qualcomm.com> From: Taylor Simpson Date: Tue, 24 Mar 2026 13:37:44 -0600 X-Gm-Features: AaiRm52AasZXXiThThEEDgbVFmIXRy_rgBXc1i_srszpPpOfepAIHreEk1dR0gY Message-ID: Subject: Re: [PATCH 13/13] tests/hexagon: add tests for v68 HVX IEEE float comparisons To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="000000000000bb16fa064dca49a4" Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --000000000000bb16fa064dca49a4 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > tests/tcg/hexagon/hex_test.h | 1 + > tests/tcg/hexagon/fp_hvx_cmp.c | 58 +++++++++++++++++++++++++++++++ > tests/tcg/hexagon/Makefile.target | 3 ++ > 3 files changed, 62 insertions(+) > create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c > > diff --git a/tests/tcg/hexagon/fp_hvx_cmp.c > b/tests/tcg/hexagon/fp_hvx_cmp.c > new file mode 100644 > index 0000000000..e925c973f3 > --- /dev/null > +++ b/tests/tcg/hexagon/fp_hvx_cmp.c > @@ -0,0 +1,58 @@ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + * > + * SPDX-License-Identifier: GPL-2.0-or-later > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#if __HEXAGON_ARCH__ > 75 > +#error "After v75, compiler will replace some FP HVX instructions." > +#endif > + > +int err; > +#include "hvx_misc.h" > +#include "hex_test.h" > + > +#define TEST_CMP(VAL1, VAL2, EXP) do { \ > + ((MMVector *)&buffers[0])->sf[index] =3D VAL1; \ > + ((MMVector *)&buffers[1])->sf[index] =3D VAL2; \ > + expect[0].w[index] =3D EXP ? 0xffffffff : 0; \ > + index++; \ > +} while (0) > + > +int main(void) > +{ > + HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0]; > + HVX_Vector buffers[2], true_vec, false_vec; > + HVX_VectorPred pred; > + int index =3D 0; > + > + memset(&buffers, 0, sizeof(buffers)); > + memset(expect, 0, sizeof(expect)); > + memset(&true_vec, 0xff, sizeof(true_vec)); > + memset(&false_vec, 0, sizeof(false_vec)); > + > + TEST_CMP(raw_sf(2.2), raw_sf(2.1), true); > + TEST_CMP(raw_sf(2.2), raw_sf(2.2), false); > + TEST_CMP(raw_sf(0), raw_sf(-2.2), true); > + TEST_CMP(SF_SNaN, SF_SNaN, false); > + TEST_CMP(SF_INF, SF_INF_neg, true); > + TEST_CMP(SF_INF_neg, SF_INF, false); > + TEST_CMP(SF_SNaN, SF_QNaN, false); > + TEST_CMP(SF_QNaN, SF_SNaN, true); > + TEST_CMP(SF_QNaN, SF_QNaN_neg, true); > + > + pred =3D Q6_Q_vcmp_gt_VsfVsf(buffers[0], buffers[1]); > + *hvx_output =3D Q6_V_vmux_QVV(pred, true_vec, false_vec); > + > + check_output_sf(__LINE__, 1); > + > + puts(err ? "FAIL" : "PASS"); > + return err ? 1 : 0; > +} > We should add some half-float tests as well as and/or/xor versions. Also, check the FP flags. Finally, we should add another test for bfloat. Thanks, Taylor --000000000000bb16fa064dca49a4 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23,= 2026 at 7:16=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= > wrote:
Sign= ed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= >
---
=C2=A0tests/tcg/hexagon/hex_test.h=C2=A0 =C2=A0 =C2=A0 |=C2=A0 1 +
=C2=A0tests/tcg/hexagon/fp_hvx_cmp.c=C2=A0 =C2=A0 | 58 ++++++++++++++++++++= +++++++++++
=C2=A0tests/tcg/hexagon/Makefile.target |=C2=A0 3 ++
=C2=A03 files changed, 62 insertions(+)
=C2=A0create mode 100644 tests/tcg/hexagon/fp_hvx_cmp.c

diff --git a/tests/tcg/hexagon/fp_hvx_cmp.c b/tests/tcg/hexagon/fp_hvx_= cmp.c
new file mode 100644
index 0000000000..e925c973f3
--- /dev/null
+++ b/tests/tcg/hexagon/fp_hvx_cmp.c
@@ -0,0 +1,58 @@
+/*
+ *=C2=A0 Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries= .
+ *
+ *=C2=A0 SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include <hexagon_types.h>
+#include <hvx_hexagon_protos.h>
+
+#if __HEXAGON_ARCH__ > 75
+#error "After v75, compiler will replace some FP HVX instructions.&qu= ot;
+#endif
+
+int err;
+#include "hvx_misc.h"
+#include "hex_test.h"
+
+#define TEST_CMP(VAL1, VAL2, EXP) do { \
+=C2=A0 =C2=A0 ((MMVector *)&buffers[0])->sf[index] =3D VAL1; \
+=C2=A0 =C2=A0 ((MMVector *)&buffers[1])->sf[index] =3D VAL2; \
+=C2=A0 =C2=A0 expect[0].w[index] =3D EXP ? 0xffffffff : 0; \
+=C2=A0 =C2=A0 index++; \
+} while (0)
+
+int main(void)
+{
+=C2=A0 =C2=A0 HVX_Vector *hvx_output =3D (HVX_Vector *)&output[0];
+=C2=A0 =C2=A0 HVX_Vector buffers[2], true_vec, false_vec;
+=C2=A0 =C2=A0 HVX_VectorPred pred;
+=C2=A0 =C2=A0 int index =3D 0;
+
+=C2=A0 =C2=A0 memset(&buffers, 0, sizeof(buffers));
+=C2=A0 =C2=A0 memset(expect, 0, sizeof(expect));
+=C2=A0 =C2=A0 memset(&true_vec, 0xff, sizeof(true_vec));
+=C2=A0 =C2=A0 memset(&false_vec, 0, sizeof(false_vec));
+
+=C2=A0 =C2=A0 TEST_CMP(raw_sf(2.2),=C2=A0 raw_sf(2.1),=C2=A0 true);
+=C2=A0 =C2=A0 TEST_CMP(raw_sf(2.2),=C2=A0 raw_sf(2.2),=C2=A0 false);
+=C2=A0 =C2=A0 TEST_CMP(raw_sf(0),=C2=A0 =C2=A0 raw_sf(-2.2), true);
+=C2=A0 =C2=A0 TEST_CMP(SF_SNaN,=C2=A0 =C2=A0 =C2=A0 SF_SNaN,=C2=A0 =C2=A0 = =C2=A0 false);
+=C2=A0 =C2=A0 TEST_CMP(SF_INF,=C2=A0 =C2=A0 =C2=A0 =C2=A0SF_INF_neg,=C2=A0= =C2=A0true);
+=C2=A0 =C2=A0 TEST_CMP(SF_INF_neg,=C2=A0 =C2=A0SF_INF,=C2=A0 =C2=A0 =C2=A0= =C2=A0false);
+=C2=A0 =C2=A0 TEST_CMP(SF_SNaN,=C2=A0 =C2=A0 =C2=A0 SF_QNaN,=C2=A0 =C2=A0 = =C2=A0 false);
+=C2=A0 =C2=A0 TEST_CMP(SF_QNaN,=C2=A0 =C2=A0 =C2=A0 SF_SNaN,=C2=A0 =C2=A0 = =C2=A0 true);
+=C2=A0 =C2=A0 TEST_CMP(SF_QNaN,=C2=A0 =C2=A0 =C2=A0 SF_QNaN_neg,=C2=A0 tru= e);
+
+=C2=A0 =C2=A0 pred =3D Q6_Q_vcmp_gt_VsfVsf(buffers[0], buffers[1]);
+=C2=A0 =C2=A0 *hvx_output =3D Q6_V_vmux_QVV(pred, true_vec, false_vec); +
+=C2=A0 =C2=A0 check_output_sf(__LINE__, 1);
+
+=C2=A0 =C2=A0 puts(err ? "FAIL" : "PASS");
+=C2=A0 =C2=A0 return err ? 1 : 0;
+}

We should add some half-float tests = as well as and/or/xor versions.
Also, check the FP flags.
Finally, we should add another test for bfloat.

Thanks,
Taylor

--000000000000bb16fa064dca49a4--