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From: Taylor Simpson <ltaylorsimpson@gmail.com>
To: Brian Cain <brian.cain@oss.qualcomm.com>
Cc: Matheus Bernardino <matheus.bernardino@oss.qualcomm.com>,
	qemu-devel@nongnu.org, ale@rev.ng,  anjo@rev.ng,
	marco.liebel@oss.qualcomm.com, philmd@linaro.org,
	 quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com
Subject: Re: [PATCH 03/13] target/hexagon/cpu: add HVX IEEE FP extension
Date: Tue, 24 Mar 2026 13:46:40 -0600	[thread overview]
Message-ID: <CAATN3NqwCo5D+6SPepoW2h-qwgdRSg9CDW_MRKWejHeSqvBqkA@mail.gmail.com> (raw)
In-Reply-To: <CAEqNhNa2ner=c6Zb-TYVTJ7Foa=quSRYG3MVHn6kpmG4OCGfxg@mail.gmail.com>

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On Tue, Mar 24, 2026 at 1:21 PM Brian Cain <brian.cain@oss.qualcomm.com>
wrote:

>
>
> On Tue, Mar 24, 2026 at 1:48 PM Taylor Simpson <ltaylorsimpson@gmail.com>
> wrote:
>
>>
>>
>> On Tue, Mar 24, 2026 at 10:52 AM Matheus Bernardino <
>> matheus.bernardino@oss.qualcomm.com> wrote:
>>
>>> On Mon, Mar 23, 2026 at 4:33 PM Taylor Simpson <ltaylorsimpson@gmail.com>
>>> wrote:
>>> >
>>> >
>>> >
>>> > On Mon, Mar 23, 2026 at 7:15 AM Matheus Tavares Bernardino <
>>> matheus.bernardino@oss.qualcomm.com> wrote:
>>> >>
>>> >> This flag will be used to control the HVX IEEE float instructions,
>>> which
>>> >> are only available at some Hexagon cores. When unavailable, the
>>> >> instruction is essentially treated as a no-op.
>>> >>
>>> >> Signed-off-by: Matheus Tavares Bernardino <
>>> matheus.bernardino@oss.qualcomm.com>
>>> >> ---
>>> >>  target/hexagon/cpu.h             |  1 +
>>> >>  target/hexagon/translate.h       |  1 +
>>> >>  target/hexagon/attribs_def.h.inc |  3 +++
>>> >>  target/hexagon/cpu.c             |  1 +
>>> >>  target/hexagon/decode.c          | 22 ++++++++++++++++++++++
>>> >>  target/hexagon/translate.c       |  1 +
>>> >>  6 files changed, 29 insertions(+)
>>> >>
>>> >>
>>> >> diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
>>> >> index dbc9c630e8..d832a64a17 100644
>>> >> --- a/target/hexagon/decode.c
>>> >> +++ b/target/hexagon/decode.c
>>> >> @@ -696,6 +696,18 @@ static bool pkt_has_write_conflict(Packet *pkt)
>>> >>      return !bitmap_empty(conflict, 32);
>>> >>  }
>>> >>
>>> >> +static void convert_to_nop(Insn *insn)
>>> >> +{
>>> >> +    bool is_endloop = insn->is_endloop;
>>> >> +    memset(insn, 0, sizeof(*insn));
>>> >> +    insn->opcode = A2_nop;
>>> >> +    insn->new_read_idx = -1;
>>> >> +    insn->dest_idx = -1;
>>> >> +    insn->generate = opcode_genptr[insn->opcode];
>>> >> +    insn->iclass = 0b111;
>>> >> +    insn->is_endloop = is_endloop;
>>> >> +}
>>> >> +
>>> >>  /*
>>> >>   * decode_packet
>>> >>   * Decodes packet with given words
>>> >> @@ -746,6 +758,16 @@ int decode_packet(DisasContext *ctx, int
>>> max_words, const uint32_t *words,
>>> >>          /* Ran out of words! */
>>> >>          return 0;
>>> >>      }
>>> >> +
>>> >> +    /* Disable HVX IEEE instruction if extension is disabled. */
>>> >> +    if (!ctx->ieee_fp_extension) {
>>> >> +        for (i = 0; i < num_insns; i++) {
>>> >> +            if (GET_ATTRIB(pkt->insn[i].opcode, A_HVX_IEEE_FP)) {
>>> >> +                convert_to_nop(&pkt->insn[i]);
>>> >> +            }
>>> >> +        }
>>> >> +    }
>>> >> +
>>> >
>>> >
>>> > Better to leave the instruction alone and turn it into a nop by not
>>> generating any TCG.
>>> >
>>> > That way, the disassembly (-d in_asm) will still show what's actually
>>> in the binary.  You could add the check in gen_tcg_funcs.py.
>>> >
>>> > You could also consider adding some sort of marker in the disassembly
>>> to indicate that the flag is needed for the instruction to do anything.
>>>
>>> Ah, good idea. Will do both for the next round, thanks.
>>>
>>
>> Note that we'll need to be careful with packets that use the result
>> vector in a .new context.  For example
>>     { V0.sf = vadd(V1.sf,V2.sf)
>>       vmem(R19+#0x0) = V0.new }
>> The problem is that the store wants to read the value from future_VRegs.
>> However, if the vadd is  nop, there is junk in future_VRegs.  So, we'll
>> either have to get the store to read from the real VRegs or have the vadd
>> copy the old value of the destination into the future_VRegs value.  The
>> first option will be more efficient because it will avoid the vector copy.
>>
>>
> For the sake of ease-of-verification we'll want to do whatever the ISS
> does.  It's not very obvious to me what it would do in this packet context
> based on the description of the nop-like behavior, but we'll follow the
> ISS' lead.  In practical terms the garbage in future_VRegs is probably just
> as bad or good as any other value - if you bothered to execute this packet
> on the target w/o support for this opcode you probably don't care much
> about the result.
>

I'll be interested to know what the ISS and hardware do in this case.

Thanks,
Taylor

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  reply	other threads:[~2026-03-24 19:47 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-23 13:15 [PATCH 00/13] hexagon: add missing HVX float instructions Matheus Tavares Bernardino
2026-03-23 13:15 ` [PATCH 01/13] tests/docker: Update hexagon cross toolchain to 22.1.0 Matheus Tavares Bernardino
2026-03-23 13:15 ` [PATCH 02/13] target/hexagon: fix incorrect/too-permissive HVX encodings Matheus Tavares Bernardino
2026-03-23 19:21   ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 03/13] target/hexagon/cpu: add HVX IEEE FP extension Matheus Tavares Bernardino
2026-03-23 19:32   ` Taylor Simpson
2026-03-24 16:52     ` Matheus Bernardino
2026-03-24 18:48       ` Taylor Simpson
2026-03-24 19:20         ` Brian Cain
2026-03-24 19:46           ` Taylor Simpson [this message]
2026-03-23 13:15 ` [PATCH 04/13] target/hexagon: add v68 HVX IEEE float arithmetic insns Matheus Tavares Bernardino
2026-03-23 20:28   ` Taylor Simpson
2026-03-24 19:30     ` Matheus Bernardino
2026-03-24 19:51       ` Taylor Simpson
2026-03-24 19:59         ` Matheus Bernardino
2026-03-25  1:18           ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 05/13] target/hexagon: add v68 HVX IEEE float min/max insns Matheus Tavares Bernardino
2026-03-23 20:47   ` Taylor Simpson
2026-03-24 20:15     ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 06/13] target/hexagon: add v68 HVX IEEE float misc insns Matheus Tavares Bernardino
2026-03-23 21:08   ` Taylor Simpson
2026-03-24 20:25     ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 07/13] target/hexagon: add v68 HVX IEEE float conversion insns Matheus Tavares Bernardino
2026-03-23 21:25   ` Taylor Simpson
2026-03-24 21:04     ` Matheus Bernardino
2026-03-25  1:15       ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 08/13] target/hexagon: add v68 HVX IEEE float compare insns Matheus Tavares Bernardino
2026-03-23 21:42   ` Taylor Simpson
2026-03-26 13:00     ` Matheus Bernardino
2026-03-23 13:15 ` [PATCH 09/13] target/hexagon: add v73 HVX IEEE bfloat16 insns Matheus Tavares Bernardino
2026-03-23 22:03   ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 10/13] tests/hexagon: add tests for v68 HVX IEEE float arithmetics Matheus Tavares Bernardino
2026-03-24 19:05   ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 11/13] tests/hexagon: add tests for v68 HVX IEEE float min/max Matheus Tavares Bernardino
2026-03-24 19:07   ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 12/13] tests/hexagon: add tests for v68 HVX IEEE float conversions Matheus Tavares Bernardino
2026-03-24 19:30   ` Taylor Simpson
2026-03-23 13:15 ` [PATCH 13/13] tests/hexagon: add tests for v68 HVX IEEE float comparisons Matheus Tavares Bernardino
2026-03-24 19:37   ` Taylor Simpson

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