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Mon, 23 Mar 2026 12:33:02 -0700 (PDT) MIME-Version: 1.0 References: <4f6bd77ba6c6c07c8796e805ce6e50539bde260e.1774271525.git.matheus.bernardino@oss.qualcomm.com> In-Reply-To: <4f6bd77ba6c6c07c8796e805ce6e50539bde260e.1774271525.git.matheus.bernardino@oss.qualcomm.com> From: Taylor Simpson Date: Mon, 23 Mar 2026 13:32:49 -0600 X-Gm-Features: AaiRm50BhrJUPSGcCLNIem94bo2nrq1uim_vbpX3K9_edu-u6uRQL5e2sLpjup0 Message-ID: Subject: Re: [PATCH 03/13] target/hexagon/cpu: add HVX IEEE FP extension To: Matheus Tavares Bernardino Cc: qemu-devel@nongnu.org, brian.cain@oss.qualcomm.com, ale@rev.ng, anjo@rev.ng, marco.liebel@oss.qualcomm.com, philmd@linaro.org, quic_mburton@quicinc.com, sid.manning@oss.qualcomm.com Content-Type: multipart/alternative; boundary="0000000000005f8cd0064db61a46" Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=ltaylorsimpson@gmail.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org --0000000000005f8cd0064db61a46 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Mar 23, 2026 at 7:15=E2=80=AFAM Matheus Tavares Bernardino < matheus.bernardino@oss.qualcomm.com> wrote: > This flag will be used to control the HVX IEEE float instructions, which > are only available at some Hexagon cores. When unavailable, the > instruction is essentially treated as a no-op. > > Signed-off-by: Matheus Tavares Bernardino < > matheus.bernardino@oss.qualcomm.com> > --- > target/hexagon/cpu.h | 1 + > target/hexagon/translate.h | 1 + > target/hexagon/attribs_def.h.inc | 3 +++ > target/hexagon/cpu.c | 1 + > target/hexagon/decode.c | 22 ++++++++++++++++++++++ > target/hexagon/translate.c | 1 + > 6 files changed, 29 insertions(+) > > > diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c > index dbc9c630e8..d832a64a17 100644 > --- a/target/hexagon/decode.c > +++ b/target/hexagon/decode.c > @@ -696,6 +696,18 @@ static bool pkt_has_write_conflict(Packet *pkt) > return !bitmap_empty(conflict, 32); > } > > +static void convert_to_nop(Insn *insn) > +{ > + bool is_endloop =3D insn->is_endloop; > + memset(insn, 0, sizeof(*insn)); > + insn->opcode =3D A2_nop; > + insn->new_read_idx =3D -1; > + insn->dest_idx =3D -1; > + insn->generate =3D opcode_genptr[insn->opcode]; > + insn->iclass =3D 0b111; > + insn->is_endloop =3D is_endloop; > +} > + > /* > * decode_packet > * Decodes packet with given words > @@ -746,6 +758,16 @@ int decode_packet(DisasContext *ctx, int max_words, > const uint32_t *words, > /* Ran out of words! */ > return 0; > } > + > + /* Disable HVX IEEE instruction if extension is disabled. */ > + if (!ctx->ieee_fp_extension) { > + for (i =3D 0; i < num_insns; i++) { > + if (GET_ATTRIB(pkt->insn[i].opcode, A_HVX_IEEE_FP)) { > + convert_to_nop(&pkt->insn[i]); > + } > + } > + } > + > Better to leave the instruction alone and turn it into a nop by not generating any TCG. That way, the disassembly (-d in_asm) will still show what's actually in the binary. You could add the check in gen_tcg_funcs.py. You could also consider adding some sort of marker in the disassembly to indicate that the flag is needed for the instruction to do anything. Thanks, Taylor --0000000000005f8cd0064db61a46 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


On Mon, Mar 23,= 2026 at 7:15=E2=80=AFAM Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com= > wrote:
This= flag will be used to control the HVX IEEE float instructions, which
are only available at some Hexagon cores. When unavailable, the
instruction is essentially treated as a no-op.

Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm= .com>
---
=C2=A0target/hexagon/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 1 +
=C2=A0target/hexagon/translate.h=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
=C2=A0target/hexagon/attribs_def.h.inc |=C2=A0 3 +++
=C2=A0target/hexagon/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= =C2=A0 1 +
=C2=A0target/hexagon/decode.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 22 ++++++= ++++++++++++++++
=C2=A0target/hexagon/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
=C2=A06 files changed, 29 insertions(+)


diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c
index dbc9c630e8..d832a64a17 100644
--- a/target/hexagon/decode.c
+++ b/target/hexagon/decode.c
@@ -696,6 +696,18 @@ static bool pkt_has_write_conflict(Packet *pkt)
=C2=A0 =C2=A0 =C2=A0return !bitmap_empty(conflict, 32);
=C2=A0}

+static void convert_to_nop(Insn *insn)
+{
+=C2=A0 =C2=A0 bool is_endloop =3D insn->is_endloop;
+=C2=A0 =C2=A0 memset(insn, 0, sizeof(*insn));
+=C2=A0 =C2=A0 insn->opcode =3D A2_nop;
+=C2=A0 =C2=A0 insn->new_read_idx =3D -1;
+=C2=A0 =C2=A0 insn->dest_idx =3D -1;
+=C2=A0 =C2=A0 insn->generate =3D opcode_genptr[insn->opcode];
+=C2=A0 =C2=A0 insn->iclass =3D 0b111;
+=C2=A0 =C2=A0 insn->is_endloop =3D is_endloop;
+}
+
=C2=A0/*
=C2=A0 * decode_packet
=C2=A0 * Decodes packet with given words
@@ -746,6 +758,16 @@ int decode_packet(DisasContext *ctx, int max_words, co= nst uint32_t *words,
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0/* Ran out of words! */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
=C2=A0 =C2=A0 =C2=A0}
+
+=C2=A0 =C2=A0 /* Disable HVX IEEE instruction if extension is disabled. */=
+=C2=A0 =C2=A0 if (!ctx->ieee_fp_extension) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 for (i =3D 0; i < num_insns; i++) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (GET_ATTRIB(pkt->insn[i].o= pcode, A_HVX_IEEE_FP)) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 convert_to_nop(&am= p;pkt->insn[i]);
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 }
+=C2=A0 =C2=A0 }
+

Better to leave the instruction alone= and turn it into a nop by not generating any TCG.

That way, the disassembly (-d in_asm) will still show what's actually = in the binary.=C2=A0 You could add the check in gen_tcg_funcs.py.

You could also consider adding some sort of marker in the d= isassembly to indicate that the flag is needed for the instruction to do an= ything.

Thanks,
Taylor

--0000000000005f8cd0064db61a46--