qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: francisco iglesias <frasse.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>,
	Edgar Iglesias <edgar.iglesias@xilinx.com>
Subject: [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA
Date: Fri, 25 May 2018 18:24:09 +0200	[thread overview]
Message-ID: <CAAYMZQtBJ5TuNz44R7ussH69CSRoKH2ZPaEfTPOHwBNFkNmVCw@mail.gmail.com> (raw)
In-Reply-To: <CAFEAcA-RkvGiorW3AqJg=DGebmeSdKtcbdXb=oLe2aEN4M5Nzw@mail.gmail.com>

On Friday, 25 May 2018, Peter Maydell <peter.maydell@linaro.org> wrote:

> On 18 May 2018 at 18:19, Peter Maydell <peter.maydell@linaro.org> wrote:
> > From: Francisco Iglesias <frasse.iglesias@gmail.com>
> >
> > Add a model of the generic DMA found on Xilinx ZynqMP.
>
> Hi; the latest Coverity run finds a couple of issues in this code:
>
>
> > +static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
> > +{
> > +    XlnxZDMA *s = XLNX_ZDMA(opaque);
> > +    RegisterInfo *r = &s->regs_info[addr / 4];
> > +
> > +    if (!r->data) {
> > +        qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
> > +                 object_get_canonical_path(OBJECT(s)),
> > +                 addr);
>
> object_get_canonical_path() returns a string that the caller
> takes ownership of, so you have to g_free() it when you've
> finished with it. (CID 1391294)
>
> > +        ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
> > +        zdma_ch_imr_update_irq(s);
> > +        return 0;
> > +    }
> > +    return register_read(r, ~0, NULL, false);
> > +}
> > +
> > +static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
> > +                      unsigned size)
> > +{
> > +    XlnxZDMA *s = XLNX_ZDMA(opaque);
> > +    RegisterInfo *r = &s->regs_info[addr / 4];
> > +
> > +    if (!r->data) {
> > +        qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64
> "\n",
> > +                 object_get_canonical_path(OBJECT(s)),
> > +                 addr, value);
>
> Similarly here. (CID 1391293)
>
> > +        ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
> > +        zdma_ch_imr_update_irq(s);
> > +        return;
> > +    }
> > +    register_write(r, value, ~0, NULL, false);
> > +}
>
> Could you write a patch that adds the missing g_free()s, please?
>
> Hi Peter,

Absolutly! I'll be back with a patch with the corrections asap! Thank you
for explaining the issues!

Brst regards,
Francisco Iglesias





> thanks
> -- PMM
>

  reply	other threads:[~2018-05-25 16:24 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-18 17:19 [Qemu-devel] [PULL 00/32] target-arm queue Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 01/32] target/arm: Add "ARM_CP_NO_GDB" as a new bit field for ARMCPRegInfo type Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 02/32] target/arm: Add "_S" suffix to the secure version of a sysreg Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 03/32] target/arm: Add the XML dynamic generation Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 04/32] xlnx-zdma: Add a model of the Xilinx ZynqMP generic DMA Peter Maydell
2018-05-25 13:51   ` Peter Maydell
2018-05-25 16:24     ` francisco iglesias [this message]
2018-05-25 13:57   ` Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 05/32] xlnx-zynqmp: Connect the ZynqMP GDMA and ADMA Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 06/32] hw/arm/smmuv3: Fix Coverity issue in smmuv3_record_event Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 07/32] hw/arm/smmu-common: Fix coverity issue in get_block_pte_address Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 08/32] target/arm: Introduce translate-a64.h Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 09/32] target/arm: Add SVE decode skeleton Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 10/32] target/arm: Implement SVE Bitwise Logical - Unpredicated Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 11/32] target/arm: Implement SVE load vector/predicate Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 12/32] target/arm: Implement SVE predicate test Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 13/32] target/arm: Implement SVE Predicate Logical Operations Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 14/32] target/arm: Implement SVE Predicate Misc Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 16/32] target/arm: Implement SVE Integer Reduction Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 17/32] target/arm: Implement SVE bitwise shift by immediate (predicated) Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated) Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 19/32] target/arm: Implement SVE bitwise shift by wide elements (predicated) Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 20/32] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 21/32] target/arm: Implement SVE Integer Multiply-Add Group Peter Maydell
2018-05-18 17:19 ` [Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 23/32] target/arm: Implement SVE Index Generation Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 25/32] target/arm: Implement SVE Bitwise Shift - Unpredicated Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 26/32] target/arm: Implement SVE Compute Vector Address Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 27/32] target/arm: Implement SVE floating-point exponential accelerator Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 28/32] target/arm: Implement SVE floating-point trig select coefficient Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 29/32] target/arm: Implement SVE Element Count Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 30/32] target/arm: Implement SVE Bitwise Immediate Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 31/32] target/arm: Implement SVE Integer Wide Immediate - Predicated Group Peter Maydell
2018-05-18 17:20 ` [Qemu-devel] [PULL 32/32] target/arm: Implement SVE Permute - Extract Group Peter Maydell
2018-05-18 18:48 ` [Qemu-devel] [PULL 00/32] target-arm queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAAYMZQtBJ5TuNz44R7ussH69CSRoKH2ZPaEfTPOHwBNFkNmVCw@mail.gmail.com \
    --to=frasse.iglesias@gmail.com \
    --cc=edgar.iglesias@xilinx.com \
    --cc=peter.maydell@linaro.org \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).