From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,HTML_MESSAGE,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07A12C433E2 for ; Mon, 31 Aug 2020 21:39:42 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B4EF22083E for ; Mon, 31 Aug 2020 21:39:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B4EF22083E Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:60924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kCrWe-00012r-U6 for qemu-devel@archiver.kernel.org; Mon, 31 Aug 2020 17:39:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47608) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kCrDn-0004Yt-Ql for qemu-devel@nongnu.org; Mon, 31 Aug 2020 17:20:12 -0400 Received: from mail-qv1-f67.google.com ([209.85.219.67]:34239) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kCrDl-0001ZL-QR for qemu-devel@nongnu.org; Mon, 31 Aug 2020 17:20:11 -0400 Received: by mail-qv1-f67.google.com with SMTP id m14so1852323qvt.1 for ; Mon, 31 Aug 2020 14:20:09 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=SjgWIsZuXFPtl3+R2qxjhWR5+JINNygoUiofAL6ajIc=; b=ZOsh/vZxd8acJPvYPrgYUvjAkXkbpMybkbvJxcc/lBTMY4PdCv0QMq5TSTxDGRUxMr OdS9eg/Z+uPGzn/ArWmbuXwdibFPutfI4ttTccdYZwEks3jjkzVYMHy4VWyHU4ja2OiW AuIvYluHr5FxssE0ewsYA/2peEB8VShSG+heSiQ/SQHSGdnWkpbvNkB3RTUaSyNcNxkd 0Lm31P8t+JlHtOdY4za3ygKfnhFlETvUHhSi+TT5o45o5ivTN5BNrWLC4UUg0lxoR7eY TUwsi1HGqxSeSjtsRgzhOjgkI6q32JSw9CHDG4YcmM+OGI6BXGK2pFrgpF+dgx1364Ml q41Q== X-Gm-Message-State: AOAM531LMVgiOKC4EDX9rfL+Vt8rN9U1pANciDEt5+tVitckj3Hsck+u Cvcrs0e51aq7XEmNVdwL3bEGFLJ8zgQFq8e1XxI= X-Google-Smtp-Source: ABdhPJzbXTwMlKCHEK9iUVx0HIKGKaf7MKsvxxkEwEHnCKErFwPwMBCpDNQqTCRvluxbUlFBHfThGY3vxLQnHPj+TJA= X-Received: by 2002:ad4:59d0:: with SMTP id el16mr3028940qvb.116.1598908808980; Mon, 31 Aug 2020 14:20:08 -0700 (PDT) MIME-Version: 1.0 References: <20200828141929.77854-1-richard.henderson@linaro.org> <20200828141929.77854-10-richard.henderson@linaro.org> In-Reply-To: <20200828141929.77854-10-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Date: Mon, 31 Aug 2020 22:51:42 +0200 Message-ID: Subject: Re: [PATCH v2 09/76] target/microblaze: Split out FSR from env->sregs To: Richard Henderson Content-Type: multipart/alternative; boundary="000000000000966d6e05ae32f728" Received-SPF: pass client-ip=209.85.219.67; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-qv1-f67.google.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/31 17:15:50 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , "qemu-devel@nongnu.org Developers" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" --000000000000966d6e05ae32f728 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Le ven. 28 ao=C3=BBt 2020 16:25, Richard Henderson a =C3=A9crit : > Continue eliminating the sregs array in favor of individual members. > Does not correct the width of FSR, yet. > > Signed-off-by: Richard Henderson > Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- > target/microblaze/cpu.h | 1 + > linux-user/microblaze/cpu_loop.c | 4 ++-- > target/microblaze/gdbstub.c | 4 ++-- > target/microblaze/op_helper.c | 8 ++++---- > target/microblaze/translate.c | 6 ++++-- > 5 files changed, 13 insertions(+), 10 deletions(-) > > diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h > index 7d94af43ed..bcafef99b0 100644 > --- a/target/microblaze/cpu.h > +++ b/target/microblaze/cpu.h > @@ -240,6 +240,7 @@ struct CPUMBState { > uint64_t msr; > uint64_t ear; > uint64_t esr; > + uint64_t fsr; > uint64_t sregs[14]; > float_status fp_status; > /* Stack protectors. Yes, it's a hw feature. */ > diff --git a/linux-user/microblaze/cpu_loop.c > b/linux-user/microblaze/cpu_loop.c > index c10e3e0261..da5e98b784 100644 > --- a/linux-user/microblaze/cpu_loop.c > +++ b/linux-user/microblaze/cpu_loop.c > @@ -96,10 +96,10 @@ void cpu_loop(CPUMBState *env) > case ESR_EC_FPU: > info.si_signo =3D TARGET_SIGFPE; > info.si_errno =3D 0; > - if (env->sregs[SR_FSR] & FSR_IO) { > + if (env->fsr & FSR_IO) { > info.si_code =3D TARGET_FPE_FLTINV; > } > - if (env->sregs[SR_FSR] & FSR_DZ) { > + if (env->fsr & FSR_DZ) { > info.si_code =3D TARGET_FPE_FLTDIV; > } > info._sifields._sigfault._addr =3D 0; > diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c > index 05e22f233d..2634ce49fc 100644 > --- a/target/microblaze/gdbstub.c > +++ b/target/microblaze/gdbstub.c > @@ -71,7 +71,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray > *mem_buf, int n) > val =3D env->esr; > break; > case GDB_FSR: > - val =3D env->sregs[SR_FSR]; > + val =3D env->fsr; > break; > case GDB_BTR: > val =3D env->sregs[SR_BTR]; > @@ -127,7 +127,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t > *mem_buf, int n) > env->esr =3D tmp; > break; > case GDB_FSR: > - env->sregs[SR_FSR] =3D tmp; > + env->fsr =3D tmp; > break; > case GDB_BTR: > env->sregs[SR_BTR] =3D tmp; > diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.= c > index f01cf9be64..ae57d45536 100644 > --- a/target/microblaze/op_helper.c > +++ b/target/microblaze/op_helper.c > @@ -175,19 +175,19 @@ static void update_fpu_flags(CPUMBState *env, int > flags) > int raise =3D 0; > > if (flags & float_flag_invalid) { > - env->sregs[SR_FSR] |=3D FSR_IO; > + env->fsr |=3D FSR_IO; > raise =3D 1; > } > if (flags & float_flag_divbyzero) { > - env->sregs[SR_FSR] |=3D FSR_DZ; > + env->fsr |=3D FSR_DZ; > raise =3D 1; > } > if (flags & float_flag_overflow) { > - env->sregs[SR_FSR] |=3D FSR_OF; > + env->fsr |=3D FSR_OF; > raise =3D 1; > } > if (flags & float_flag_underflow) { > - env->sregs[SR_FSR] |=3D FSR_UF; > + env->fsr |=3D FSR_UF; > raise =3D 1; > } > if (raise > diff --git a/target/microblaze/translate.c b/target/microblaze/translate.= c > index 411c7b6e49..c58c49ea8f 100644 > --- a/target/microblaze/translate.c > +++ b/target/microblaze/translate.c > @@ -1810,7 +1810,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int > flags) > "debug=3D%x imm=3D%x iflags=3D%x fsr=3D%" PRIx64 " " > "rbtr=3D%" PRIx64 "\n", > env->msr, env->esr, env->ear, > - env->debug, env->imm, env->iflags, env->sregs[SR_FSR], > + env->debug, env->imm, env->iflags, env->fsr, > env->sregs[SR_BTR]); > qemu_fprintf(f, "btaken=3D%d btarget=3D%" PRIx64 " mode=3D%s(saved= =3D%s) " > "eip=3D%d ie=3D%d\n", > @@ -1877,8 +1877,10 @@ void mb_tcg_init(void) > tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, ear), > "rear"); > cpu_SR[SR_ESR] =3D > tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), > "resr"); > + cpu_SR[SR_FSR] =3D > + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), > "rfsr"); > > - for (i =3D SR_ESR + 1; i < ARRAY_SIZE(cpu_SR); i++) { > + for (i =3D SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) { > cpu_SR[i] =3D tcg_global_mem_new_i64(cpu_env, > offsetof(CPUMBState, sregs[i]), > special_regnames[i]); > -- > 2.25.1 > > > --000000000000966d6e05ae32f728 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


Le ven. 28 ao=C3=BBt 2020 16:25, Richard Henderson <= ;richard.henderson@linaro.o= rg> a =C3=A9crit=C2=A0:
Cont= inue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org= >

Reviewe= d-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>