Re: [Qemu-devel] [PULL v2 12/12] target/mips: Introduce 32 R5900 multimedia registers

["Philippe Mathieu-Daudé" <f4bug@amsat.org>]

Hi Fredrik and Aleksandar,

On Fri, Jan 18, 2019 at 6:10 PM Aleksandar Markovic
<aleksandar.markovic@rt-rk.com> wrote:
>
> From: Fredrik Noring <noring@nocrew.org>
>
> The 32 R5900 128-bit registers are split into two 64-bit halves:
> the lower halves are the GPRs and the upper halves are accessible
> by the R5900-specific multimedia instructions.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Fredrik Noring <noring@nocrew.org>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
>  target/mips/cpu.h       |  3 +++
>  target/mips/translate.c | 16 ++++++++++++++++
>  2 files changed, 19 insertions(+)
>
> diff --git a/target/mips/cpu.h b/target/mips/cpu.h
> index 21daf50..c4da7df 100644
> --- a/target/mips/cpu.h
> +++ b/target/mips/cpu.h
> @@ -429,6 +429,9 @@ struct TCState {
>
>      float_status msa_fp_status;
>
> +    /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */
> +    uint64_t mmr[32];

FYI using MMI then migrating fails because these registers are not migrated.

> +
>  #define NUMBER_OF_MXU_REGISTERS 16
>      target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
>      target_ulong mxu_cr;
...