From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Alistair Francis <alistair.francis@opensource.wdc.com>
Cc: alistair23@gmail.com,
Richard Henderson <richard.henderson@linaro.org>,
Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org
Subject: Re: [PULL v2 07/35] target/riscv: access cfg structure through DisasContext
Date: Wed, 16 Feb 2022 11:24:23 +0100 [thread overview]
Message-ID: <CAAeLtUA7KCTPCkutpTn2GgpWi2nU_Zidsh1yKf6bFKEQ4CWdpA@mail.gmail.com> (raw)
In-Reply-To: <20220216062912.319738-8-alistair.francis@opensource.wdc.com>
Alistair,
This PULL seems not to include the fixup (which you had intended to
squash into it) for the regression introduced (i.e. the condition
being inverted):
https://patchwork.kernel.org/project/qemu-devel/patch/20220203153946.2676353-1-philipp.tomsich@vrull.eu/
Without that change this will introduce a regression in Zb[abcs]
(i.e., it will be enabled when it shouldn't be, and will be disabled
when it should be on).
Please ignore, if I missed a later stand-alone patch (I just looked at
the series in Patchworks).
Thanks,
Philipp.
On Wed, 16 Feb 2022 at 07:29, Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Philipp Tomsich <philipp.tomsich@vrull.eu>
>
> The Zb[abcs] support code still uses the RISCV_CPU macros to access
> the configuration information (i.e., check whether an extension is
> available/enabled). Now that we provide this information directly
> from DisasContext, we can access this directly via the cfg_ptr field.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Suggested-by: Richard Henderson <richard.henderson@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> Message-Id: <20220202005249.3566542-5-philipp.tomsich@vrull.eu>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
> index 810431a1d6..f9bd3b7ec4 100644
> --- a/target/riscv/insn_trans/trans_rvb.c.inc
> +++ b/target/riscv/insn_trans/trans_rvb.c.inc
> @@ -19,25 +19,25 @@
> */
>
> #define REQUIRE_ZBA(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zba) { \
> + if (ctx->cfg_ptr->ext_zba) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBB(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbb) { \
> + if (ctx->cfg_ptr->ext_zbb) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBC(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbc) { \
> + if (ctx->cfg_ptr->ext_zbc) { \
> return false; \
> } \
> } while (0)
>
> #define REQUIRE_ZBS(ctx) do { \
> - if (!RISCV_CPU(ctx->cs)->cfg.ext_zbs) { \
> + if (ctx->cfg_ptr->ext_zbs) { \
> return false; \
> } \
> } while (0)
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-02-16 10:26 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 6:28 [PULL v2 00/35] riscv-to-apply queue Alistair Francis
2022-02-16 6:28 ` [PULL v2 01/35] include: hw: remove ibex_plic.h Alistair Francis
2022-02-16 6:28 ` [PULL v2 02/35] Allow setting up to 8 bytes with the generic loader Alistair Francis
2022-02-16 6:28 ` [PULL v2 03/35] target/riscv: correct "code should not be reached" for x-rv128 Alistair Francis
2022-02-16 6:28 ` [PULL v2 04/35] target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' Alistair Francis
2022-02-16 6:28 ` [PULL v2 05/35] target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr Alistair Francis
2022-02-16 6:28 ` [PULL v2 06/35] target/riscv: access configuration through cfg_ptr in DisasContext Alistair Francis
2022-02-16 6:28 ` [PULL v2 07/35] target/riscv: access cfg structure through DisasContext Alistair Francis
2022-02-16 10:24 ` Philipp Tomsich [this message]
2022-02-16 22:14 ` Alistair Francis
2022-02-16 6:28 ` [PULL v2 08/35] target/riscv: iterate over a table of decoders Alistair Francis
2022-02-16 6:28 ` [PULL v2 09/35] target/riscv: Add XVentanaCondOps custom extension Alistair Francis
2022-02-16 6:28 ` [PULL v2 10/35] target/riscv: add a MAINTAINERS entry for XVentanaCondOps Alistair Francis
2022-02-16 6:28 ` [PULL v2 11/35] target/riscv: Fix vill field write in vtype Alistair Francis
2022-02-16 6:28 ` [PULL v2 12/35] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode Alistair Francis
2022-02-16 6:28 ` [PULL v2 13/35] target/riscv: Implement SGEIP bit in hip and hie CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 14/35] target/riscv: Implement hgeie and hgeip CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 15/35] target/riscv: Improve delivery of guest external interrupts Alistair Francis
2022-02-16 6:28 ` [PULL v2 16/35] target/riscv: Allow setting CPU feature from machine/device emulation Alistair Francis
2022-02-16 6:28 ` [PULL v2 17/35] target/riscv: Add AIA cpu feature Alistair Francis
2022-02-16 6:28 ` [PULL v2 18/35] target/riscv: Add defines for AIA CSRs Alistair Francis
2022-02-16 6:28 ` [PULL v2 19/35] target/riscv: Allow AIA device emulation to set ireg rmw callback Alistair Francis
2022-02-16 6:28 ` [PULL v2 20/35] target/riscv: Implement AIA local interrupt priorities Alistair Francis
2022-02-16 6:28 ` [PULL v2 21/35] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32 Alistair Francis
2022-02-16 6:28 ` [PULL v2 22/35] target/riscv: Implement AIA hvictl and hviprioX CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 23/35] target/riscv: Implement AIA interrupt filtering CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 24/35] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 25/35] target/riscv: Implement AIA xiselect and xireg CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 26/35] target/riscv: Implement AIA IMSIC interface CSRs Alistair Francis
2022-02-16 6:29 ` [PULL v2 27/35] hw/riscv: virt: Use AIA INTC compatible string when available Alistair Francis
2022-02-16 6:29 ` [PULL v2 28/35] target/riscv: Allow users to force enable AIA CSRs in HART Alistair Francis
2022-02-16 6:29 ` [PULL v2 29/35] hw/intc: Add RISC-V AIA APLIC device emulation Alistair Francis
2022-04-12 14:53 ` Peter Maydell
2022-04-13 23:59 ` Alistair Francis
2022-02-16 6:29 ` [PULL v2 30/35] target/riscv: Ignore reserved bits in PTE for RV64 Alistair Francis
2022-02-16 6:29 ` [PULL v2 31/35] target/riscv: add PTE_A/PTE_D/PTE_U bits check for inner PTE Alistair Francis
2022-02-16 6:29 ` [PULL v2 32/35] target/riscv: add support for svnapot extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 33/35] target/riscv: add support for svinval extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 34/35] target/riscv: add support for svpbmt extension Alistair Francis
2022-02-16 6:29 ` [PULL v2 35/35] docs/system: riscv: Update description of CPU Alistair Francis
2022-02-16 15:29 ` [PULL v2 00/35] riscv-to-apply queue Peter Maydell
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