From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: Alistair Francis <alistair23@gmail.com>
Cc: Alistair Francis <alistair.francis@wdc.com>,
Kito Cheng <kito.cheng@sifive.com>,
Richard Henderson <richard.henderson@linaro.org>,
"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v11 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci
Date: Tue, 28 Sep 2021 17:45:58 +0200 [thread overview]
Message-ID: <CAAeLtUBk3ffamhKaqYsQkCW79Z6Jd+gMH_jAv_NXAVyDPdHOmw@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKM7b9Xz0C7YN7QyARUJSAuDqxWk4VnwHfMB+5tTHGvy4w@mail.gmail.com>
Richard,
On Tue, 28 Sept 2021 at 09:07, Alistair Francis <alistair23@gmail.com> wrote:
>
> On Sun, Sep 12, 2021 at 12:07 AM Philipp Tomsich
> <philipp.tomsich@vrull.eu> wrote:
> >
> > The 1.0.0 version of Zbb does not contain gorc/gorci. Instead, a
> > orc.b instruction (equivalent to the orc.b pseudo-instruction built on
> > gorci from pre-0.93 draft-B) is available, mainly targeting
> > string-processing workloads.
> >
> > This commit adds the new orc.b instruction and removed gorc/gorci.
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> > Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
>
> I'm seeing this warning when building with gcc (GCC) 11.2.1
>
> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg.h:1267:5:
> warning: overflow in conversion from ‘long long unsigned int’ to
> ‘int32_t’ {aka ‘int’} changes value from ‘72340172838076673’ to
> ‘16843009’ [-Woverflow]
> 1267 | (__builtin_constant_p(VECE) \
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1268 | ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1269 | : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1270 | : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1271 | : (VECE) == MO_64 ? (uint64_t)(C) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1272 | : (qemu_build_not_reached_always(), 0)) \
> | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> 1273 | : dup_const(VECE, C))
> | ~~~~~~~~~~~~~~~~~~~~~
> ../target/riscv/insn_trans/trans_rvb.c.inc:301:34: note: in expansion
> of macro ‘dup_const’
> 301 | TCGv ones = tcg_constant_tl(dup_const(MO_8, 0x01));
> | ^~~~~~~~~
> [78/87] Compiling C object
> libqemu-riscv32-linux-user.fa.p/target_riscv_translate.c.o
> In file included from
> /var/mnt/scratch/alistair/software/qemu/include/tcg/tcg-op.h:28,
> from ../target/riscv/translate.c:22:
The dup_const macro is returning an unsigned long long, which probably
should be fixed on the tcg.h-level instead of forcing a cast to target_long
at the call site.
Or should we introduce a dup_const_tl?
Philipp.
next prev parent reply other threads:[~2021-09-28 15:47 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-11 14:00 [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 01/16] target/riscv: Introduce temporary in gen_add_uw() Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 02/16] target/riscv: fix clzw implementation to operate on arg1 Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 03/16] target/riscv: clwz must ignore high bits (use shift-left & changed logic) Philipp Tomsich
2021-09-14 9:15 ` LIU Zhiwei
2021-09-14 10:24 ` Philipp Tomsich
2021-09-15 8:11 ` LIU Zhiwei
2021-09-11 14:00 ` [PATCH v11 04/16] target/riscv: Add x-zba, x-zbb, x-zbc and x-zbs properties Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 05/16] target/riscv: Reassign instructions to the Zba-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 06/16] target/riscv: Remove the W-form instructions from Zbs Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 07/16] target/riscv: Remove shift-one instructions (proposed Zbo in pre-0.93 draft-B) Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 08/16] target/riscv: Reassign instructions to the Zbs-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 09/16] target/riscv: Add instructions of the Zbc-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 10/16] target/riscv: Reassign instructions to the Zbb-extension Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 11/16] target/riscv: Add orc.b instruction for Zbb, removing gorc/gorci Philipp Tomsich
2021-09-28 7:06 ` Alistair Francis
2021-09-28 15:45 ` Philipp Tomsich [this message]
2021-09-28 18:45 ` Richard Henderson
2021-09-28 18:45 ` Philipp Tomsich
2021-09-28 21:00 ` Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 12/16] target/riscv: Add a REQUIRE_32BIT macro Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 13/16] target/riscv: Add rev8 instruction, removing grev/grevi Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 14/16] target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 15/16] target/riscv: Remove RVB (replaced by Zb[abcs]) Philipp Tomsich
2021-09-11 14:00 ` [PATCH v11 16/16] disas/riscv: Add Zb[abcs] instructions Philipp Tomsich
2021-09-23 21:31 ` [PATCH v11 00/16] target/riscv: Update QEmu for Zb[abcs] 1.0.0 Philipp Tomsich
2021-09-24 3:02 ` Alistair Francis
2021-09-27 20:01 ` Vineet Gupta
2021-09-27 20:01 ` Vineet Gupta
2021-09-27 20:23 ` Jim Wilson
2021-09-27 21:54 ` Vineet Gupta
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